AS6C6416-55TIN

AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM REVISION HISTORY AS6C6416-55TIN 48pin TSOP I Revision Description Issue Date July.2017 Rev. 1.0 Initial Issue Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION n Fast access time : 55ns n Low power consumption: Operating current : 12mA (TYP.) Standby current : 12µA(TYP.) n Single 2.7V ~ 3.6V power supply n All inputs and outputs TTL compatible n Fully static operation n Tri-state output n Data byte control : (i) BYTE# fixed to VCC LB# controlled DQ0 ~ DQ7 UB# controlled DQ8 ~ DQ15 (ii) BYTE# fixed to VSS DQ15 used as address pin, while DQ8~DQ14 pins not used n Data retention voltage : 1.2V (MIN.) n ROHS Compliant-Pb free n Package : 48-pin 12mm x 20mm TSOP I The AS6C6416 is a 67,108,864-bit low power CMOS static random access memory organized as 4,194,304 words by 16 bits or 8,388,608 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C6416 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C6416 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS6C6416-55TIN Operating Temperature -40 ~ 85℃ VCC Range Speed 2.7 ~ 3.6V 55ns FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0~A21 /A-1~A21 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# CE2 WE# OE# LB# UB# BYTE# Confidential DECODER I/O DATA CIRCUIT 4096Kx16/8192Kx8 MEMORY ARRAY COLUMN I/O Power Dissipation Standby(ISB1,TYP.) Operating(ICC,TYP.) 12µA 12mA PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A21 Address Inputs(word mode) A-1 - A21 Address Inputs(byte mode) DQ0 - DQ15 Data Inputs/Outputs CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control BYTE# Byte Enable VCC Power Supply VSS Ground CONTROL CIRCUIT - 2 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM PIN CONFIGURATION A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# CE2 A21 UB# LB# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AS6C6416-55TIN XXXXXXXX XXXXXXXX 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0 TSOP I Confidential - 3 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 RATING -0.5 to 4.6 -0.5 to VCC+0.5 UNIT V V TA -40 to 85 ℃ TSTG PD IOUT -65 to 150 1 50 ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE# CE2 H X X L L L L L L L L L X L X H H H H H H H H H X X H H H L H H H H H H L H L H Standby Output Disable Read Write Byte# Read Byte # Write BYTE# OE# I/O OPERATION DQ0-DQ7 DQ8-DQ14 DQ15 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z A-1 DOUT High-Z High-Z High-Z DOUT DOUT DOUT DOUT DOUT High-Z High-Z DIN High-Z DIN DIN DIN DIN DIN SUPPLY CURRENT WE# LB# UB# X X X H H H L L L X X X X X X H H H H H H L L L X X H L X L L H L L H L X X H X L L H L L H L L L L H L L DOUT High-Z A-1 ICC,ICC1 L X L L L DIN High-Z A-1 ICC,ICC1 ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 Notes: 1. H = VIH, L = VIL, X = Don't care. 2. The BYTE# pin has to be tied to VCC to use the device as a 4M x 16 SRAM, and to be tied to VSS as a 8M x 8 SRAM. In the 8M x 8 configuration, Pin 45 is A-1, and both UB# and LB# are tied to VSS, while DQ8 to DQ14 pins are not used. Confidential - 4 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI Output Leakage ILO Current Output High Voltage VOH Output Low Voltage VOL ICC Average Operating Power supply Current ICC1 Standby Power Supply Current ISB1 TEST CONDITION VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS Output Disabled IOH = -1mA IOL = 2mA Cycle time = MIN. CE#≦0.2V and CE2≧VCC-0.2V II/O = 0mA Other pins at 0.2V or VCC-0.2V Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V II/O = 0mA Other pins at 0.2V or VCC-0.2V *5 25℃ CE#≧VCC-0.2V *5 or CE2≦0.2V 40℃ Other pins at 0.2V 70℃ or VCC-0.2V 85℃ MIN. 2.7 2.2 - 0.2 -1 TYP. 3.0 - *4 MAX. UNIT 3.6 V VCC+0.3 V 0.6 V 1 µA -1 - 1 µA 2.2 - 2.7 - 0.4 V V - 12 20 mA - 3 5 mA - 12 12 - 32 36 100 160 µA µA µA µA Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values, measured at VCC = VCC(TYP.) and TA = 25℃, are included for reference only and are not guaranteed or tested. 5. This parameter is measured at VCC=3.0V. CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX. 15 20 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. Confidential - 5 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* AS6C6416-55TIN MIN. MAX. 55 55 55 30 10 5 20 20 10 55 20 10 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW AS6C6416-55TIN MIN. MAX. 55 50 50 0 45 0 25 0 5 20 50 - UNIT ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Confidential - 6 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Confidential - 7 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,4,5) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout tOW High-Z (4) tDW (4) tDH Data Valid Din WRITE CYCLE 2 (CE# and CE2 Controlled) (1,4,5) tWC Address tAW CE# tAS tWR tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din Confidential tDH Data Valid - 8 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5) tWC Address tAW tWR CE# tCW tAS CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Confidential - 9 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention SYMBOL TEST CONDITION VDR CE#≧VCC - 0.2V or CE2≦0.2V Data Retention Current IDR VCC = 1.2V CE# ≧VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V tCDR See Data Retention Waveforms (below) Chip Disable to Data Retention Time Recovery Time 25℃ 40℃ 70℃ 85℃ tR MIN. 1.2 - TYP. 10 10 - MAX. UNIT 3.6 V 32 µA 36 µA 100 µA 160 µA 0 - - ns tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low VCC Data Retention Waveform (1) (CE# controlled) VDR ≠ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≠ Vcc-0.2V VIH Low VCC Data Retention Waveform (2) (CE2 controlled) VDR ≠ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE2 tR CE2 ∝ 0.2V VIL VIL Low VCC Data Retention Waveform (3) (LB#, UB# controlled) VDR ≠ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# Confidential VIH tR LB#,UB# ≠ Vcc-0.2V - 10 of 12 - VIH Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 48-pin 12mm x 20mm TSOP I Package Outline Dimension Confidential - 11 of 12 - Rev.1.0 July 2017 AS6C6416-55TIN 64M Bits(4Mx16) LOW POWER CMOS SRAM ORDERING INFORMATION AS6C SRAM prefix 6416 -55 T Device Number Access Package Option 64 = 64M T=48 pin TSOP I(12x20mm) Time 16 = x16 I Temperature Range I = Industrial (-40 to + 85℃ N N = Lead Free RoHS compliant part XX Packing Type None:Tray TR:Reel Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. 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