AS6C8008-55BIN

JANUARY 2008 January 2007 AS6C8008 X 8 BITCMOS LOW SRAM POWER CMOS SRAM 1024K X 8 BIT SUPER 512K LOW POWER FEATURES GENERAL DESCRIPTION Fast access time : 55ns Low power consumption: Operating current : 30mA (TYP.) Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 1.5V (MIN.) Lead free and green package available Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA The AS6C8008 is a 8,388,608-bit low power CMOS static random access memory organized as 1,048,576 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C8008 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The AS6C8008 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS6C8008(I) Operating Temperature -40 ~ 85℃ Vcc Range 2.7 ~ 5.5V FUNCTIONAL BLOCK DIAGRAM Speed 55ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 6µA(LL) 30mA PIN DESCRIPTION SYMBOL Vcc Vss A0-A19 DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# CE2 WE# OE# CONTROL CIRCUIT JANUARY/2008, V 1.0 1024Kx8 MEMORY R ARAY DESCRIPTION A0 - A19 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE#, CE2 Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection COLUMN I/O Alliance Memory Inc. Page 1 of 11 JANUARY 2008 January 2007 AS6C8008 X 8 BIT LOW POWER CMOS SRAM 1024K X 8 BIT SUPER 512K LOW POWER CMOS SRAM PIN CONFIGURATION 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 CE2 CE# 6 39 A8 NC 7 38 NC NC 8 37 NC DQ0 9 36 DQ7 DQ1 10 35 DQ6 Vcc 11 34 Vss 33 Vcc 32 DQ5 31 DQ4 30 Vss 12 DQ2 13 DQ3 14 NC 15 AS6C8008 A4 A NC OE# A0 B NC NC A3 NC C DQ0 NC D Vss E A2 CE2 A4 CE# NC A5 A6 NC DQ4 DQ1 A17 A7 DQ5 Vcc Vcc DQ2 NC A16 DQ6 Vss F DQ3 NC A14 A15 NC DQ7 A1 NC 16 29 NC WE# 17 28 A9 A19 18 27 A10 A18 19 26 A11 A17 20 25 A12 G NC NC A12 A13 WE# NC A16 21 24 A13 H A18 A8 A9 A10 A11 A19 A15 22 23 A14 1 2 3 4 TFBGA 5 6 TSOP-II JANUARY/2008, V 1.0 Alliance Memory Inc. Page 2 of 11 JANUARY 2008 January 2007 AS6C8008 X 8 BITCMOS LOW SRAM POWER CMOS SRAM 1024K X 8 BIT SUPER 512K LOW POWER ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) RATING -0.5 to 6.5 -0.5 to VCC+0.5 UNIT V V TA -40 to 85(I grade) ℃ TSTG PD IOUT -65 to 150 1 50 260 ℃ W mA ℃ TSOLDER *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE# Standby Output Disable Read Write Note: H X L L L CE2 X L H H H OE# X X H L X WE# X X H H L S UPPLY CUR RENT ISB1 ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 I/O OPERATION High-Z High-Z High-Z DOUT DIN H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION MIN. PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS ILO Output Disabled Current Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. CE# = VIL and CE2 = VIH ICC - 55 II/O = 0mA Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V ICC1 II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# ≧ VCC-0.2V Standby Power ISB1 or CE2≦0.2V Supply Current Other pins at 0.2V or VCC-0.2V JANUARY/2008, V 1.0 Alliance Memory Inc. TYP. 2.7 2.4 - 0.2 -1 *4 3.0 - MAX. UNIT 5.5 V VCC+0.3 V 0.6 V 1 µA -1 - 1 µA 2.4 - 2.7 - 0.4 V V - 30 60 mA - 4 12 mA - 6 50 µA Page 3 of 11 JANUARY 2008 January 2007 AS6C8008 X 8 BIT LOW POWER CMOS SRAM 1024K X 8 BIT SUPER 512K LOW POWER CMOS SRAM Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25? , f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. AS6C8008 UNIT AS6C8008 UNIT tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW tWHZ *These parameters are guaranteed by device characterization, but not production tested. JANUARY/2008, V 1.0 Alliance Memory Inc. Page 4 of 11 JANUARY 2008 January 2007 AS6C8008 X 8 BIT LOW POWER CMOS SRAM 1024K X 8 BIT SUPER 512K LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. JANUARY/2008, V 1.0 Alliance Memory Inc. Page 5 of 11 JANUARY 2008 January 2007 AS6C8008 X 8 BIT LOW POWER CMOS SRAM 1024K X 8 BIT SUPER 512K LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS tWP tWR WE# tWHZ Dout T OW High-Z (4) (4) tDW tDH Data Valid Din WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tWP WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. JANUARY/2008, V 1.0 Alliance Memory Inc. Page 6 of 11 JANUARY 2008 January 2007 AS6C8008 X 8 BITCMOS LOW SRAM POWER CMOS SRAM 1024K X 8 BIT SUPER 512K LOW POWER DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current SYMBOL TEST CONDITION VDR CE# > _ VCC - 0.2V or CE2 >_ 0.2V VCC = 1.5V IDR CE# > _ VCC - 0.2V or CE2 >_ 0.2V Other pins at 0.2V or VCC - 0.2V Chip Disable to Data Retention Time tCDR Recovery Time tRC* = Read Cycle Time MIN. 1.5 - See Data Retention Waveforms (below) tR DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) TYP. - MAX. UNIT 5.5 V 50 4 µA 0 - - ns tRC* - - ns (CE# controlled) > 1.5V VDR _ Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH Low Vcc Data Retention Waveform (2) tR _ Vcc-0.2V CE# > VIH (CE2 controlled) > 1.5V VDR _ Vcc Vcc(min.) Vcc(min.) tCDR CE2 VIL JANUARY/2008, V 1.0 tR _ 0.2V CE2 > Alliance Memory Inc. VIL Page 7 of 11 JANUARY 2008 January 2007 AS6C8008 X 8 BIT LOW POWER CMOS SRAM 1024K X 8 BIT SUPER 512K LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION θ 44-pin 400mil TSOP-II Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0 JANUARY/2008, V 1.0 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 Alliance Memory Inc. Page 8 of 11 JANUARY 2008 January 2007 AS6C8008 X 8 BIT LOW POWER CMOS SRAM 1024K X 8 BIT SUPER 512K LOW POWER CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension JANUARY/2008, V 1.0 Alliance Memory Inc. Page 9 of 11 JANUARY 2008 January 2007 AS6C8008 XCMOS 8 BITSRAM LOW POWER CMOS SRAM 1024K X 8 BIT LOW512K POWER ORDERING INFORMATION Alliance Organization VCC Range Package Operating Temp Speed ns AS6C8008-55ZIN 1024K x 8 2.7 - 5.5V 44pin TSOP II Industrial ~ -40 C - 85 C 55 AS6C8008-55BIN 1024K x 8 2.7 - 5.5V 48ball TFBGA Industrial ~ -40 C - 85 C 55 PART NUMBERING SYSTEM AS6C 8008 -55 Device Number low power S RAM prefix 380 =8M 08 = x8 JANUAR/2008, V 1.0 Access Time X X Package Option Temperature Range Z - 44pin TSOP I = Industrial B = 48ball TFBGA (-40 to + 85 C) Alliance Memory Inc. N N = Lead Free RoHS compliant part Page 10 of 11 JANUARY 2008 January 2007 AS6C8008 XCMOS 8 BITSRAM LOW POWER CMOS SRAM 1024K X 8 BIT LOW512K POWER ® Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211 Copyright © Alliance Memory All Rights Reserved www.alliancememory.com © Copyright 2007 Alliance Memory, Inc. All rights reserved. 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