AS6C8016-55TIN

AS6C8016-55TIN Revision History List 512K x 16 bit -AS6C8016-55TIN - 48-pin TSOP I PACKAGE Revision Rev. 1.0 Details Initial Issue Date November12.2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -1/11- Rev.1.0 Nov 2015 AS6C8016-55TIN FEATURES n n n n n n n GENERAL DESCRIPTION The AS6C8016-55TIN is a 8,388,608-bit low power CMOS static random access memory organized as 524,288 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. Fast access time : 55ns Low power consumption: Operating current : 30/20mA (TYP.) Standby current : 1.5µA (TYP.) SL-version Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) The AS6C8016-55TIN is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. n Data retention voltage : 1.2V(MIN.) The AS6C8016-55TIN operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible n Package : 48-pin 12mm x 20mm TSOP-I n Green & ROHS Compliant FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A18 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# CE2 WE# OE# LB# UB# SYMBOL DESCRIPTION A0 - A18 Address Inputs DQ0 – DQ15 Data Inputs/Outputs DECODER I/O DATA CIRCUIT 512Kx16 MEMORY ARRAY CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground COLUMN I/O CONTROL CIRCUIT PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed AS6C8016-55TIN -40℃ ~ 85℃ 2.7 ~ 3.6V 55ns Confidential -2/11- Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 1.5µA(SL) 30/20mA Rev.1.0 Nov 2015 AS6C8016-55TIN PIN CONFIGURATION A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# CE2 NC UB# LB# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AS6C8016-55TIN 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC Vss DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0 TSOP-I ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. Confidential -3/11- Rev.1.0 Nov.2015 AS6C8016-55TIN TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# CE2 OE# WE# LB# UB# H X X L L L L L L L L X L X H H H H H H H H X X X H H L L L X X X X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L I/O OPERATION SUPPLY CURRENT DQ0-DQ7 DQ8-DQ15 High – Z High – Z ISB,ISB1 High – Z High – Z High – Z High – Z High – Z High – Z ICC,ICC1 High – Z High – Z DOUT High – Z ICC,ICC1 High – Z DOUT DOUT DOUT DIN High – Z ICC,ICC1 High – Z DIN DIN DIN H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC VIN VSS Output Leakage VCC VOUT VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. - 55 CE# = VIL and CE2 = VIH ICC II/O = 0mA - 70 Other pins at VIL or VIH Average Operating Cycle time = 1µs Power supply Current CE#≦0.2V and CE2≧VCC-0.2V ICC1 II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL ISB Other pins at VIL or VIH Standby Power Supply Current ISB1 CE# VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V * SLI *5 25℃ 40℃ SLI MIN. 2.7 2.2 - 0.2 -1 TYP. 3.0 - *4 MAX. 3.6 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.2 - 2.7 - 0.4 V V - 30 40 mA - 20 30 mA - 4 8 mA - 0.15 1 mA - 1.5 1.5 5 5 µA µA 1.5 20 µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V Confidential -4/11- Rev.1.0 Nov.2015 AS6C8016-55TIN CAPACITANCE (TA = 25 , f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW AS6C8016-55TIN MIN. MAX. 55 55 55 30 10 5 20 20 10 55 25 10 - UNIT AS6C8016-55TIN MIN. MAX. 55 50 50 0 45 0 25 0 5 20 45 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Confidential -5/11- Rev.1.0 Nov 2015 AS6C8016-55TIN TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Confidential -6/11- Rev.1.0 Nov.2015 AS6C8016-55TIN WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din Confidential tDH Data Valid -7/11- Rev.1.0 Nov.2015 AS6C8016-55TIN WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tCW tAS CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Confidential -8/11 Rev.1.0 Nov.2015 AS6C8016-55TIN DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL CE# VCC for Data Retention VDR Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time IDR tCDR TEST CONDITION VCC - 0.2V or CE2≦0.2V 25℃ VCC = 1.2V SLI 40℃ CE# VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V SLI See Data Retention Waveforms (below) tR MIN. 1.2 - TYP. 1 MAX. 3.6 3 UNIT V µA - 1 3 µA - 1 20 µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ¡Ù 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR VIH CE# ¡Ù Vcc-0.2V Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ¡Ù 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE2 tR CE2 ¡Ø 0.2V VIL VIL Low Vcc Data Retention Waveform (3) (LB#, UB# controlled) VDR ¡Ù 1.2V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# Confidential VIH tR LB#,UB# ¡Ù Vcc-0.2V -9/11- VIH Rev.1.0 Nov 2015 AS6C8016-55TIN PACKAGE OUTLINE DIMENSION 48-pin 12mm x 20mm TSOP-I Package Outline Dimension Confidential -10/11- Rev.1.0 Nov 2015 AS6C8016-55TIN PART NUMBERING SYSTEM AS6C 8016 SRAM 8M=512K x 16 55 T Speed=55 ns T = 48pin TSOP I I I=Industrial (-40°C
85°C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential -11/11- Rev.1.0 Nov 2015