AS7C1024B-12TC

March 2004 ® AS7C1024B 5V 128K X 8 CMOS SRAM Features • Industrial and commercial temperatures • Organization: 131,072 words x 8 bits • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time • Low power consumption: ACTIVE - 605 mW / max @ 10 ns 300 mil SOJ 400 mil SOJ 8 × 20mm TSOP 1 8 x 13.4mm sTSOP 1 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA • Low power consumption: STANDBY - 55 mW / max CMOS • 6T 0.18u CMOS technology • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages Pin arrangement 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Logic block diagram VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O7 Row decoder 512 x 256 x 8 Array (1,048,576) Sense amp 32-pin (8 x 20mm) TSOP I 32-pin (8 x 13.4mm) sTSOP1 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 I/O0 WE OE CE1 CE2 Column decoder Control circuit Selection guide -10 Maximum address access time Maximum output enable access time Maximum Operating Current Maximum CMOS standby Current 10 5 110 10 -12 A9 A10 A11 A12 A13 A14 A15 A16 -15 15 7 90 10 AS7C1024B AS7C1024B -20 20 8 80 10 Unit ns ns mA mA 12 6 100 10 3/26/04, v 1.2 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. AS7C1024B ® Functional description The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1024B is guaranteed not to exceed 55 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/ O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min –0.50 –0.50 – –65 –55 – Max +7.0 VCC +0.50 1.0 +150 +125 20 Unit V V W °C °C mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 H X L L L CE2 X L H H H WE X X H H L OE X X H L X Data High Z High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC) Key: X = don’t care, L = low, H = high 3/26/04, v 1.2 Alliance Semiconductor P. 2 of 9 AS7C1024B ® Recommended operating conditions Parameter Supply Voltage Input Voltage Ambient operating temperature commercial industrial Symbol VCC VIH VIL TA TA Min 4.5 2.2 –0.5 0 –40 Nominal 5.0 – – – Max 5.5 VCC + 0.5 0.8 70 85 Unit V V V °C °C VIL min = -1.0V for pulse width less than 5ns VIH max = VCC+2.0V for pulse width less than 5ns. DC operating characteristics (over the operating range)1 -10 Parameter Input leakage current Output leakage current Operating power supply current Sym |ILI| |ILO| ICC ISB Standby power supply current Test conditions VCC = Max, VIN = GND to VCC VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC VCC = Max, CE1 ≤ VIL, CE2 ≥ VIH, f = fMax, IOUT = 0 mA VCC = Max, CE1 ≥ VIH and/or CE2 ≤ VIL, f = fMax VCC = Max, CE1 ≥ VCC–0.2V ISB1 VOL VOH and/or CE2 ≤ 0.2V VIN ≤ 0.2V or VIN ≥ VCC – 0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = –4 mA, VCC = Min 10 – 10 – 10 – 10 Min Max -12 Min Max -15 Min Max -20 Min Max Unit µA µA mA - 1 1 110 50 – – – – 1 1 100 45 – – – – 1 1 90 45 – – – – 1 1 80 40 mA Output voltage 2.4 0.4 - – 2.4 0.4 – – 2.4 0.4 – – 2.4 0.4 – V Capacitance (f = 1 MHz, Ta = 25 °C, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE1, CE2, WE, OE I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF 3/26/04, v 1.2 Alliance Semiconductor P. 3 of 9 AS7C1024B ® Read cycle (over the operating range)3,9,12 -10 Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time tRC tAA tACE1 tACE2 tOE 10 3 3 3 0 – 0 – 10 10 10 5 4 4 4 10 12 – – – – 3 3 3 – – 0 – 0 – -12 – 12 12 12 6 – – – 5 5 – 5 – 12 15 – – – – 3 3 3 – – 0 – 0 – -15 – 15 15 15 7 – – – 6 6 – 6 – 15 20 – – – – 3 3 3 – – 0 – 0 – -20 Notes 3 3, 12 3, 12 5 4, 5, 12 4, 5, 12 4, 5, 12 4, 5, 12 4, 5 4, 5 4, 5, 12 4, 5, 12 – 20 20 20 8 – – – 7 7 – 7 – 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Min Max Min Max Min Max Min Max Unit Output hold from address change tOH CE1 Low to output in low Z tCLZ1 CE2 High to output in low Z CE1 Low to output in high Z CE2 Low to output in high Z OE Low to output in low Z OE High to output in high Z Power up time Power down time tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ tPU tPD Key to switching waveforms Rising input Falling input Undefined / don’t care Read waveform 1 (address controlled)3,6,7,9,12 tRC Address DOUT tAA Data valid tOH Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12 CE1 CE2 OE DOUT Current supply tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% 50% ICC ISB tOE tOLZ tOHZ tCHZ1, tCHZ2 tRC1 3/26/04, v 1.2 Alliance Semiconductor P. 4 of 9 AS7C1024B ® Write cycle (over the operating range)11, 12 -10 Parameter Write cycle time Chip enable (CE1) to write end Chip enable (CE2) to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Symbol tWC tCW1 tCW2 tAW tAS tWP tWR tAH tDW tDH tWZ tOW Min Max Min 10 8 8 8 0 7 0 0 5 0 1 5 12 9 9 9 0 8 0 0 6 0 – 1 -12 Max – – – – – – – – – – 6 – 15 10 10 10 0 9 0 0 8 0 – 1 -15 Min Max – – – – – – – – – – 7 – 20 12 12 12 0 12 0 0 10 0 – 2 -20 Min Max – – – – – – – – – – 8 – Unit ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 12 Notes Write waveform 1 (WE controlled)10,11,12 tWC tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tWR tAH 3/26/04, v 1.2 Alliance Semiconductor P. 5 of 9 AS7C1024B ® Write waveform 2 (CE1 and CE2 controlled)10,11,12 tAW Address tAS CE1 CE2 tWP WE tWZ DIN DOUT tDW Data valid tDH tCW1, tCW2 tWC tAH tWR AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.5V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. +5V 480Ω Thevenin equivalent: 168Ω DOUT +1.728V +3.5V GND 90% 10% 2 ns 90% 10% DOUT 255Ω C13 Figure A: Input pulse GND Figure B: 5V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE1 and OE are low and CE2 is high for read cycle. Address valid prior to or coincident with CE1 transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 3/26/04, v 1.2 Alliance Semiconductor P. 6 of 9 AS7C1024B ® Package dimensions D e E1E2 32-pin SOJ 300 mil Min A A1 B c A1 b Seating Plane A 32-pin SOJ 400 mil Min 0.132 0.025 0.105 0.026 0.015 0.007 0.820 0.354 0.395 0.435 Max 0.146 0.115 0.032 0.020 0.013 0.830 0.378 0.405 0.445 Max 0.145 0.105 0.032 0.020 0.010 0.830 0.275 0.305 0.340 0.128 0.025 0.095 0.026 0.016 0.007 0.820 0.255 0.295 0.330 Pin 1 A2 B b c D E E1 E2 e A2 E 0.050 BSC 0.050 BSC b e α c D Hd L A2 A A1 32-pin TSOP 8×20 mm Min A A1 A2 b c D pin 1 pin 32 Max 1.20 0.15 1.05 0.27 0.21 18.50 8.10 20.20 0.70 5° – 0.05 0.95 0.17 0.10 18.30 7.90 19.80 0.50 0° e E Hd L 0.50 nominal E pin 16 pin 17 α 3/26/04, v 1.2 Alliance Semiconductor P. 7 of 9 AS7C1024B ® Ordering codes Package \ Access time Plastic SOJ, 300 mil Plastic SOJ, 400 mil TSOP1 8×20 mm sTSOP1 8 x 13.4mm Temp commercial industrial commercial industrial commercial industrial commercial industrial 10 ns AS7C1024B-10TJC – AS7C1024B-10JC – AS7C1024B-10TC – AS7C1024B-10STC – 12 ns AS7C1024B-12TJC AS7C1024B-12TJI AS7C1024B-12JC AS7C1024B-12JI AS7C1024B-12TC AS7C1024B-12TI AS7C1024B-12STI 15 ns AS7C1024B-15TJC AS7C1024B-15TJI AS7C1024B-15JC AS7C1024B-15JI AS7C1024B-15TC AS7C1024B-15TI AS7C1024B-15STI 20 ns AS7C1024B-20TJC AS7C1024B-20TJI AS7C1024B-20JC AS7C1024B-20JI AS7C1024B-20TC AS7C1024B-20TI AS7C1024B-20STI AS7C1024B-12STC AS7C1024B-15STC AS7C1024B-20STC Note: Add suffix ‘N’ to the above part number for LEAD FREE PARTS (Ex: AS7C1024B-10TCN) Part numbering system AS7C SRAM prefix 1024B Device number –XX Access time X Package:T = TSOP1 8×20 mm ST = sTSOP1 8 x 13.4 mm J = SOJ 400 mil TJ = SOJ 300 mil X Temperature range C = Commercial, 0° C to 70° C I = Industrial, -40° C to 85° C X N = LEAD FREE PART 3/26/04, v 1.2 Alliance Semiconductor P. 8 of 9 AS7C1024B ® ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C1024B Document Version: v 1.2 © Copyright 2003 Alliance Semiconductor Corporation. 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