AS7C1024C

September 2006 Advance Information ® AS7C1024C 5V 128K X 8 CMOS SRAM Features • Industrial (-40o to 85oC) temperature • Organization: 131,072 x 8 bits • High speed - 12 ns address access time - 6 ns output enable access time • Low power consumption via chip deselect • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages • ESD protection ≥ 2000 volts - 300 mil SOJ - 400 mil SOJ Pin arrangement Logic block diagram VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Address decoder 131,702 x 8 Array (1,048,576) Sense amp I/O7 I/O0 WE OE CE1 CE2 Address decoder Control circuit A9 A10 A11 A12 A13 A14 A15 A16 12/5/06, v. 1.0 Alliance Memory AS7C1024C P. 1 of 9 Copyright © Alliance Memory All rights reserved. AS7C1024C ® Functional description The AS7C1024C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min –0.50 –0.50 – –55 –55 – Max +7.0 VCC +0.50 1.25 +125 +125 50 Unit V V W °C °C mA Truth table CE1 H X L L L CE2 X L H H H WE X X H H L OE X X H L X Data High Z High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC) Key: X = don’t care, L = low, H = high. 12/5/06, v. 1.0 Alliance Memory P. 2 of 9 AS7C1024C ® Recommended operating conditions Parameter Supply Voltage Input Voltage Ambient operating temperature (Industrial) Note: 1 VIL min = -1.5V for pulse width less than 10ns, once per cycle. Symbol VCC VIH VIL(1) TA Min 4.5 2.2 –0.5(1) –40 Nominal 5.0 – – Max 5.5 VCC + 0.5 0.8 85 Unit V V V °C DC operating characteristics (over the operating range)1 AS7C1024C-12 Parameter Input leakage current Output leakage current Symbol |ILI| |ILO| ICC ISB Test conditions VCC = Max, VIN = GND to VCC VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC VCC = Max, CE1 ≤ VIL, CE2 ≥ VIH, f = fMax, IOUT = 0 mA VCC = Max, CE1 ≥ VIH and/or CE2 ≤ VIL, f = fMax VCC = Max, CE1 ≥ VCC–0.2V and/or CE2 ≤ 0.2V VIN ≤ 0.2V or VIN ≥ VCC – 0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = –4 mA, VCC = Min Min – – Max 5 5 Unit μA μA Operating power supply current – 160 mA – 40 mA Standby power supply current1 ISB1 – 10 mA Output voltage VOL VOH – 2.4 0.4 – V V Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Note: This parameter is guaranteed by device characterization, but is not production tested. Symbol CIN CI/O Signals A, CE1, CE2, WE, OE I/O Test conditions VIN = 3dV VOUT = 3dV Max 7 8 Unit pF pF 12/5/06, v. 1.0 Alliance Memory P. 3 of 9 AS7C1024C ® Read cycle (over the operating range)3,9 AS7C1024C-12 Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output hold from address change CE1 Low to output in low Z CE2 High to output in low Z CE1 Low to output in high Z CE2 Low to output in high Z OE Low to output in low Z OE High to output in high Z Power up time Power down time Symbol tRC tAA tACE1 tACE2 tOE tOH tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ tPU tPD Min 12 – – – – 4 3 3 0 – 0 – 0 – Max – 12 12 12 6 – – – 6 5 – 5 – 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 4, 5, 12 4, 5, 12 4, 5, 12 4, 5, 12 4, 5 4, 5 4, 5, 12 4, 5, 12 3 3, 12 3, 12 Notes Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address DOUT tAA Data valid tOH Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12 CE1 CE2 OE DOUT Current supply tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% 50% ICC ISB tOE tOLZ tOHZ tCHZ1, tCHZ2 tRC1 12/5/06, v. 1.0 Alliance Memory P. 4 of 9 AS7C1024C ® Write cycle (over the operating range)11 AS7C1024C-12 Parameter Write cycle time Chip enable (CE1) to write end Chip enable (CE2) to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Symbol tWC tCW1 tCW2 tAW tAS tWP tWR tAH tDW tDH tWZ tOW Min 12 10 10 10 0 8 0 0 7 0 0 3 Max – – – – – – – – – – 5 – Unit ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 12 Notes Write waveform 1 (WE controlled)10,11 tWC tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tWR tAH Write waveform 2 (CE1 and CE2 controlled)10,11,12 tAW Address tAS CE1 CE2 tWP WE twz DIN DOUT 12/5/06, v. 1.0 tDW Data valid tDH tCW1, tCW2 tWC tAH tWR Alliance Memory P. 5 of 9 AS7C1024C ® AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.0 V. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5 V. +5 V 480 Ω Thevenin equivalent: 168 Ω +3.0V GND 90% 10% 3 ns 90% 10% DOUT 255 Ω C13 DOUT +1.728 V Figure A: Input pulse GND Figure B: 5 V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 12/5/06, v. 1.0 Alliance Memory P. 6 of 9 AS7C1024C ® Package dimensions 32-pin SOJ 300 mil Min A 32-pin SOJ 300/400 mil e D 32-pin SOJ 400 mil Min 0.132 0.025 0.105 0.026 0.015 0.007 0.820 0.354 0.395 0.435 Max 0.146 0.115 0.032 0.020 0.013 0.830 0.378 0.405 0.445 Max 0.145 0.105 0.032 0.020 0.010 0.830 0.275 0.305 0.340 0.128 0.025 0.095 0.026 0.016 0.007 0.820 0.255 0.295 0.330 A1 A2 B b E1 E2 c D E E1 A b Seating plane Pin 1 A1 c A2 E B E2 e 0.050 BSC 0.050 BSC Note: This part is compatible with both pin numbering conventions used by various manufacturers. 12/5/06, v. 1.0 Alliance Memory P. 7 of 9 AS7C1024C ® Ordering Codes Package Plastic SOJ, 300 mil Plastic SOJ, 400 mil Volt/Temp 5V industrial 5V industrial 12 ns AS7C1024C-12TJIN AS7C1024C-12JIN Part numbering system AS7C SRAM prefix 1024C Device number –XX X X X Package: Temperature range N = LEAD FREE Access time J = SOJ 400 mil I = industrial, -40° PART C to 85° C TJ = SOJ 300 mil 12/5/06, v. 1.0 Alliance Memory P. 8 of 9 AS7C1024C ® ® Alliance Memory, Inc. 1116 South Amphlett San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved Part Number: AS7C1024C Document Version: v. 1.0 © Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.