AS7C1026C-15JINTR

September 2006 A AS7C1026C ® 5 V 64K X 16 CMOS SRAM • Industrial (-40o to 85oC) temperature • Organization: 65,536 words × 16 bits • Center power and ground pins for low noise • High speed - 15 ns address access time - 6 ns output enable access time • Low power consumption via chip deselect • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • Upper and Lower byte pin • JEDEC standard packaging - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 • ESD protection > _ 2000 volts Pin arrangement A7 I/O0–I/O7 I/O8–I/O15 Control circuit Address decoder A8 WE I/O buffer UB OE LB CE 12/5/06, v 1.0 GND A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC A15 A6 A14 A5 A13 A4 A11 A3 VCC 65,536 x 16 Array A12 A2 A9 A1 A10 A0 Address decoder Logic block diagram 44-Pin SOJ (400 mil), TSOP 2 AS7C1026C Features Alliance Memory P. 1 of 9 Copyright © Alliance Memory. All rights reserved. AS7C1026C ® Functional description The AS7C1026C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 15 ns with output enable access times (tOE) of 6 ns are ideal for highperformance applications. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1026C is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Voltage on VCC relative to GND Vt1 Voltage on any pin relative to GND Vt2 Power dissipation PD Storage temperature (plastic) Min Max Unit –0.50 VCC +0.50 V –55 +125 –0.50 – Tstg Ambient temperature with VCC applied Tbias DC current into outputs (low) 1.25 –55 IOUT Note: +7.0 W °C +125 – V °C 50 mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 L H L L H DOUT High Z L L DOUT DOUT DIN High Z High Z H X X X L H L H L L X L L H L L L X L L H X H X L L X Key: H = high, L = low, X = don’t care. 12/5/06, v 1.0 X L High Z L DIN L H X H X H H High Z L High Z Alliance Memory High Z DOUT Mode Standby (ISB), ISBI) Read I/O0–I/O7 (ICC) Read I/O8–I/O15 (ICC) Read I/O0–I/O15 (ICC) DIN Write I/O0–I/O15 (ICC) DIN Write I/O8–I/O15 (ICC) High Z Output disable (ICC) Write I/O0–I/O7 (ICC) P. 2 of 9 AS7C1026C ® Recommended operating conditions Supply voltage Parameter Symbol Min Nominal Max Unit VIH 2.2 – VCC + 0.5 V – 85 VCC Input voltage 4.5 –0.5 VIL Ambient operating temperature (Industrial) TA Notes: 5.0 5.5 – –40 0.8 V V o C VIL min = -1.5V for pulse width less than 5ns, once per cycle. VIH max = VCC+2.0V for pulse width less than 5ns, once per cycle. DC operating characteristics (over the operating range)1 Parameter Sym Input leakage current | ILI | Output leakage current | ILO | Operating power supply current ICC ISB Standby power supply current ISB1 VOL Output voltage VOH Test conditions Min Max Unit – 5 µA – 5 µA – 210 mA – 60 mA – 10 mA – 0.4 V Signals Test conditions Max Unit I/O VOUT = 0 V 7 pF VCC = Max, VIN = GND to VCC VCC = Max, CE = VIH, VOUT = GND to VCC VCC = Max, CE ? VIL, IOUT = 0mA, f = fMax VCC = Max, CE ? VIH , f = fMax VCC = Max, CE ? VCC–0.2 V, VIN ? 0.2 V or VIN ? VCC–0.2 V, f = 0 IOL = 8 mA, VCC = Min IOH = –4 mA, VCC = Min Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Symbol CIN CI/O AS7C1026C-15 A, CE, WE, OE, LB, UB 2.4 VIN = 0 V – 6 V pF Note: This parameter is guaranteed by device characterization, but is not production tested. 12/5/06, v 1.0 Alliance Memory P. 3 of 9 AS7C1026C ® Read cycle (over the operating range)3,9 Parameter Read cycle time AS7C1026C-15 Symbol Min Max Unit Notes tAA – 15 ns 3 – 7 tRC Address access time Chip enable (CE) access time tACE Output enable (OE) access time tOE Output hold from address change tOH CE low to output in low Z tCLZ CE high to output in high Z tCHZ Byte select access time tBA OE low to output in low Z tOLZ Byte select Low to low Z tBLZ Byte select High to high Z tBHZ OE high to output in high Z tOHZ Power up time tPU Power down time tPD 15 – 4 4 – 0 – 0 – – 0 – – ns 15 ns ns – ns – 6 7 4, 5 ns 4, 5 ns – 6 – 4, 5 ns 4, 5 ns 12 4, 5 ns ns 6 5 ns ns – 3 ns 4, 5 4, 5 4, 5 Key to switching waveforms Rising input Falling input Read waveform 1 (address controlled)3,6,7,9 Undefined output/don’t care tRC Address DataOUT tAA tOH Previous data valid tOH Data valid Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9 tRC Address tAA OE tOE tOLZ tOH CE tLZ tOHZ tHZ tACE LB, UB tBLZ tBA DataIN 12/5/06, v 1.0 tBHZ Data valid Alliance Memory P. 4 of 9 AS7C1026C ® Write cycle (over the operating range) 11 Symbol Min Max Unit Chip enable (CE) to write end tCW 9 – ns Address setup time tAS Write cycle time Parameter AS7C1026C-15 tWC Address setup to write end 15 tAW Write pulse width 9 0 9 tWP Write recovery time tWR Data valid to write end tDW Write enable to output in high Z tWZ Address hold from end of write 0 tAH Data hold time 0 7 tDH Output active from write end 0 – 1 tOW Byte select low to end of write tBW Write waveform 1 (WE controlled)11 9 – ns – Notes ns – ns – ns – ns – ns – ns – ns 6 ns – ns – ns 5 4, 5 4, 5 tWC tAH Address tWR tCW CE tBW LB, UB tAW tAS tWP WE tDW DataIN DataOUT 12/5/06, v 1.0 tDH Data valid tWZ Data undefined Alliance Memory tOW high Z P. 5 of 9 AS7C1026C ® Write waveform 2 (CE controlled)11 tWC tAH Address tAS tWR tCW CE tAW tBW LB, UB tWP WE tDH tDW Data valid DataIN tWZ tCLZ DataOUT high Z tOW Data undefined high Z AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.0 V. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5 +5 V 480 Ω DOUT +3.0V GND 90% 10% 90% 3 ns 10% Figure A: Input pulse 255 Ω C13 Thevenin Equivalent: 168 Ω DOUT +1.728 V GND Figure B: 5 V Output load Notes: 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 12/5/06, v 1.0 Alliance Memory P. 6 of 9 AS7C1026C ® Package dimensions c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 E He 44-pin TSOP 2 D A l 0–5° A1 e b Min (mm) Max (mm) A1 0.05 0.15 A2 0.95 1.05 b 0.30 0.45 c 0.120 0.21 D 18.31 18.52 E 10.06 10.26 He 11.68 11.94 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 A2 44-pin TSOP 2 e l 1.2 0.80 (typical) 0.40 0.60 44-pin SOJ 400 mil D e Min (in) Max (in) 44-pin SOJ E1 E2 Pin 1 c B A2 A A1 b Seating plane E A 0.128 A1 0.025 – A2 0.105 0.115 B 0.026 0.032 b 0.015 0.020 c 0.007 0.013 D 1.120 1.130 E Alliance Memory 0.370 NOM E1 0.395 0.405 E2 0.435 0.445 e 12/5/06, v 1.0 0.148 0.050 NOM P. 7 of 9 AS7C1026C ® Ordering codes Package Plastic SOJ, 400 mil TSOP 2, 10.2 x 18.4 mm Volt/Temp 5V Industrial 5V Industrial Part numbering system AS7C 1026C SRAM prefix Device number 12/5/06, v 1.0 –XX Access time 15 ns AS7C1026C-15JIN AS7C1026C-15TIN X X Package: Temperature range: J = SOJ 400 mil I = industrial: -40° C T = TSOP 2, 10.2 x to 85° C 18.4 mm Alliance Memory X N = LEAD FREE PART P. 8 of 9 AS7C1026C ® ® Alliance Memory, Inc. 1116 South Amphlett San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved Part Number: AS7C1026C Document Version: v 1.0 © Copyright 2003 Alliance Memory, Inc. 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