AS7C164A-15JCNTR

NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM FEATURES GENERAL DESCRIPTION Fast access time : 12/15 ns Low power consumption: Operating current : 110/100/90/80mA (TYP.) Standby current : 1mA (TYP.) Single 5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 2.0V (MIN.) Green package available Package : 28-pin 300 mil SOJ The AS7C164A is a 65,536-bit high speed CMOS static random access memory organized as 8,192 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS7C164A is well designed for high speed system applications, and particularly well suited for battery back-up nonvolatile memory application. The AS7C164A operates from a single power supply of 5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS7C164A Operating Temperature 0 ~ 70℃ Vcc Range Speed 4.5 ~ 5.5V 12/15ns FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A12 DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# CE2 WE# OE# CONTROL CIRCUIT NOVEMBER/2009 V1.2 Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 1mA 110/100/90/80mA 8Kx8 MEMORY ARRAY SYMBOL DESCRIPTION A0 - A12 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE#, CE2 Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection COLUMN I/O Alliance Memory Inc Page 1 of 10 NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM PIN CONFIGURATION 1 28 Vcc 2 27 WE# A7 3 26 CE2 A6 4 25 A8 A5 5 24 A9 A4 6 A3 7 A2 8 A1 9 AS7C164A NC A12 23 A11 22 OE# 21 A10 20 CE# 19 DQ7 18 DQ6 A0 10 DQ0 11 DQ1 12 17 DQ5 DQ2 13 16 DQ4 Vss 14 15 DQ3 SOJ ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature SYMBOL VT1 VT2 TA RATING -0.5 to 6.5 -0.5 to VCC+0.5 0 to 70(C grade) TSTG PD IOUT -65 to 150 1 50 Storage Temperature Power Dissipation DC Output Current UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H X L L L CE2 X L H H H OE# X X H L X WE# X X H H L I/O OPERATION High-Z High-Z High-Z DOUT DIN SUPPLY CURRENT ISB1 ISB1 ICC ICC ICC H = VIH, L = VIL, X = Don't care. NOVEMBER/2009 V1.2 Alliance Memory Inc Page 2 of 10 NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL VCC ≧ VIN ≧ VSS Input Leakage Current ILI Output Leakage VCC ≧ VOUT ≧ VSS, ILO Output Disabled Current Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. Average Operating CE# = VIL and CE2 = VIH, -12 ICC Power supply Current II/O = 0mA -15 Other pins at VIH or VIL Standby Power Supply Current ISB1 MIN. 4.5 2.4 - 0.5 -1 CE# ≧VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V TYP. 5.0 - *4 MAX. 5.5 VCC+0.5 0.8 1 UNIT V V V µA -1 - 1 µA 2.4 - - 0.4 V V - 90 80 160 140 mA mA - 1 5 mA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load NOVEMBER/2009 V1.2 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA Alliance Memory Inc Page 3 of 10 NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW tWHZ *These parameters are guaranteed by device NOVEMBER/2009 V1.2 Alliance Memory Inc Page 4 of 10 NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tCLZ Dout High-Z tOLZ tOE tOH tOHZ tCHZ Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low , CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, t CHZ is less than tCLZ , tOHZ is less than tOLZ. NOVEMBER/2009 V1.2 Alliance Memory Inc Page 5 of 10 NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW (4) tDH Data Valid Din WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tWP WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. NOVEMBER/2009 V1.2 Alliance Memory Inc Page 6 of 10 NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL VCC for Data Retention VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time tCDR tR TEST CONDITION CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V VCC = 2.0V CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V Others at 0.2V or VCC-0.2V See Data Retention Waveforms (below) MIN. TYP. MAX. UNIT 2.0 - 5.5 V - 0.6 3 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 2.0V Vcc Vcc(min.) Vcc(min.) tCDR VIH CE# tR CE# ≧ Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 2.0V Vcc Vcc(min.) Vcc(min.) tCDR CE2 NOVEMBER/2009 V1.2 VIL tR CE2 ≦ 0.2V Alliance Memory Inc VIL Page 7 of 10 NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM 28-pin 300 mil SOJ Package Outline Dimension 28 15 1 14 A2 CL X XX SYM. UNIT INCH(REF) MM(BASE) A 0.140 (MAX) 3.556 (MAX) A1 0.026 (MIN) 0.660 (MIN) A2 0.100±0.005 2.540±0.127 B 0.018±0.003 0.457±0.076 B1 0.028 ±0.003 0.711±0.076 c 0.010±0.003 0.254±0.076 D 0.710±0.010 18.03±0.254 E 0.337±0.010 8.560±0.254 E1 0.300±0.005 7.620±0.127 e 0.050±0.003 1.270±0.076 L 0.087±0.010 2.210±0.254 S 0.030±0.004 0.762±0.102 Y 0.003 (MAX) 0.076 (MAX) Note : 1.S/E/D dimension is not including mold flash. 2.The end flash in package lengthwise is not more than 10 mils each side. NOVEMBER/2009 V1.2 Alliance Memory Inc Page 8 of 10 NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM ORDERING INFORMATION Package/Access Time Temperature 28-pin 300 mil SOJ Commercial 12 ns 15 ns AS7C164A-12JCN AS7C164A-15JCN PART NUMBERING SYSTEM AS7C SRAM prefix Voltage: 5V supply NOVEMBER/2009 V1.2 164A -XX Device Number Access Time J J = SOJ, 300 mil Alliance Memory Inc C Temperature Range: C = 0 ~ 70 C X N = Lead Free Part Page 9 of 10 NOVEMBER 2009 AS7C164A 8K X 8 BIT HIGH SPEED CMOS SRAM ® Alliance Memory, Inc 551 Taylor Way, San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211 Copyright © Alliance Memory All Rights Reserved www.alliancememory.com © Copyright 2009 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. 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Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofAlliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against allclaims arising from such use. NOVEMBER/2009 V1.2 Alliance Memory Inc Page 10 of 10