AS7C252MNTF18A-10TQIN

January 2005 ® AS7C252MNTF18A 2.5V 2M x 18 Flowthrough SRAM with NTDTM Features • • • • • • • • Organization: 2,097,152 words × 18 bits NTD™architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 2.5V core power supply Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation Logic block diagram A[19:0] 20 D Address register burst logic Q 20 CLK CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ CLK D Q 20 Write delay addr. registers CLK Control logic CLK Write Buffer 2M x 18 SRAM array DQ [a,b] 18 D Data Q input register CLK 18 18 18 18 CLK CEN OE Output buffer 18 OE DQ [a,b] Selection guide -75 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 8.5 7.5 325 140 90 -85 10 8.5 300 130 90 -10 12 10 275 130 90 Units ns ns mA mA mA 1/17/05, v 1.1 Alliance Semiconductor P. 1 of 18 Copyright © Alliance Semiconductor. All rights reserved. AS7C252MNTF18A ® 2.5V 32 Mb Synchronous SRAM products list1,2 Org 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 Part Number AS7C252MPFS18A AS7C251MPFS32A AS7C251MPFS36A AS7C252MPFD18A AS7C251MPFD32A AS7C251MPFD36A AS7C252MFT18A AS7C251MFT32A AS7C251MFT36A AS7C252MNTD18A AS7C251MNTD32A AS7C251MNTD36A AS7C252MNTF18A AS7C251MNTF32A AS7C251MNTF36A Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 1 Core Power Supply: VDD = 2.5V + 0.125V 2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 1/17/05, v 1.1 Alliance Semiconductor P. 2 of 18 AS7C252MNTF18A ® Pin diagram 100-pin TQFP - top view 100 99 98 97 96 95 94 93 VDDQ VSSQ NC NC DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 VSS VDD NC VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb NC VSSQ VDDQ NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD A A A A TQFP 14 x 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS NC VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 NC NC VSSQ VDDQ NC NC NC 1/17/05, v 1.1 LBO A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Alliance Semiconductor P. 3 of 18 AS7C252MNTF18A ® Functional Description The AS7C252MNTF18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 2,097,152 words × 18 bits and incorporates a LATE Write. This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for one 'dead' cycle for valid data to become available. This dead cycle can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations. NTD™ devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flowthrough read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear. With NTD™, write and read operations can be used in any order without producing dead bus cycle. Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input. The AS7C252MNTF18A operates with a 2.5V ± 5% power supply for the device core (VDD). These devices are available in 100-pin TQFP package. TQFP Capacitance Parameter Input capacitance I/O capacitance *Guaranteed not tested Symbol CIN* CI/O* I/O pins Signals Address and control pins Test conditions Vin = 0V Vin = Vout = 0V Max 5 7 Unit pF pF TQFP thermal resistance Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 1 This parameter is sampled. Symbol 1 layer 4 layer θJA θJA θJC Typical 40 22 8 Units °C/W °C/W °C/W Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 1/17/05, v 1.1 Alliance Semiconductor P. 4 of 18 AS7C252MNTF18A ® Signal descriptions Signal CLK CEN A, A0, A1 DQ[a,b] CE0, CE1, CE2 ADV/LD R/W BW[a,b] OE LBO ZZ NC I/O Properties I I I I/O I I I I I I I CLOCK SYNC SYNC SYNC SYNC SYNC SYNC SYNC ASYNC STATIC ASYNC - Description Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. Clock enable. When de-asserted high, the clock input signal is masked. Address. Sampled when all chip enables are active and ADV/LD is asserted. Data. Driven as output when the chip is enabled and OE is active. Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is high. Advance or Load. When sampled high, the internal burst address counter will increment in the order defined by the LBO input value. When low, a new address is loaded. A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE operation. Is ignored when ADV/LD is high. Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. Asynchronous output enable. I/O pins are not driven when OE is inactive. Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. Snooze. Places device in low power mode; data is retained. Connect to GND if unused. No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successful complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 1/17/05, v 1.1 Alliance Semiconductor P. 5 of 18 AS7C252MNTF18A ® Burst order Interleaved burst order (LBO = 1) A1A0 Starting address First increment Second increment Third increment 00 01 10 11 A1A0 01 00 11 10 A1A0 10 11 00 01 A1A0 11 10 01 00 Starting Address First increment Second increment Third increment Linear burst order (LBO = 0) A1A0 00 01 10 11 A1A0 01 10 11 00 A1A0 10 11 00 01 A1A0 11 00 01 10 Synchronous truth table[5,6,7,8,9,11] CE0 CE1 CE2 ADV/LD R/W BWn OE CEN Address source CLK Operation DQ Notes H X X X L X L X L X L X X X X L X H X H X H X H X X X H X X L X L X L X L X X L L L H L H L H L H L H X X X X X H X H X L X L X X X X X X X X X X L L H H X X X X X L L H H X X X X X L L L L L L L L L L L L H NA NA NA NA Next Next Next L to H L to H L to H L to H L to H L to H L to H DESELECT Cycle DESELECT Cycle DESELECT Cycle CONTINUE DESELECT Cycle READ Cycle (Begin Burst) READ Cycle (Continue Burst) DUMMY READ (Continue Burst) WRITE CYCLE (Begin Burst) WRITE CYCLE (Continue Burst) High-Z High-Z High-Z High-Z Q Q 1,10 2 3 1,3,10 2,3 1,2,3, 10 4 1 External L to H External L to H NOP/DUMMY READ (Begin Burst) High-Z External L to H D D High-Z High-Z - High-Z 1,2,10 External L to H NOP/WRITE ABORT (Begin Burst) Next L to H WRITE ABORT (Continue Burst) INHIBIT CLOCK Current L to H Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb) are HIGH. BWn = L means one or more byte write signals are LOW. Notes: 1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first. 2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed. 3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements. 4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle. 5 BWa enables WRITEs to byte “a” (DQa pins); BWb enables WRITEs to byte “b” (DQb pins). 6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 7 Wait states are inserted by setting CEN HIGH. 8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up. 9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE. 10 The address counter is incremented for all CONTINUE BURST cycles. 11 ZZ pin is always Low. 1/17/05, v 1.1 Alliance Semiconductor P. 6 of 18 AS7C252MNTF18A ® Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature Temperature under bias Symbol VDD, VDDQ VIN VIN PD IOUT Tstg Tbias Min –0.5 –0.5 –0.5 – – –65 –65 Max +4.6 VDD + 0.5 VDDQ + 0.5 1.8 20 +150 +135 Unit V V V W mA o o C C Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Recommended operating conditions Parameter Supply voltage for inputs Supply voltage for I/O Ground supply Symbol VDD VDDQ Vss Min 2.375 2.375 0 Nominal 2.5 2.5 0 Max 2.625 2.625 0 Unit V V V 1/17/05, v 1.1 Alliance Semiconductor P. 7 of 18 AS7C252MNTF18A ® DC electrical characteristics Parameter Input leakage current† Sym |ILI| |ILO| VIH VIL VOH VOL Conditions VDD = Max, 0V < VIN < VDD OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ Address and control pins I/O pins Address and control pins I/O pins IOH = –4 mA, VDDQ = 2.375V IOL = 8 mA, VDDQ = 2.625V Min -2 -2 1.7* 1.7* -0.3** -0.3** 1.7 – Max 2 2 VDD+0.3 VDDQ+0.3 0.7 0.7 – 0.7 Unit µA µA V V V V V V Output leakage current Input high (logic 1) voltage Input low (logic 0) voltage Output high voltage Output low voltage * † LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA. VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC IL min **V = -1.5 for pulse width less than 0.2 X tCYC IDD operating conditions and maximum limits Parameter Operating power supply current1 Sym ICC ISB Standby power supply current ISB1 ISB2 Conditions CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax, IOUT = 0 mA, ZZ < VIL All VIN ≤ 0.2V or > VDD – 0.2V, Deselected, f = fMax, ZZ < VIL Deselected, f = 0, ZZ < 0.2V, all VIN ≤ 0.2V or ≥ VDD – 0.2V Deselected, f = fMax, ZZ ≥ VDD – 0.2V, all VIN ≤ VIL or ≥ VIH -75 325 140 90 80 -85 300 130 90 80 -10 275 130 mA 90 80 Unit 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 1/17/05, v 1.1 Alliance Semiconductor P. 8 of 18 AS7C252MNTF18A ® Timing characteristics over operating range Parameter Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data Output invalid from clock high Output enable low to output low Z Output enable high to output high Z Clock high to output high Z Output enable high to invalid output Clock high pulse width Clock low pulse width Address and Control setup to clock high Data setup to clock high Write setup to clock high Chip select setup to clock high Address hold from clock high Data hold from clock high Write hold from clock high Chip select hold from clock high Clock enable setup to clock high Clock enable hold from clock high ADV setup to clock high ADV hold from clock high 1 See “Notes:” on page 15. Sym tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tOHOE tCH tCL tAS tDS tWS tCSS tAH tDH tWH tCSH tCENS tCENH tADVS tADVH -75 Min 8.5 – – 2.5 2.5 0 – – 0 2.5 2.5 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 0.5 2.0 0.5 Max – 7.5 3.5 – – – 3.5 4.0 – – – – – – – – – – – – – – – Min 10 – – 2.5 2.5 0 – – 0 3.0 3.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 0.5 2.0 0.5 -85 Max – 8.5 4.0 – – – 4.0 5.0 – – – – – – – – – – – – – – – Min 12 – – 2.5 2.5 0 – – 0 3.0 3.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 0.5 2.0 0.5 -10 Max – 10 4.0 – – – 4.0 5.0 – – – – – – – – – – – – – – – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes1 2,3,4 2 2,3,4 2,3,4 2,3,4 5 5 6 6 6, 7 6, 8 6 6 6, 7 6, 8 6 6 6 6 Snooze Mode Electrical Characteristics Description Conditions Symbol Min Max Units Current during Snooze Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current ZZ > VIH ISB2 tPDS tPUS tZZI tRZZI 80 2 2 2 0 mA cycle cycle cycle 1/17/05, v 1.1 Alliance Semiconductor P. 9 of 18 AS7C252MNTF18A ® Key to switching waveforms Rising input Falling input don’t care Undefined Timing waveform of read cycle tCH CLK tCENS tCENH tCL tCYC CEN tAS Address A1 tAH A2 A3 tWS tWH R/W tCSS CE0,CE2 tCSH CE1 tADVS tADVH ADV/LD OE tOE Dout tLZOE Q(A1) tHZOE Q(A2) Q(A2Y‘01) Q(A2Y‘10) Q(A2Y‘11) Q(A3) Q(A3Y‘01) Command READ Q(A1) DSEL READ Q(A2) BURST BURST READ READ Q(A2Ý01) Q(A2Ý10) BURST READ Q(A2Ý11) STALL READ Q(A3) BURST READ Q(A3Ý01) 1/17/05, v 1.1 Alliance Semiconductor P. 10 of 18 AS7C252MNTF18A ® Timing waveform of write cycle tCH CLK tCENS tCENH tCL tCYC CEN tAS Address A1 tAH A2 A3 R/W BWn tCSS CE0,CE2 tCSH CE1 tADVS tADVH ADV/LD OE tDS Din tHZOE Dout Q(n-1) tDH D(A3) D(A1) D(A2) D(A2Y‘01) D(A2Y‘10) D(A2Y‘11) D(A3Y‘01) Command WRITE D(A1) DSEL WRITE D(A2) BURST BURST BURST WRITE WRITE WRITE D(A2Ý01) D(A2Ý10) D(A2Ý11) STALL WRITE D(A3) BURST WRITE D(A3Ý01) 1/17/05, v 1.1 Alliance Semiconductor P. 11 of 18 AS7C252MNTF18A ® Timing waveform of read/write cycle tCH CLK tCENS CEN tAS ADDRESS tWS R/W tWS BWn tCSS CE0, CE2 tCSH tWH A1 tCL tCYC tCENH tAH A2 A3 A4 A5 A6 A7 tWH CE1 tADVS ADV/LD tADVH OE tCD tDS tDH D/Q D(A1) D(A2) tHZOE tOH Q(A3) Q(A4) tLZC D(A2Ý01) tOE tHZC Q(A4Ý01) D(A5) Q(A6) D(A7) tLZOE Command WRITE D(A1) WRITE D(A2) BURST WRITE D(A2Ý01) READ Q(A3) READ Q(A4) BURST READ Q(A4Ý01) WRITE D(A5) READ Q(A6) WRITE D(A7) DSEL Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. 1/17/05, v 1.1 Alliance Semiconductor P. 12 of 18 AS7C252MNTF18A ® NOP, stall and deselect cycles CLK CEN CE1 CE0, CE2 ADV/LD R/W BWn Address A1 A2 A3 D/Q Q(A1) Q(A1Ý01) Q(A1Ý10) D(A2) Command READ Q(A1) BURST STALL Q(A1Ý01) BURST DSEL Q(A1Ý10) BURST DSEL WRITE D(A2) BURST BURST WRITE WRITE D(A2Ý10) NOP NOP D(A3) D(A2Ý01) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE is low. 1/17/05, v 1.1 Alliance Semiconductor P. 13 of 18 AS7C252MNTF18A ® Timing waveform of snooze mode CLK tPUS ZZ setup cycle ZZ tZZI ZZ recovery cycle Isupply ISB2 tRZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation Cycle Dout High-Z 1/17/05, v 1.1 Alliance Semiconductor P. 14 of 18 AS7C252MNTF18A ® AC test conditions • Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. • Input and output timing reference levels: 1.5V. +3.0V Z0 = 50Ω 90% 90% 10% DOUT VL = 1.5V for 3.3V I/O; 30 pF* = V DDQ/2 for 2.5V I/O 50Ω DOUT 353Ω/1538Ω Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω/1667Ω 5 pF* GND *including scope and jig capacitance 10% GND Figure A: Input waveform Figure B: Output load (A) Figure C: Output load(B) Notes: 1) For test conditions, see “AC test conditions”, Figures A, B, C 2) This parameter measured with output load condition in Figure C. 3) This parameter is sampled, but not 100% tested. 4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage. 5) tCH measured high above VIH and tCL measured as low below VIL 6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. 7) Write refers to R/W and BW[a,b]. 8) Chip select refers to CE0, CE1, and CE2. 1/17/05, v 1.1 Alliance Semiconductor P. 15 of 18 AS7C252MNTF18A ® Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters Hd D b e He E α c L1 L A1 A2 1/17/05, v 1.1 Alliance Semiconductor P. 16 of 18 AS7C252MNTF18A ® Ordering information Package &Width TQFP x18 -75 AS7C252MNTF18A-75TQC AS7C252MNTF18A-75TQI –85 AS7C252MNTF18A-85TQC AS7C252MNTF18A-85TQI –10 AS7C252MNTF18A-10TQC AS7C252MNTF18A-10TQI Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C252MNTF18A-85TQCN) Part numbering guide AS7C 1 25 2 2M 3 NTF 4 18 5 A 6 –XX 7 TQ 8 C/I 9 X 10 1. Alliance Semiconductor SRAM prefix 2. Operating voltage: 25 = 2.5V 3. Organization: 2M = 2 Meg 4. NTF = No Turn-Around Delay. Flow-through mode 5. Organization: 18 = x 18 6. Production version: A = first production version 7. Clock access time: [-75 = 7.5 ns access time;-85 = 8.5 ns access time; -10 = 10.0 ns access time] 8. Package type: TQ = TQFP 9. Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C) 10. N = Lead free part 1/17/05, v 1.1 Alliance Semiconductor P. 17 of 18 AS7C252MNTF18A ® ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. 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