AS7C256A-12JCN

September 2004 ® AS7C256A 5V 32K X 8 CMOS SRAM (Common I/O) Features • • • • Pin compatible with AS7C256 Industrial and commercial temperature options Organization: 32,768 words × 8 bits High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time • Very low power consumption: ACTIVE - 412.5 mW max @ 10 ns • Very low power consumption: STANDBY - 11 mW max CMOS I/O • Easy memory expansion with CE and OE inputs • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages - 300 mil SOJ - 8 × 13.4 mm TSOP 1 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA • 2.0V Data retention Logic block diagram VCC GND Input buffer Pin arrangement 28-pin TSOP 1 (8×13.4 mm) 28-pin SOJ (300 mil) A0 A1 A2 A3 A4 A5 A6 A7 I/O7 Row decoder Sense amp 256 X 128 X 8 Array (262,144) I/O0 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS7C256A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 Column decoder WE Control circuit OE CE A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 AAAAAAA 8 9 10 11 12 13 14 Selection guide -10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current 10 5 75 2 -12 12 6 70 2 -15 15 7 65 2 -20 20 8 60 2 Unit ns ns mA mA 9/24/04; v.1.2 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. AS7C256A AS7C256A ® Functional description The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. CMOS standby mode consumes ≤11 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min –0.5 –0.5 – –65 –55 – Max +7.0 VCC + 0.5 1.0 +150 +125 20 Unit V V W o C oC mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L L WE X H H L OE X H L X High Z High Z DOUT DIN Data Mode Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC) Key: X = Don’t care, L = Low, H = High 9/24/04; v.1.2 Alliance Semiconductor P. 2 of 9 AS7C256A ® Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature commercial industrial Symbol VCC VIH** VIL* TA TA Min 4.5 2.2 -0.5 0 –40 Typical 5.0 – – – – Max 5.5 VCC+0.5 0.8 70 85 Unit V V V oC o C * VIL min = –1.0V for pulse width less than 5ns. ** VIH max = VCC + 2.0V for pulse width less than 5ns. DC operating characteristics (over the operating range)1 -10 Parameter Input leakage current Sym |ILI| Test conditions VCC = Max, Vin = GND to VCC -12 -15 -20 Min Max Min Max Min Max Min Max Unit Notes – – – – – – 2.4 1 1 75 45 2.0 0.4 – – – – – – 2.4 1 1 70 45 2.0 0.4 – – – – – – – 2.4 1 1 65 40 2.0 0.4 – – – – – – – 2.4 1 1 60 40 2.0 0.4 – µA µA mA mA mA V V 4 4 Output leakage V = Max, |ILO| CC current VOUT = GND to VCC Operating power supply current ICC ISB Standby power supply current VCC = Max, CE < VIL f = fMax, IOUT = 0mA VCC = Max, CE > VIH f = fMax VCC = Max, CE > VCC–0.2V ISB1 VIN < 0.2V or VIN > VCC–0.2V, f = 0 VOL IOL = 8 mA, VCC = Min VOH IOH = –4 mA, VCC = Min Output voltage Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)4 Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE I/O Test conditions Vin = 0V Vin = Vout = 0V Max 5 7 Unit pF pF 9/24/04; v.1.2 Alliance Semiconductor P. 3 of 9 AS7C256A ® Read cycle (over the operating range)2,8 -10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE LOW to output in low Z CE HIGH to output in high Z OE LOW to output in low Z OE HIGH to output in high Z Power up time Power down time Symbol Min tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD 10 – – – 3 3 – 0 – 0 – Max – 10 10 5 – – 3 – 3 – 10 Min 12 – – – 3 3 – 0 – 0 – -12 Max – 12 12 6 – – 3 – 3 – 12 Min 15 – – – 3 3 – 0 – 0 – -15 Max – 15 15 7 – – 4 – 4 – 15 Min 20 – – – 3 3 – 0 – 0 – -20 Max – 20 20 8 – – 5 – 5 – 20 Unit ns ns ns ns ns ns ns ns ns ns ns 4 3,4 3,4 3,4 3,4 3,4 3,4 2 2 Notes Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)2,5,6,8 tRC Address tAA Dout Data valid tOH Read waveform 2 (CE controlled)2,5,7,8 tRC1 CE tOE OE tOLZ Dout tCLZ Supply current tPU 50% tACE Data valid tPD 50% ICC ISB tOHZ tCHZ 9/24/04; v.1.2 Alliance Semiconductor P. 4 of 9 AS7C256A ® Write cycle (over the operating range)9 -10 Parameter Write cycle time Chip enable to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Symbol tWC tCW tAW tAS tWP tWR tAH tDW tDH tWZ tOW Min 10 8 8 0 7 0 0 5 0 – 3 Max – – – – – – – – – 5 – Min 12 8 8 0 8 0 0 6 0 – 3 -12 Max – – – – – – – – – 6 – Min 15 10 10 0 9 0 0 8 0 – 3 -15 Max – – – – – – – – – 7 – Min 20 12 12 0 12 0 0 10 0 – 3 -20 Max – – – – – – – – – 8 – Unit ns ns ns ns ns ns ns ns ns ns ns 3,4 3,4 3,4 Notes Write waveform 1 (WE controlled)9 tWC tAW Address WE tAS Din tWZ Dout tWP tDW Data valid tOW tWR tDH tAH Write waveform 2 (CE controlled)9 tAW Address tAS CE WE tDW Din Data valid tDH tCW tWR tWC tAH 9/24/04; v.1.2 Alliance Semiconductor P. 5 of 9 AS7C256A ® AC test conditions - Output load: see Figure B Input pulse level: GND to VCC See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. +5.0V Dout 255Ω 480Ω C10 Dout Thevenin equivalent 168Ω VCC GND 90% 10% 2 ns 90% 10% +1.72V Figure A: Input pulse GND Figure B: Output load Notes 1 2 3 4 5 6 7 8 9 10 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. For test conditions, see AC Test Conditions, Figures A, B. These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. All write cycle timings are referenced from the last valid address to the first transitioning address. C=30pF, except on High Z and Low Z parameters, where C=5pF. 9/24/04; v.1.2 Alliance Semiconductor P. 6 of 9 AS7C256A ® Package diagrams 28-pin SOJ e D B A b Pin 1 A2 E c 28-pin SOJ Min Max in inches A A1 A2 B b c D E E1 E2 e 0.128 0.148 0.026 0.095 0.105 0.026 0.032 0.016 0.020 0.007 0.010 0.720 0.730 0.255 0.275 0.295 0.305 0.330 0.340 0.050 BSC E1 E2 A1 Seating Plane 28-pin TSOP1 b e c L A2 A A1 28-pin TSOP1 8×13.4 mm Min Max A A1 A2 b c D e E Hd L α 1.00 1.20 0.05 0.15 0.91 1.05 0.17 0.27 0.10 0.20 11.70 11.90 0.55 nominal 7.90 8.10 13.20 13.60 0.50 0.70 0° 5° D Hd α E 9/24/04; v.1.2 Alliance Semiconductor P. 7 of 9 AS7C256A ® Ordering information Package / Access time Plastic SOJ, 300 mil TSOP 8x13.4mm Temperature Commercial Industrial Commercial Industrial 10 ns AS7C256A-10JC AS7C256A-10JI AS7C256A-10TC AS7C256A-10TI 12 ns AS7C256A-12JC AS7C256A-12JI AS7C256A-12TC AS7C256A-12TI 15 ns AS7C256A-15JC AS7C256A-15JI AS7C256A-15TC AS7C256A-15TI 20 ns AS7C256A-20JC AS7C256A-20JI AS7C256A-20TC AS7C256A-20TI Note: Add suffix ‘N’to the above part number for lead free parts. (Ex. AS7C256A-10JIN) Part numbering system AS7C 256A –XX Packages: SRAM prefix Device number Access time J = SOJ 300 mil T = TSOP 8x13.4mm X C or I Temperature range: C = 0 oC to 70 0C X N= Lead Free Part I = -40C to 85C 9/24/04; v.1.2 Alliance Semiconductor P. 8 of 9 ® AS7C256A ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C256A Document Version: v.1.2 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such lifesupporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.