AS7C31025A-12TJC

January 2001 Advance Information ® AS7C1025A AS7C31025A 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) Features • • • • • AS7C1025A (5V version) AS7C31025A (3.3V version) Industrial and commercial temperatures Organization: 131,072 x 8 bits High speed - 10/10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time • Low power consumption: ACTIVE - 660 mW (AS7C1025A) / max @ 10 ns (5V) - 324 mW (AS7C31025A) / max @ 10 ns (3.3V) • Low power consumption: STANDBY - 55 mW (AS7C1025A) / max CMOS (5V) - 36 mW (AS7C31025A) / max CMOS (3.3V) • • • • • • Latest 6T 0.25u CMOS technology 2.0V data retention Easy memory expansion with CE, OE inputs Center power and ground TTL/LVTTL-compatible, three-state I/O JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ - 32-pin, TSOP II • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA 32-pin TSOP II A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 Pin arrangement Logic block diagram VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O7 Row decoder 512×256×8 Array (1,048,576) Sense amp 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) I/O0 WE OE CE A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 Column decoder A9 A10 A11 A12 A13 A14 A15 A16 Control circuit Selection guide AS7C1025A-10 AS7C31025A-10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C1025A AS7C31025A AS7C1025A AS7C31025A 10 3 120 90 10 10 AS7C1025A-12 AS7C31025A-12 12 3 110 80 10 10 AS7C1025A-15 AS7C31025A-15 15 4 100 80 10 10 AS7C1025A-20 AS7C31025A-20 20 5 100 80 15 15 Unit ns ns mA mA mA mA 2/6/01; V.0.9 Alliance Semiconductor AS7C1025A AS7C31025A AS7C1025A AS7C31025A P. 1 of 8 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C1025A AS7C31025A Functional description The AS7C1025A and AS7C31025A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high the devices enter standby mode. The standard AS7C1025A is guaranteed not to exceed 55 mW power consumption in standby mode. Both devices also offer 2.0V data retention. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025A) or 3.3V supply (AS7C31025A). The AS7C1025A and AS7C31025A are packaged in common industry standard packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Device AS7C1025A AS7C31025A Symbol Vt1 Vt1 Vt2 PD Tstg Tbias IOUT Min –0.50 –0.50 –0.50 – –65 –55 – Max +7.0 +5.0 VCC + 0.5 1.0 +150 +125 20 Unit V V V W o o C C mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L L WE X H H L OE X H L X Data High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC) Key: X = Don’t Care, L = Low, H = High 2/6/01; V.0.9 Alliance Semiconductor P. 2 of 8 ® AS7C1025A AS7C31025A Recommended operating conditions Parameter Supply voltage Device AS7C1025A AS7C31025A AS7C1025A Input voltage AS7C31025A Both Ambient operating temperature † VIL min. = –3.0V for pulse width less than tRC/2. Symbol VCC VCC VIH VIH VIL† TA TA Min 4.5 3.0 2.2 2.0 –0.5 0 –40 Nominal 5.0 3.3 – – – – – Max 5.5 3.6 VCC + 0.5 VCC + 0.5 0.8 70 85 Unit V V V V V o o commercial industrial C C DC operating characteristics (over the operating range)1 -10 Parameter Input leakage current Output leakage current Operating power supply current Standby power supply current1 Output voltage Data retention current -12 Min – -15 Min – -20 Sym | ILI | Test conditions VCC = Max, VIN = GND to VCC VCC = Max, CE = VIH, Vout = GND to VCC Device Both Min – Max 1 Max 1 Max Min Max Unit 1 – 1 µA | ILO | Both AS7C1025A – – – – – – – – 2.4 1 120 90 30 30 10 10 .04 – – – – – – – – 2.4 1 110 80 25 25 10 10 0.4 – – – – – – – – – 2.4 1 100 80 20 20 10 10 0.4 – – – – – – – – – 2.4 1 100 80 20 20 15 15 0.4 – µA ICC CE = VIL, f = fMax, IOUT = 0 mA AS7C31025A AS7C1025A AS7C31025A AS7C1025A AS7C31025A AS7C1025A AS7C31025A mA ISB ISB1 VOL VOH ICCDR CE = VIH, f = fMax, fOUT = 0 CE ≥ VCC–0.2V, VIN ≤ 0.2V or VIN ≥ VCC –0.2V, f = 0, fOUT = 0 IOL = 8 mA, VCC = Min IOH = –4 mA, VCC = Min VCC = 2.0V CE ≥ VCC – 0.2V VIN ≥ VCC – 0.2V or VIN ≤ 0.2V mA mA V V mA mA AS7C1025A AS7C31025A – – 1 1 – – 1 1 – – 1 1 – 5 5 Capacitance (f = 1 MHz, Ta = 25 oC, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF 2/6/01; V.0.9 Alliance Semiconductor P. 3 of 8 ® AS7C1025A AS7C31025A Read cycle (over the operating range)3,9 -10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE Low to output in low Z CE Low to output in high Z OE Low to output in low Z OE High to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD 10 – – – 2 0 – 0 – 0 – – 10 10 3 – – 3 – 3 – 10 12 – – – 3 0 – 0 – 0 – -12 – 12 12 3 – – 3 – 3 – 12 15 – – – 3 0 – 0 – 0 – -15 – 15 15 4 – – 4 – 4 – 15 20 – – – 3 0 – 0 – 0 – -20 Min Max – 20 20 5 – – 5 – 5 – 20 Unit ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 3 3 Notes Min Max Min Max Min Max Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tAA DOUT Data valid tOH Read waveform 2 (CE and OE controlled)3,6,8,9 CE tOE OE DOUT Supply current tPU tACE tCLZ 50% Data valid tPD 50% ICC ISB tOLZ tOHZ tCHZ tRC1 2/6/01; V.0.9 Alliance Semiconductor P. 4 of 8 ® AS7C1025A AS7C31025A Write cycle (over the operating range)11 -10 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW 1 Min 10 8 8 0 7 0 5 0 6 12 10 9 0 8 0 6 0 – 1 -12 Max – – – – – – – – 6 – 15 12 10 0 9 0 8 0 – 1 -15 Min Max – – – – – – – – 6 – 20 12 12 0 12 0 10 0 – 2 -20 Min Max – – – – – – – – 8 – Unit ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 Notes Max Min Write waveform 1 (WE controlled)10,11 tWC tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tAH Write waveform 2 (CE controlled)10,11 tAW Address tAS CE tWP WE tWZ DIN DOUT tDW Data valid tDH tCW tWC tAH 2/6/01; V.0.9 Alliance Semiconductor P. 5 of 8 ® AS7C1025A AS7C31025A Data retention characteristics (over the operating range) Parameter VCC for data retention Data retention current Chip enable to data retention time Operation recovery time Input leakage current Symbol VDR ICCDR tCDR tR | ILI | Test conditions VCC = 2.0V CE ≥ VCC – 0.2V VIN ≥ VCC – 0.2V or VIN ≤ 0.2V Min 2.0 – 0 tRC – Max – 500 – – 1 Unit V µA ns ns µA Data retention waveform Data retention mode VCC VCC tCDR CE VIH VDR VIH VDR ≥ 2.0V VCC tR AC test conditions – – – – Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent: 168W DOUT +1.728V (5V and 3.3V) +5V 480W +3.0V GND 90% 10% 2 ns 90% 10% DOUT 255W C(14) DOUT 255W +3.3V 320W C(14) Figure A: Input pulse GND Figure B: 5V Output load GND Figure C: 3.3V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. NA. C=30pF, except all high Z and low Z parameters, where C=5pF. 2/6/01; V.0.9 Alliance Semiconductor P. 6 of 8 ® AS7C1025A AS7C31025A Package dimensions 32-pin TSOP II 32-pin TSOP II (mm) Symbol Min – 0.05 0.3 0.12 20.82 10.03 11.56 1.27 BSC 0.40 0.95 REF. 0° 5° 0.60 Max 1.2 0.15 0.52 0.21 21.08 10.29 11.96 A A1 b E1 E N N/2+1 C D E1 1 D N/2 E e A Seating plane ZD L ZD α c b A1 L α c 32-pin SOJ 300 mil Symbol A A1 A2 Min 0.025 0.086 0.026 0.014 0.006 0.820 0.250 0.292 0.330 Max 0.145 0.105 0.032 0.020 0.013 0.830 0.275 0.305 0.340 32-pin SOJ 400 mil Min 0.025 0.086 0.026 0.015 0.007 0.820 0.360 0.395 0.435 Max 0.145 0.115 0.032 0.020 0.013 0.830 0.380 0.405 0.445 32-pin SOJ 300 mil/400 mil e D B b E1 E2 c D E A b Seating Plane Pin 1 A1 c A2 E B E1 E2 e 0.050 BSC 0.050 BSC 2/6/01; V.0.9 Alliance Semiconductor P. 7 of 8 ® AS7C1025A AS7C31025A Ordering codes Package \ Access time Voltage 5V TSOP II 3.3V 5V 300-mil SOJ 3.3V 5V 400-mil SOJ 3.3V Temperature Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 10 ns AS7C1025A-10TC AS7C1025A-10TI AS7C31025A-10TC AS7C31025A-10TI AS7C1025A-10TJC AS7C1025A-10TJI AS7C31025A-10TJC AS7C31025A-10TJI AS7C1025A-10JC AS7C1025A-10JI AS7C31025A-10JC AS7C31025A-10JI 12 ns AS7C1025A-12TC AS7C1025A-12TI AS7C31025A-12TC AS7C31025A-12TI AS7C1025A-12TJC AS7C1025A-12TJI AS7C31025A-12TJC AS7C31025A-12TJI AS7C1025A-12JC AS7C1025A-12JI AS7C31025A-12JC AS7C31025A-12JI 15 ns AS7C1025A-15TC AS7C1025A-15TI AS7C31025A-15TC AS7C31025A-15TI AS7C1025A-15TJC AS7C1025A-15TJI AS7C31025A-15TJC AS7C31025A-15TJI AS7C1025A-15JC AS7C1025A-15JI AS7C31025A-15JC AS7C31025A-15JI 20 ns AS7C1025A-20TC AS7C1025A-20TI AS7C31025A-20TC AS7C31025A-20TI AS7C1025A-20TJC AS7C1025A-20TJI AS7C31025A-20TJC AS7C31025A-20TJI AS7C1025A-20JC AS7C1025A-20JI AS7C31025A-20JC AS7C31025A-20JI Part numbering system AS7C SRAM prefix X Blank=5V CMOS 3=3.3V CMOS 1025 Device number –XX Access time X Package: T = TSOP II J = SOJ X Temperature range C = Commercial, 0°C to 70°C I = Industrial, -40°C to 85°C 2/6/01; V.0.9 Alliance Semiconductor P. 8 of 8 © Copyright Alliance Semiconductor Corporation. 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