AS7C31026B-15JCN

March 2004 ® AS7C31026B 3.3 V 64K X 16 CMOS SRAM Features • Industrial and commercial versions • Organization: 65,536 words × 16 bits • Center power and ground pins for low noise • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time • Low power consumption: ACTIVE - 288 mW / max @ 10 ns • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packaging • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 • Low power consumption: STANDBY - 18 mW / max CMOS I/O • 6 T 0.18 u CMOS technology Logic block diagram A0 Pin arrangement VCC A2 A3 A4 A5 A6 A7 I/O0–I/O7 I/O8–I/O15 Row decoder A1 44-Pin SOJ (400 mil), TSOP 2 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 64 K × 16 Array GND WE Column decoder A8 A9 A10 A11 A12 A13 A14 A15 UB OE LB CE Selection guide -10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current -12 12 6 75 5 -15 15 7 70 5 AS7C31026B I/O buffer Control circuit -20 20 8 65 5 Unit ns ns mA mA 10 5 80 5 3/26/04, v 1.3 Alliance Semiconductor P. 1 of 10 Copyright © Alliance Semiconductor. All rights reserved. AS7C31026B ® Functional description The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The device is packaged in common industry standard packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min –0.50 –0.50 – –65 –55 – Max +5.0 VCC +0.50 1.0 +150 +125 20 Unit V V W °C °C mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L L L L L L L WE X H H H L L L H X OE X L L L X X X H X LB X L H L L L H X H UB X H L L L H L X H I/O0–I/O7 High Z DOUT High Z DOUT DIN DIN High Z High Z I/O8–I/O15 High Z High Z DOUT DOUT DIN High Z DIN High Z Mode Standby (ISB), ISBI) Read I/O0–I/O7 (ICC) Read I/O8–I/O15 (ICC) Read I/O0–I/O15 (ICC) Write I/O0–I/O15 (ICC) Write I/O0–I/O7 (ICC) Write I/O8–I/O15 (ICC) Output disable (ICC) Key: H = high, L = low, X = don’t care. 3/26/04, v 1.3 Alliance Semiconductor P. 2 of 10 AS7C31026B ® Recommended operating conditions Parameter Supply voltage Input voltage commercial industrial Symbol VCC VIH VIL Ambient operating temperature VIL = -1.0V for pulse width less than 5ns VIH = VCC + 1.5V for pulse width less than 5ns Min 3.0 2.0 –0.5 0 –40 Nominal 3.3 – – – – Max 3.6 VCC + 0.5 0.8 70 85 Unit V V V o o TA TA C C DC operating characteristics (over the operating range)1 -10 Parameter Input leakage current Output leakage current Operating power supply current -12 Max 1 -15 Min – -20 Min – Sym | ILI | | ILO | Test conditions VCC = Max VIN = GND to VCC VCC = Max CE = VIH, VOUT = GND to VCC VCC = Max, CE ≤ VIL, IOUT = 0mA f = fMax VCC = Max, CE ≥ VIH, f = fMax VCC = Max, CE ≥ VCC–0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC–0.2 V, f = 0 IOL = 8 mA, VCC = Min IOH = –4 mA, VCC = Min Min Max Min – 1 – Max 1 Max 1 Unit µA – 1 – 1 – 1 – 1 µA ICC ISB ISB1 VOL VOH – 80 – 75 – 70 – 65 mA Standby power supply current Output voltage – 30 – 25 – 20 – 20 mA – – 2.4 5 0.4 – – – 2.4 5 0.4 – – – 2.4 5 0.4 – – – 2.4 5 0.4 – mA V V Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE, LB, UB I/O Test conditions VIN = 0 V VIN = VOUT = 0 V Max 5 7 Unit pF pF 3/26/04, v 1.3 Alliance Semiconductor P. 3 of 10 AS7C31026B ® Read cycle (over the operating range)3,9 -10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE low to output in low Z CE high to output in high Z OE low to output in low Z Byte select access time Byte select Low to low Z Byte select High to high Z OE high to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tBA tBLZ tBHZ tOHZ tPU tPD Min 10 – – – 3 3 – 0 – 0 – – 0 – Max – 10 10 5 – – 3 – 5 – 5 5 – 10 Min 12 – – – 3 3 – 0 – 0 – – 0 – -12 Max – 12 12 6 – – 3 – 6 – 6 6 – 12 Min 15 – – – 3 3 – 0 – 0 – – 0 – -15 Max – 15 15 7 – – 4 – 7 – 6 7 – 15 Min 20 – – – 3 3 – 0 – 0 – – 0 -20 Max – 20 20 8 – – 5 – 8 – 8 8 – 20 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 4, 5 4, 5 5 4, 5 4, 5 4, 5 3 3 Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address DataOUT tOH Previous data valid tAA Data valid tOH 3/26/04, v 1.3 Alliance Semiconductor P. 4 of 10 AS7C31026B ® Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9 tRC Address tAA OE tOLZ CE tLZ LB, UB tBLZ DataIN tBA Data valid tBHZ tACE tOHZ tHZ tOE tOH Write cycle (over the operating range) 11 -10 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Byte select low to end of write Symbol tWC tCW tAW tAS tWP tWR tAH tDW tDH tWZ tOW tBW Min 10 8 8 0 7 0 0 5 0 – 1 7 Max – – – – – – – – – 5 – – 12 9 9 0 8 0 0 6 0 – 1 8 -12 – – – – – – – – – 6 – – 15 10 10 0 9 0 0 8 0 – 1 9 -15 Max – – – – – – – – – 7 – – 20 12 12 0 12 0 0 10 0 – 2 9 -20 Min Max – – – – – – – – – 8 – – Unit ns ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 Notes Min Max Min 3/26/04, v 1.3 Alliance Semiconductor P. 5 of 10 AS7C31026B ® Write waveform 1 (WE controlled)10,11 tWC tAH Address tCW CE tBW LB, UB tAS WE tDW DataIN tWZ DataOUT Data undefined Data valid tOW high Z tDH tAW tWP tWR Write waveform 2 (CE controlled)10,11 tWC Address tAS CE tCW tAW tBW LB, UB tWP WE tDW DataIN tCLZ DataOUT high Z tWZ Data undefined high Z Data valid tOW tDH tWR tAH 3/26/04, v 1.3 Alliance Semiconductor P. 6 of 10 AS7C31026B ® AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.0 V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5 Thevenin Equivalent: 168 Ω DOUT +1.728 V +3.3 V 320 Ω +3.0 V GND DOUT 90% 10% 2 ns 90% 10% 255 Ω C13 Figure A: Input pulse GND Figure B: 3.3 V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 3/26/04, v 1.3 Alliance Semiconductor P. 7 of 10 AS7C31026B ® Package dimensions 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 c 44-pin TSOP 2 Min (mm) Max (mm) 1.2 0.05 0.95 0.30 44-pin TSOP 2 E He A A1 A2 0.15 1.05 0.45 0.21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 b c D D l 0.120 18.31 10.06 18.52 10.26 11.94 0.60 A A1 b e A2 0–5° E He e l 11.68 0.40 0.80 (typical) D e 44-pin SOJ 400 mil Min (in) Max (in) A A1 A2 0.128 0.025 0.105 0.026 0.015 0.007 1.120 0.395 0.435 0.148 – 0.115 0.032 0.020 0.013 1.130 0.405 0.445 44-pin SOJ E1 E2 Pin 1 B A2 A A1 b c B b c D E E1 E2 e Seating plane E 0.370 NOM 0.050 NOM 3/26/04, v 1.3 Alliance Semiconductor P. 8 of 10 AS7C31026B ® Ordering codes Package\Access time Plastic SOJ, 400 mil TSOP 2, 10.2 x 18.4 mm Volt/Temp 3.3 V industrial 3.3 V industrial 10 ns AS7C31026B-10JI AS7C31026B-10TI 12 ns AS7C31026B-12JC AS7C31026B-12JI AS7C31026B-12TC AS7C31026B-12TI 15 ns AS7C31026B-15JC AS7C31026B-15JI AS7C31026B-15TC AS7C31026B-15TI 20 ns AS7C31026B-20JC AS7C31026B-20JI AS7C31026B-20TC AS7C31026B-20TI 3.3 V commercial AS7C31026B-10JC 3.3 V commercial AS7C31026B-10TC Note: Add suffix ‘N’ to the above part number for lead free parts (Ex. AS7C31026B-10JCN) Part numbering system AS7C SRAM prefix X Voltage: 1026B –XX X Package: X X Temperature range: N=Lead Free C = commercial: 0° C to 70° C J = SOJ 400 mil Part T = TSOP 2, 10.2 x 18.4 mm I = industrial: -40° C to 85° C Device Access 3 = 3.3 V CMOS number time 3/26/04, v 1.3 Alliance Semiconductor P. 9 of 10 AS7C31026B ® ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C31026B Document Version: v 1.3 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. 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