AS7C31026C-12TINTR

September 2006 Advance Information AS7C31026C ® 3.3 V 64K X 16 CMOS SRAM Features • Industrial (-40o to 85oC) temperature • Organization: 65,536 words × 16 bits • Center power and ground pins for low noise • High speed - 12 ns address access time - 6 ns output enable access time • Low power consumption via chip deselect • Upper and Lower byte pin • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O Logic block diagram Control circuit Address decoder A8 WE I/O buffer UB OE LB CE A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AS7C31026C I/O0–I/O7 I/O8–I/O15 44-Pin SOJ (400 mil), TSOP 2 GND A15 A7 A14 A6 A13 A5 A11 A4 A12 A3 • ESD protection ? 2000 volts VCC 65,536 × 16 Array A9 A2 A10 A1 - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 - 48-ball 7 × 7 mm BGA Pin arrangement Address decoder A0 • JEDEC standard packaging 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 0000048 - BGA Ball-Grid-Array Package 1 A LB B I/O8 C I/O9 D VSS E VDD F I/O14 G I/O15 H NC 9/20/06, v 2.0 Alliance Memory 2 3 OE A0 UB A3 I/O10 A5 I/O11 NC I/O12 NC I/O13 A14 NC A12 A8 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VDD VSS I/O6 I/O7 NC P. 1 of 10 Copyright © Alliance Memory. All rights reserved. AS7C31026C ® Functional description The AS7C31026C is a 3V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for highperformance applications. When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31026C is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Voltage on VCC relative to GND Voltage on any pin relative to GND Min Storage temperature (plastic) Unit –0.50 VCC +0.50 V –55 +125 Vt1 –0.50 PD – Vt2 Power dissipation Max Tstg Ambient temperature with VCC applied Tbias DC current into outputs (low) +4.60 1.25 –55 IOUT W °C +125 – V °C 50 mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 L H L L H DOUT High Z DOUT DOUT DIN High Z High Z H L X H L H L L L L L L L L H X X L H X L L X X H X Key: H = high, L = low, X = don’t care. 9/20/06, v 2.0 X L X L High Z L DIN L L H X H X H H High Z L High Z Alliance Memory High Z DOUT Mode Standby (ISB), ISBI) Read I/O0–I/O7 (ICC) Read I/O8–I/O15 (ICC) Read I/O0–I/O15 (ICC) DIN Write I/O0–I/O15 (ICC) DIN Write I/O8–I/O15 (ICC) High Z Output disable (ICC) Write I/O0–I/O7 (ICC) P. 2 of 10 AS7C31026C ® Recommended operating conditions Supply voltage Parameter Symbol Min Nominal Max Unit VIH 2.0 – VCC + 0.5 V 3.0 VCC Input voltage VIL Ambient operating temperature (industrial) –0.5 3.6 – –40 TA VIL = -2.0V for pulse width less than 5ns, once per cycle. 3.3 0.8 – V V o 85 C VIH = VCC +2.0V for pulse width less than 5ns, once per cycle. DC operating characteristics (over the operating range)1 Parameter Sym Input leakage current | ILI | Output leakage current | ILO | Operating power supply current ICC ISB Standby power supply current ISB1 VOL Output voltage VOH Test conditions Min Max Unit – 5 µA – 5 µA – 160 mA – 45 mA VCC = Max, CE ? VCC–0.2 V, VIN ? 0.2 V or VIN ? VCC–0.2 V, f = 0 – 10 mA IOH = –4 mA, VCC = Min – 2.4 0.4 V Test conditions Max Unit VIN = VOUT = 0 V 7 pF VCC = Max VIN = GND to VCC VCC = Max CE = VIH, VOUT = GND to VCC VCC = Max, CE ? VIL, IOUT = 0mA f = fMax VCC = Max, CE ? VIH, f = fMax IOL = 8 mA, VCC = Min Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2 Parameter Input capacitance Symbol CIN Signals A, CE, WE, OE, LB, UB I/O I/O capacitance CI/O Note: 1. This parameter is guaranteed by device characterization, but is not production tested. 9/20/06, v 2.0 AS7C31026C-12 Alliance Memory VIN = 0 V – 6 V pF P. 3 of 10 AS7C31026C ® Read cycle (over the operating range)3,9 AS7C31026C-12 Parameter Read cycle time Symbol Min Max Unit Notes tAA – 12 ns 3 – 6 tRC Address access time Chip enable (CE) access time tACE Output enable (OE) access time tOE Output hold from address change tOH CE low to output in low Z tCLZ CE high to output in high Z tCHZ Byte select access time tBA OE low to output in low Z tOLZ Byte select Low to low Z tBLZ Byte select High to high Z tBHZ OE high to output in high Z tOHZ Power up time tPU Power down time tPD 12 – 4 4 – 0 – 0 – – 0 – – ns 12 ns ns – ns – 6 5 4, 5 ns 4, 5 ns – 6 – 4, 5 ns 4, 5 ns 12 4, 5 ns ns 6 5 ns ns – 3 ns 4, 5 4, 5 4, 5 Key to switching waveforms Rising input Falling input Read waveform 1 (address controlled)3,6,7,9 Undefined output/don’t care tRC Address DataOUT tAA tOH Previous data valid tOH Data valid Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9 tRC Address tAA OE tOE tOLZ tOH CE tLZ tOHZ tHZ tACE LB, UB tBLZ tBA DataIN 9/20/06, v 2.0 tBHZ Data valid Alliance Memory P. 4 of 10 AS7C31026C ® Write cycle (over the operating range) 11 Write cycle time Parameter Symbol tWC Chip enable (CE) to write end tCW Address setup time tAS Address setup to write end Write pulse width Min 12 8 tWP 8 – ns tDW Write enable to output in high Z tWZ 0 0 0 6 0 tDH – tOW 3 8 tBW Write waveform 1 (WE controlled)10,11 Notes ns ns Data valid to write end Byte select low to end of write – ns – tAH Output active from write end – Unit 8 tWR Data hold time Max tAW Write recovery time Address hold from end of write AS7C31026C-12 – ns – ns – ns – ns – ns 6 ns – ns – ns 5 4, 5 4, 5 tWC tAH Address tWR tCW CE tBW LB, UB tAW tAS tWP WE tDW DataIN DataOUT 9/20/06, v 2.0 tDH Data valid tWZ Data undefined Alliance Memory tOW high Z P. 5 of 10 AS7C31026C ® Write waveform 2 (CE controlled)10,11 tWC tAH Address tAS tWR tCW CE tAW tBW LB, UB tWP WE tDH tDW Data valid DataIN tWZ tCLZ DataOUT high Z Data undefined tOW high Z AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.0 V. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5 Thevenin Equivalent: 168 ? DOUT +1.728 V +3.3 V DOUT +3.0 V GND 90% 10% 90% 3 ns 255 ? 10% 320 ? C13 GND Figure B: 3.3 V Output load Figure A: Input pulse Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 9/20/06, v 2.0 Alliance Memory P. 6 of 10 AS7C31026C ® Package dimensions A E He 44-pin TSOP 2 44-pin TSOP 2 c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A1 A2 b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 c D A2 A A1 l 0–5° e b 0.05 0.15 0.30 0.45 0.95 0.120 18.31 He 11.68 l 0.40 E e 10.06 1.2 1.05 0.21 18.52 10.26 11.94 0.80 (typical) 0.60 44-pin SOJ 400 mil e 44-pin SOJ A E1 E2 Pin 1 c B A2 Seating plane E 0.128 0.148 0.025 B 0.026 0.032 0.007 0.013 A2 c D E E1 E2 e Alliance Memory Min (in) Max (in) A1 b A A1 9/20/06, v 2.0 Max (mm) D D b Min (mm) 0.105 0.015 1.120 – 0.115 0.020 1.130 0.370 NOM 0.395 0.435 0.405 0.445 0.050 NOM P. 7 of 10 AS7C31026C ® 48-ball BGA Bottom View 6 5 4 3 2 1 Ball A1 A Top View B/4 Ball #A1 index (see note 7) C/4 B (see note 8) C D SRAM DIE C1 F C G H J A B B1 *pin 1 indicator will show as engraved circle and/or Inc. trade mark Detail View Side View E E2 A D E2 E Die E1 A B Minimum – Typical 0.75 – – 3.75 – C1 – 5.25 – E 1.14 1.24 1.34 E2 0.15 0.20 0.25 Y 9/20/06, v 2.0 Maximum 7.00 BSC C7.00 BSC E1 Die 0.3/Tµp B1 D Y 0.25 – – 0.30 0.68 – 0.40 – Notes 1 Bump counts: 48 (8 row x 6 column). 2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3 Units: millimeters. 4 All tolerance are +/- 0.050 unless otherwise specified. 5 Typ: typical. 6 Y is coplanarity: 0.010 (max). 7 “A1” ID corner must be identified by chamfer, ink mark, metallized marking, indentation or other feature on the package body. 8 If “A1” ID corner is on the package body, it must be located within the zone indicated. 0.010 Alliance Memory P. 8 of 10 AS7C31026C ® Ordering codes Volt/Temp 12 ns Plastic SOJ, 400 mil Package 3.3V industrial AS7C31026C-12JIN TSOP 2, 10.2 x 18.4 mm 3.3V industrial AS7C31026C-12TIN BGA, 7 x 7 mm 3.3V industrial AS7C31026C-12BIN Part numbering system AS7C SRAM prefix 9/20/06, v 2.0 X Voltage: 3 = 3.3 V CMOS 1026B –XX Device Access number time X X Package: Temperature J = SOJ 400 mil I = industrial: -40° C T = TSOP 2, 10.2 x 18.4 mm to 85° C B=BGA, 7 x 7 mm Alliance Memory X N = Lead Free Part P. 9 of 10 AS7C31026C ® ® Alliance Memory, Inc. 511 Taylor Way San Carlos, CA 94070, USA Tel: 650-610-6800 Fax: 650-620-9211 Copyright © Alliance Memory All Rights Reserved Part Number: AS7C31026C-12JIN Document Version: v 2.0 www.alliancememory.com © Copyright 2008 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.