AS7C316096B-10BIN

AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 REVISION HISTORY Revision Rev. 1.0 Rev. 2.0 Confidential Description Initial Issue Typo error on page 1 - should be 44-pin 400 mil TSOP-II 0 Issue Date June.2014 Jan. 2017 Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 FEATURES GENERAL DESCRIPTION  Fast access time : 10ns  Low power consumption: Operating current : 70mA (TYP.) Standby current : 4mA(TYP.)  Single 3.3V power supply  All inputs and outputs TTL compatible  Fully static operation  Tri-state output  Data retention voltage : 1.5V (MIN.)  All parts are ROHS Compliant  Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA The AS7C316096B is a 16M-bit high speed CMOS static random access memory organized as 2048K words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS7C316096B operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible Table 1. Speed Grade Information Product Family AS7C316096B VCC Range Speed 2.7 ~ 3.6V 10ns Power Dissipation Standby(ISB1,TYP.) Operating(ICC,TYP.) 4mA 70mA Table 2. Ordering Information Product part No Org Temperature Package AS7C316096B-10TIN 2048K x 8 Industrial -40°C to 85°C 44-pin 400mil TSOP-II AS7C316096B-10BIN 2048K x 8 Industrial -40°C to 85°C 48-ball 6mm x 8mm TFBGA Confidential 1 Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0-A20 DQ0-DQ7 CE# CE2 WE# OE# Confidential PIN DESCRIPTION DECODER I/O DATA CIRCUIT 2048Kx8 MEMORY ARRAY COLUMN I/O CONTROL CIRCUIT 2 SYMBOL DESCRIPTION A0 – A20 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE#, CE2 Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 PIN CONFIGURATION 54 NC 2 53 Vss NC 3 52 NC DQ6 4 51 DQ5 Vss 5 50 Vcc DQ7 6 49 DQ4 A4 7 48 A5 A3 8 47 A6 A2 9 46 A7 A1 10 45 A8 A0 11 44 A9 NC 12 43 NC CE# 13 42 OE# Vcc 14 41 Vss WE# 15 40 NC CE2 16 39 A20 A19 17 38 A10 A18 18 37 A11 A17 19 36 A12 A16 20 35 A13 A15 21 34 A14 DQ0 22 33 DQ3 Vcc 23 32 Vss DQ1 24 31 DQ2 NC 25 30 NC Vss 26 29 Vcc NC 27 28 NC AS7C316096B 1 XXXXXXXX XXXX NC Vcc TSOP II(Top View) NC OE# A0 A1 A2 CE2 B NC NC A3 A4 CE# NC C DQ0 NC A5 A6 NC DQ4 D Vss DQ1 A17 A7 E Vcc DQ2 A18 A16 DQ6 Vss F DQ3 NC A14 A15 G NC NC A12 A13 WE# NC H A19 A8 A9 A10 A11 A20 1 2 3 4 TFBGA 5 6 Confidential DQ5 Vcc NC DQ7 AS7C316096B XXXXX XXXX A TFBGA 3 Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 RATING -0.5 to 4.6 -0.5 to VCC+0.5 UNIT V V TA -40 to 85(I grade) ℃ TSTG PD IOUT -65 to 150 1 50 ℃ Operating Temperature Storage Temperature Power Dissipation DC Output Current W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE CE# CE2 OE# WE# H X X X L X Output Disable L H Read L L MODE Standby Write Note: SUPPLY CURRENT X I/O OPERATION High-Z X High-Z ISB1 H H High-Z ICC H L H DOUT ICC H X L DIN ICC ISB1 H = VIH, L = VIL, X = don’t care. DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Average Operating Power supply Current Standby Power Supply Current SYM. TEST CONDITION VCC *1 VIH *2 VIL ILI VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, ILO Output Disabled VOH IOH = -4mA VOL IOL = 8mA CE# ≤0.2V and CE2≧ VCC-0.2V, ICC other pins at 0.2V or VCC-0.2V, -10 II/O = 0mA; f=max. CE# ≧ VCC - 0.2V; ISB1 Other pins at 0.2V or VCC-0.2V. MIN. 2.7 2.2 - 0.3 -1 TYP. 3.3 - *4 MAX. 3.6 VCC+0.3 0.8 1 UNIT V V V µA -1 - 1 µA 2.4 - - 0.4 V V - 70 120 mA 4 40 mA - Notes: 1. VIH(MAX) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(MIN) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ Confidential 4 Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 8 10 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS speed Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 10ns 0.2V to Vcc-0.2V 3ns VCC/2 CL = 30pF + 1TTL, IOH/IOL = -8mA/4mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* AS7C316096B-10 MIN. MAX. 10 10 10 4.5 2 0 4 4 2 - UNIT AS7C316096B-10 MIN. MAX. 10 8 8 0 8 0 6 0 2 4 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Confidential 5 Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Confidential 6 Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Confidential 7 Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V VCC = 1.5V CE# ≧ VCC - 0.2V Data Retention Current IDR or CE2 ≦ 0.2V Other pins at 0.2V or VCC-0.2V Chip Disable to Data See Data Retention tCDR Retention Time Waveforms (below) Recovery Time tR tRC* = Read Cycle Time MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 4 40 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ¡Ù 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ¡Ù Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ¡Ù 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE2 Confidential tR CE2 ¡Ø 0.2V VIL VIL 8 Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 PACKAGE OUTLINE DIMENSION 54-pin 400 mil TSOP-II Package Outline Dimension Confidential 9 Rev 2.0 – Jan 2017 AS7C316096B Preliminary 1.0 2048K X 8 BIT HIGH SPEED CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension Confidential 10 Rev 2.0 – Jan 2017 AS7C316096B 2048K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 1.0 Alliance Memory Inc. reserves the rights to change the specifications and products without notice. Alliance Memory, Inc., 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 Confidential 11 Rev 2.0 – Jan 2017