AS7C316098B-10TIN

AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 REVISION HISTORY Revision Rev. 1.0 Confidential Description Initial Issued Issue Date June 2014 0 Rev1.0 – June 2014 AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 FEATURES GENERAL DESCRIPTION  Fast access time : 10ns  low power consumption: Operating current : 70mA (TYP.) Standby current : 4mA(TYP.)  Single 3.3V power supply  All inputs and outputs TTL compatible  Fully static operation  Tri-state output  Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15)  Data retention voltage : 1.5V (MIN.)  All parts are ROHS Compliant  Package : 54-pin 400 mil TSOP-II The AS7C316098B is a 16M-bit high speed CMOS static random access memory organized as 1024K words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS7C316098B operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible Table 1. Speed Grade Information Product Family AS7C316098B Vcc Range Speed 2.7 ~ 3.6V 10ns Power Dissipation Standby(ISB1,TYP.) Operating(ICC,TYP.) 4mA 70mA Table 2. Ordering Information Product part No AS7C316098B-10TIN Confidential Org 1024K x 16 Temperature Package Industrial -40°C to 85°C 1 54-pin 400mil TSOP-II Rev1.0 – June 2014 AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss SYMBOL DESCRIPTION A0 - A19 Address Inputs DQ0 – DQ15 Data Inputs/Outputs A0-A19 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# CE2 WE# OE# LB# UB# Confidential DECODER I/O DATA CIRCUIT 1024Kx16 MEMORY ARRAY COLUMN I/O CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground CONTROL CIRCUIT 2 Rev1.0 – June 2014 AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 PIN CONFIGURATION 54 DQ11 2 53 Vss DQ13 3 52 DQ10 DQ14 4 51 DQ9 Vss 5 50 Vcc DQ15 6 49 DQ8 A4 7 48 A5 A3 8 47 A6 A2 9 46 A7 A1 10 45 A8 A0 11 44 A9 UB# 12 43 NC CE# 13 42 OE# Vcc 14 41 Vss WE# 15 40 NC CE2 16 39 LB# A19 17 38 A10 A18 18 37 A11 A17 19 36 A12 A16 20 35 A13 A15 21 34 A14 DQ0 22 33 DQ7 Vcc 23 32 Vss DQ1 24 31 DQ6 DQ2 25 30 DQ5 Vss 26 29 Vcc DQ3 27 28 DQ4 AS7C316098B 1 Vcc XXX XXXX XXXXXXXXX DQ12 TSOP II(Top View) Confidential 3 Rev1.0 – June 2014 AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on Vcc relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature TA Storage Temperature Power Dissipation DC Output Current TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to Vcc+0.5 UNIT V V -40 to 85(I grade) ℃ -65 to 150 1 50 ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# CE2 OE# WE# LB# UB# H X L L L L L L L L X L H H H H H H H H X X H H L L L X X X X X H H H H H L L L X X L X L H L L H L X X X L H L L H L L I/O OPERATION SUPPLY CURRENT DQ0-DQ7 DQ8-DQ15 High – Z High – Z ISB1 High – Z High – Z High – Z High – Z ICC High – Z High – Z DOUT High – Z High – Z DOUT ICC DOUT DOUT DIN High – Z High – Z DIN ICC DIN DIN H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Average Operating Power supply Current Standby Power Supply Current SYM. TEST CONDITION VCC *1 VIH *2 VIL ILI VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, ILO Output Disabled VOH IOH = -4mA VOL IOL = 8mA CE# ≤0.2V and CE2≧ VCC-0.2V, ICC other pins at 0.2V or VCC-0.2V, -10 II/O = 0mA; f=max. CE# ≧ VCC - 0.2V; ISB1 other pins at 0.2V or VCC-0.2V. MIN. 2.7 2.2 - 0.3 -1 TYP. 3.3 - *4 MAX. 3.6 VCC+0.3 0.8 1 UNIT V V V µA -1 - 1 µA 2.4 - - 0.4 V V - 70 120 mA 4 40 mA - Notes: 1. VIH(MAX) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(MIN) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ Confidential 4 Rev1.0 – June 2014 AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 8 10 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS speed Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 10ns 0.2V to Vcc-0.2V 3ns VCC/2 CL = 30pF + 1TTL, IOH/IOL = -8mA/4mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* AS7C316098B-10 MIN. MAX. 10 10 10 4.5 2 0 4 4 2 4.5 4 0 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* tBW AS7C316098B-10 MIN. MAX. 10 8 8 0 8 0 6 0 2 4 8 - UNIT ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Confidential 5 Rev1.0 – June 2014 AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Confidential 6 Rev1.0 – June 2014 AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din Confidential tDH Data Valid 7 Rev1.0 – June 2014 AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tAS tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Confidential 8 Rev1.0 – June 2014 AS7C316098B 1024K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.0 DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V VCC = 1.5V CE# ≧ VCC - 0.2V Data Retention Current IDR or CE2 ≦ 0.2V Other pins at 0.2V or VCC-0.2V Chip Disable to Data See Data Retention tCDR Retention Time Waveforms (below) Recovery Time tR tRC* = Read Cycle Time MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 4 40 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ¡Ù 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ¡Ù Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ¡Ù 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE2 Confidential tR CE2 ¡Ø 0.2V VIL VIL 9 Rev1.0 – June 2014 AS7C316098B Rev. 1.0 1024K X 16 BIT HIGH SPEED CMOS SRAM PACKAGE OUTLINE DIMENSION 54-pin 400 mil TSOP-II Package Outline Dimension Confidential 10 Rev1.0 – June 2014 AS7C316098B Rev. 1.0 1024K X 16 BIT HIGH SPEED CMOS SRAM Alliance Memory Inc. reserves the rights to change the specifications and products without notice. Alliance Memory, Inc., 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 Confidential 11 Rev1.0 – June 2014