AS7C33128PFD32B-200TQIN

February 2005 ® AS7C33128PFD32B AS7C33128PFD36B 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 131,072 words × 32 or 36 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs Logic block diagram LBO CLK ADV ADSC ADSP A[16:0] 17 CLK CE CLR D CE Address register CLK D Q0 Burst logic Q1 17 Q 15 17 128K × 32/36 Memory array GWE BWE BWd DQd Q Byte write registers CLK D DQc Q Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Power down D Enable Q delay register CLK Q 36/32 36/32 BWc BWb BWa CE0 CE1 CE2 4 OE Output registers CLK Input registers CLK ZZ OE 36/32 DQ [a:d] Selection guide –200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3.0 375 130 30 –166 6 166 3.5 350 100 30 –133 7.5 133 4 325 90 30 Units ns MHz ns mA mA mA 1/31/05; v.1.1 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. AS7C33128PFD32B AS7C33128PFD36B ® 4 Mb Synchronous SRAM products list1,2 Org 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 Part Number AS7C33256PFS18B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33128PFD32B AS7C33128PFD36B AS7C33256FT18B AS7C33128FT32B AS7C33128FT36B AS7C33256NTD18B AS7C33128NTD32B AS7C33128NTD36B AS7C33256NTF18B AS7C33128NTF32B AS7C33128NTF36B Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 1/31/05; v.1.1 Alliance Semiconductor P. 2 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Pin arrangement 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A DQPc/NC DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 NC VDD NC VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd/NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TQFP 14 × 20 mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS NC VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC 1/31/05; v.1.1 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A Note: Pins 1,30,51,80 are NC for ×32 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Alliance Semiconductor P. 3 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Functional description The AS7C33128PFD32B and AS7C33128PFD36B are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology. Timing for these devices is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP and PowerPC™1-based systems in computing, datacom, instrumentation, and telecommunications systems. Fast cycle times of 5.0/6.0/7.5 ns with clock access times (tCD) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High. Burst mode is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium® count sequence. With LBO driven LOW, the device uses a linear count sequence suitable for PowerPC™ and many other applications. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s). BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to the next burst address if BWn and ADV are sampled Low. This device operates in double-cycle deselect feature during read cycles. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are as follows: • ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC. • WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High). • Master chip enable CE0 blocks ADSP, but not ADSC. AS7C33128PFD32B and AS7C33128PFD36B family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package TQFP capacitance Parameter Input capacitance I/O capacitance * Guaranteed not tested Symbol CIN* CI/O * Test conditions VIN = 0V VOUT = 0V Min - Max 5 7 Unit pF pF TQFP thermal resistance Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 1 This parameter is sampled Conditions 1–layer Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 4–layer Symbol θJA θJA θJC Typical 40 22 8 Units °C/W °C/W °C/W 1 PowerPC™ is a trademark International Business Machines Corporation. 1/31/05; v.1.1 Alliance Semiconductor P. 4 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Signal descriptions Signal CLK A,A0,A1 DQ[a,b,c,d] CE0 CE1, CE2 ADSP ADSC ADV GWE BWE BW[a,b,c,d] OE LBO ZZ NC I/O I I I/O I I I I I I I I I I I Properties CLOCK SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC ASYNC STATIC ASYNC Description Clock. All inputs except OE, ZZ, LBO are synchronous to this clock. Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information. Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode. Address strobe controller. Asserted LOW to load a new address or to enter standby mode. Advance. Asserted LOW to continue burst read/write. Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d] control write enable. Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs. Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write cycle. If all BW[a:d] are inactive the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. Selects Burst mode. When tied to VDD or left floating, device follows Interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. Snooze. Places device in low power mode; data is retained. Connect to GND if unused. No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 1/31/05; v.1.1 Alliance Semiconductor P. 5 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Write enable truth table (per byte) Function Write All Bytes Write Byte a Write Byte c and d Read GWE L H H H H H BWE X L L L H L BWa X L L H X H BWb X L H H X H BWc X L H L X H BWd X L H L X H Key: X = don’t care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal. Asynchronous Truth Table Operation Snooze mode Read Write Deselected ZZ H L L L L OE X L H X X I/O Status High-Z Dout High-Z Din, High-Z High-Z Notes: 1. X means “Don’t Care” 2. ZZ pin is pulled down internally 3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Snooze mode means power down state of which stand-by current does not depend on cycle times 5. Deselected means power down state of which stand-by current depends on cycle times Burst sequence table Interleaved burst address (LBO = 1) A1 A0 1st Address 2 Address 3rd Address 4 Address th nd Linear burst address (LBO = 0) A1 A0 11 10 01 00 1st Address 2 nd A1 A0 01 00 11 10 A1 A0 10 11 00 01 A1 A0 00 01 10 11 Address A1 A0 01 10 11 10 A1 A0 10 11 00 01 A1 A0 11 00 01 10 00 01 10 11 3rd Address 4 Address th 1/31/05; v.1.1 Alliance Semiconductor P. 6 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Synchronous truth table[4] CE01 CE1 CE2 ADSP ADSC ADV WRITE[2] OE Address accessed CLK Operation DQ H L L L L L L L L X X X X H H H H L X H X H X L L X X H H H H X X X X X X X X H X X X X X X X H H L L L L X X X X X X X X L X X X X X L H L H L L H H H H H H X X X X H H X H X L X L X L X X L L H H H H H H H H L H H H H X X X X X X X X X L L H H L L H H X L L H H X X X X X X X H H H H H H H H H H L L L L L X X X X X L H L H L H L H L H L H X X X X X NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Continue read Continue read Suspend read Suspend read Continue read Continue read Suspend read Suspend read Begin write Continue write Continue write Suspend write Suspend write Hi−Z Hi−Z Hi−Z Hi−Z Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z D3 D D D D 1 X = don’t care, L = low, H = high 2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information. 3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time 4 ZZ pin is always Low. 1/31/05; v.1.1 Alliance Semiconductor P. 7 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation Short circuit output current Storage temperature Temperature under bias Symbol VDD, VDDQ VIN VIN Pd IOUT Tstg Tbias Min –0.5 –0.5 –0.5 – – –65 –65 Max +4.6 VDD + 0.5 VDDQ + 0.5 1.8 20 +150 +135 Unit V V V W mA o o C C Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Recommended operating conditions at 3.3V I/O Parameter Supply voltage for inputs Supply voltage for I/O Ground supply Symbol VDD VDDQ Vss Min 3.135 3.135 0 Nominal 3.3 3.3 0 Max 3.465 3.465 0 Unit V V V Recommended operating conditions at 2.5V I/O Parameter Supply voltage for inputs Supply voltage for I/O Ground supply Symbol VDD VDDQ Vss Min 3.135 2.375 0 Nominal 3.3 2.5 0 Max 3.465 2.625 0 Unit V V V 1/31/05; v.1.1 Alliance Semiconductor P. 8 of 19 AS7C33128PFD32B AS7C33128PFD36B ® DC electrical characteristics for 3.3V I/O operation Parameter Input leakage current† Sym |ILI| |ILO| VIH VIL VOH VOL Conditions VDD = Max, 0V < VIN < VDD OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ Address and control pins I/O pins Address and control pins I/O pins IOH = –4 mA, VDDQ = 3.135V IOL = 8 mA, VDDQ = 3.465V Min -2 -2 2* 2* -0.3** -0.5** 2.4 – Max 2 2 VDD+0.3 VDDQ+0.3 0.8 0.8 – 0.4 Unit µA µA V Output leakage current Input high (logic 1) voltage Input low (logic 0) voltage Output high voltage Output low voltage V V V DC electrical characteristics for 2.5V I/O operation Parameter Input leakage current† Output leakage current Input high (logic 1) voltage Sym |ILI| |ILO| VIH VIL VOH VOL Conditions VDD = Max, 0V < VIN < VDD OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ Address and control pins I/O pins Address and control pins I/O pins IOH = –4 mA, VDDQ = 2.375V IOL = 8 mA, VDDQ = 2.625V Min -2 -2 1.7* 1.7* -0.3** -0.3** 1.7 – Max 2 2 VDD+0.3 VDDQ+0.3 0.7 0.7 – 0.7 Unit µA µA V V V V V V Input low (logic 0) voltage Output high voltage Output low voltage † LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA. * VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC **V IL min = -1.5 for pulse width less than 0.2 X tCYC IDD operating conditions and maximum limits Parameter Operating power supply current1 Sym ICC ISB Standby power supply current ISB1 ISB2 Conditions CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax, IOUT = 0 mA, ZZ < VIL All VIN ≤ 0.2V or > VDD – 0.2V, Deselected, f = fMax, ZZ < VIL Deselected, f = 0, ZZ < 0.2V, all VIN ≤ 0.2V or ≥ VDD – 0.2V Deselected, f = fMax, ZZ ≥ VDD – 0.2V, all VIN ≤ VIL or ≥ VIH -200 375 130 30 30 -166 350 100 30 30 -133 325 90 30 30 mA Unit mA 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 1/31/05; v.1.1 Alliance Semiconductor P. 9 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Timing characteristics over operating range –200 Parameter Clock frequency Cycle time Clock access time Output enable LOW to data valid Clock HIGH to output Low Z Data output invalid from clock HIGH Output enable LOW to output Low Z Output enable HIGH to output High Z Clock HIGH to output High Z Output enable HIGH to invalid output Clock HIGH pulse width Clock LOW pulse width Address setup to clock HIGH Data setup to clock HIGH Write setup to clock HIGH Chip select setup to clock HIGH Address hold from clock HIGH Data hold from clock HIGH Write hold from clock HIGH Chip select hold from clock HIGH ADV setup to clock HIGH ADSP setup to clock HIGH ADSC setup to clock HIGH ADV hold from clock HIGH ADSP hold from clock HIGH ADSC hold from clock HIGH 1 See “Notes” on page 16. –166 Min Max 200 – 3.0 3.0 – – – 3.0 3.0 – – – – – – – – – – – – – – – – – –133 Min Max Sym fMax tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tOHOE tCH tCL tAS tDS tWS tCSS tAH tDH tWH tCSH tADVS tADSPS tADSCS tADVH tADSPH tADSCH Min – 5 – – 0 1.5 0 – – 0 2.0 2.3 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 1.4 1.4 1.4 0.4 0.4 0.4 Max Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes1 – 6 – – 0 1.5 0 – – 0 2.4 2.4 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 166 – 3.5 3.5 – – – 3.5 3.5 – – – – – – – – – – – – – – – – – – 7.5 – – 0 1.5 0 – – 0 2.5 2.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 133 – 4.0 4.0 – – – 4.0 4.0 – – – – – – – – – – – – – – – – – 2,3,4 2 2,3,4 2,3,4 2,3,4 5 5 6 6 6,7 6,8 6 6 6,7 6,8 6 6 6 6 6 6 Snooze Mode Electrical Characteristics Description Conditions Symbol Min Max Units Current during Snooze Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current ZZ > VIH ISB2 tPDS tPUS tZZI tRZZI 30 2 2 2 0 mA cycle cycle cycle 1/31/05; v.1.1 Alliance Semiconductor P. 10 of 19 ® AS7C33128PFD32B AS7C33128PFD36B Key to switching waveforms Rising input Falling input don’t care Undefined Timing waveform of read cycle tCH CLK tADSPS ADSP tADSCS ADSC tAS Address A1 tWS GWE, BWE tCSS CE0, CE2 tCSH tWH tAH A2 LOAD NEW ADDRESS A3 tADSCH tADSPH tCYC tCL CE1 tADVS ADV ADV inserts wait states OE tOE tLZOE Dout Q(A1) tADVH tHZOE tCD tOH Q(A2) Q(A2Ý01) Q(A2Ý10) Q(A2Ý11) Q(A3) Q(A3Ý01) tHZC Q(A3Ý10) Read Q(A1) Suspend Read Q(A1) Read Q(A2) Burst Burst Read Suspend Burst Burst Burst Burst Read Read Q(A3) DSEL* Read Read Read Read Read Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11) Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care. *Outputs are disabled within two clk cycles after DSEL command 1/31/05; v.1.1 Alliance Semiconductor P. 11 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Timing waveform of write cycle tCYC tCL tCH CLK tADSPS ADSP tADSPH tADSCS ADSC ADSC LOADS NEW ADDRESS tAS Address A1 tAH A2 A3 tADSCH BW[a:d] BWE tWS tWH tCSS CE0, CE2 tCSH CE1 ADV SUSPENDS BURST ADV tADVS tADVH OE tDS Din Read Q(A1) D(A1) D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) D(A2Ý11) D(A3) D(A3Ý01) tDH D(A3Ý10) Suspend Write D(A1) Read Q(A2) Suspend Write D(A 2) ADV ADV ADV Suspend Burst Burst Burst Write Write Write D(A 2Ý01) Write D(A 2Ý01) D(A 2Ý10) D(A 2Ý11) Write D(A 3) Burst Write D(A 3Ý01) ADV Burst Write D(A 3Ý10) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. 1/31/05; v.1.1 Alliance Semiconductor P. 12 of 19 ® AS7C33128PFD32B AS7C33128PFD36B Timing waveform of read/write cycle (ADSP Controlled; ADSC High) tCH CLK tADSPS ADSP tAS Address A1 A2 tWS GWE tWH tAH A3 tADSPH tCYC tCL CE0, CE2 CE1 tADVS ADV OE tDS tDH Din tCD Dout tLZC tHZOE Q(A1) D(A2) tADVH tOE tLZOE Q(A3) tOH Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) DSEL Read Q(A1) Suspend Read Q(A1) Read Q(A2) Suspend Write D(A 2) Read Q(A3) ADV Burst Read Q(A 3Ý01) ADV Burst Read Q(A 3Ý10) ADV Burst Read Q(A 3Ý11) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. 1/31/05; v.1.1 Alliance Semiconductor P. 13 of 19 ® AS7C33128PFD32B AS7C33128PFD36B Timing waveform of read/write cycle (ADSC controlled, ADSP = HIGH) tCH CLK tADSCS ADSC tADSCH tCYC tCL tAS ADDRESS A1 A2 A3 A4 A5 tWS GWE tCSS CE0,CE2 tCSH A6 tWH A7 A8 tAH A9 CE1 ADV OE tOE tLZOE Dout Q(A1) Q(A2) Q(A3) tHZOE Q(A4) tLZOE Q(A8) tOH Q(A9) tDS Din READ Q(A1) READ Q(A2) READ Q(A3) READ Q(A4) D(A5) D(A6) tDH D(A7) WRITE WRITE WRITE D(A6) D(A7) D(A5) READ Q(A8) READ Q(A9) 1/31/05; v.1.1 Alliance Semiconductor P. 14 of 19 ® AS7C33128PFD32B AS7C33128PFD36B Timing waveform of power down cycle tCH CLK tADSPS ADSP tADSPS tCYC tCL ADSC ADDRESS A1 A2 tWS tWH GWE tCSS CE0,CE2 tCSH CE1 ADV OE tOE Din tLZOE tHZOE tHZC Dout Q(A1) D(A2) D(A2(Ý01)) tPDS ZZ ZZ Setup Cycle tPUS ZZ Recovery Cycle Normal Operation Mode tZZI Isupply tRZZI ISB2 Sleep State READ SUSPEND Q(A1) READ Q(A1) READ SUSPEND CONQ(A2) WRITE TINUE D(A2) WRITE D(A2 Ý01) 1/31/05; v.1.1 Alliance Semiconductor P. 15 of 19 AS7C33128PFD32B AS7C33128PFD36B ® AC test conditions • Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. • Input and output timing reference levels: 1.5V. +3.0V DOUT Z0 = 50Ω 50Ω DOUT VL = 1.5V for 3.3V I/O; 353Ω / 1538Ω 30 pF* = V DDQ/2 for 2.5V I/O Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω / 1667Ω 5 pF* GND *including scope and jig capacitance 90% 10% GND 90% 10% Figure A: Input waveform Figure B: Output load (A) Figure C: Output load (B) Notes 1 For test conditions, see AC Test Conditions, Figures A, B, C. 2 This parameter measured with output load condition in Figure C. 3 This parameter is sampled, but not 100% tested. 4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage. 5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL. 6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. 7 Write refers to GWE, BWE, BW[a:d]. 8 Chip select refers to CE0, CE1, CE2. 1/31/05; v.1.1 Alliance Semiconductor P. 16 of 19 ® AS7C33128PFD32B AS7C33128PFD36B Package Dimensions 100-pin quad flat pack (TQFP) TQFP Min A1 A2 b c D E e Hd He L L1 α 0.05 1.35 0.22 0.09 13.90 19.90 Hd D b Max 0.15 1.45 0.38 0.20 14.10 20.10 e 0.65 nominal 15.85 21.80 0.45 16.15 22.20 0.75 He E 1.00 nominal 0° 7° Dimensions in millimeters α c L1 L A1 A2 1/31/05; v.1.1 Alliance Semiconductor P. 17 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Ordering information Package TQFP TQFP TQFP TQFP Note Add suffix ‘N’ to the above part numbers for lead free parts (Ex. AS7C33128PFD32B-166TQCN) Width x32 x32 x36 x36 –200 AS7C33128PFD32B-200TQC AS7C33128PFD32B-200TQI AS7C33128PFD36B-200TQC AS7C33128PFD36B-200TQI –166 AS7C33128PFD32B-166TQC AS7C33128PFD32B-166TQI AS7C33128PFD36B-166TQC AS7C33128PFD36B-166TQI –133 AS7C33128PFD32B-133TQC AS7C33128PFD32B-133TQI AS7C33128PFD36B-133TQC AS7C33128PFD36B-133TQI Part numbering guide AS7C 1 33 2 128 3 PF 4 D 5 32/36 6 B 7 –XXX 8 TQ 9 C/I 10 X 11 1. Alliance Semiconductor SRAM prefix 2. Operating voltage: 33=3.3V 3. Organization: 128=128K 4. Pipeline mode 5. Deselect: D=Double cycle deselect 6. Organization: 32 = x32; 36 = x36 7. Production version: B= Product revision 8. Clock speed (MHz) 9. Package type: TQ=TQFP 10. Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C) 11. N=Lead Free Part 1/31/05; v.1.1 Alliance Semiconductor P. 18 of 19 ® AS7C33128PFD32B AS7C33128PFD36B ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C33128PFD32B-36B Document Version: v.1.1 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. 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