AS7C34096B-10BIN

AS7C34096B-10TIN AS7C34096B-10BIN Revision History AS7C34096B 512K X 8 BIT HIGH SPEED CMOS SRAM Revision Rev 1.0 Rev 1.1 Details Initial Issue Added 6mm x 8mm TFBGA Package Confidential Date Aug. 2016 Sep. 2017 1／11 Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN GENERAL DESCRIPTION FEATURES The AS7C34096B is a 4,194,304-bit high speed CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature.  Fast access time : 10ns  Low power consumption: Operating current: 40mA(TYP.) Standby current: 2mA(TYP.)  Single 3.3V power supply  All inputs and outputs TTL compatible  Fully static operation  Tri-state output The AS7C34096B operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible  Data retention voltage : 1.5V (MIN.)  Package : 44-pin 400 mil TSOP-II 36-ball 6mm x 8mm TFBGA Table 1. Ordering Information Speed Part Number Temperature Vcc Range Package AS7C34096B-10TIN 10ns Industrial -40°C to +85°C 2.7 ~ 3.6V 44pin TSOPII AS7C34096B-10BIN 10ns Industrial -40°C to +85°C 2.7 ~ 3.6V 36ball FBGA FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION SYMBOL A0 - A18 DQ0 – D7 CE# WE# OE# VCC VSS NC Vcc Vss A0-A18 DECODER 512Kx8 MEMORY ARRAY DQ0-DQ7 I/O DATA CIRCUIT COLUMN I/O CE# WE# OE# CONTROL CIRCUIT Confidential 2／11 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN PIN CONFIGURATION NC 1 44 NC NC 2 43 NC A4 3 42 NC A3 4 41 A5 5 40 A6 6 39 A7 A0 7 38 A8 CE# 8 37 OE# DQ0 9 36 DQ7 DQ1 10 35 DQ6 Vcc 11 34 Vss Vss 12 33 Vcc DQ2 13 32 DQ5 DQ3 14 31 DQ4 WE# 15 A18 16 A17 17 A16 18 A15 19 A14 AS7C34096B-10TIN A2 A1 30 A9 29 A10 28 A11 27 A12 26 A13 20 25 NC NC 21 24 NC NC 22 23 NC TSOP II AS7C34096B-10BIN Confidential 3／11 Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 -40 to 85 -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H L L L OE# X H L X WE# X H H L SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 I/O OPERATION High-Z High-Z DOUT DIN H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. *4 MAX. UNIT Supply Voltage VCC 2.7 3.3 3.6 V Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VIH*1 VIL*2 ILI 2.2 - 0.3 -1 - VCC+0.3 0.8 1 V V µA -1 - 1 µA 2.4 - - 0.4 V V - 50 70 mA - 40 55 mA - - 30 mA - 2 10 mA ILO VOH VOL ICC Average Operating Power Supply Current ICC1 Standby Power Supply Current ISB ISB1 VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, Output Disabled IOH = -4mA IOL = 8mA Cycle time = Min. CE# = VIL, II/O = 0mA, Others at VIL or VIH CE# ≦0.2, Others at 0.2V or Vcc-0.2V II/O = 0mA;f=max CE# =VIH, Others at VIL or VIH CE# ≧VCC - 0.2V, Others at 0.2V or VCC - 0.2V Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ Confidential 4／11 Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 8 10 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Speed Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 10ns 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH AS7C34096B-10 UNIT MIN. MAX. 10 ns 10 ns 10 ns 4.5 ns 2 ns 0 ns 4 ns 4 ns 2 ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* AS7C34096B-10 MIN. MAX. 10 8 8 0 8 0 6 0 2 4 UNIT ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Confidential 5／11 Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Confidential 6／11 Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN WRITE CYCLE 1 (WE# Controlled) (1,2,4,5) tWC Address tAW CE# tCW tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,4,5) tWC Address tAW CE# tAS tWR tCW tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.A write occurs during the overlap of a low CE#, low WE#. 2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Confidential 7／11 Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 1.5V IDR CE# ≧ VCC - 0.2V Others at 0.2V or Vcc – 0.2V See Data Retention tCDR Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 2 10 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM Confidential 8／11 Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ Confidential DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 3o 6o 0o 9／11 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 0o 3o 6o Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN 36 ball 6mm × 8mm TFBGA Package Outline Dimension Confidential 10／11 Rev 1.1 Sep 2017 AS7C34096B-10TIN AS7C34096B-10BIN PART NUMBERING SYSTEM AS7C SRAM 34096B 34096=512k x 8 B=B die 10 10=10ns T/B T = TSOPII B=TFBGA I I=Industrial (-40° C~+85° C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential 11／11 Rev 1.1 Sep 2017