AS7C34098B-10TIN

AS7C34098B Revision History AS7C34098B Revision Rev 1.0 Rev 2.0 Confidential Details Initial Issue Add TFBGA package Date Aug. 2016 June. 2017 - 1 of 14 - Rev.2.0. June 2017 AS7C34098B 256K X 16 BIT HIGH SPEED CMOS SRAM FEATURES GENERAL DESCRIPTION n Fast access time : 10ns n Low power consumption: Operating current: 40mA (TYP.) Standby current: 2mA (TYP.) n Single 3.3V power supply n All inputs and outputs TTL compatible n Fully static operation n Tri-state output n Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) n Data retention voltage : 1.5V (MIN.) n ROHS compliant n Package : 44-pin 400mil TSOP II 48-ball 6mm x 8mm TFBGA The AS7C34098B is a 4,194,304-bit high speed CMOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. Table 1. Ordering Information Part Number Speed The AS7C34098B operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible Temperature Vcc Range Package AS7C34098B-10TIN* 10ns Industrial -40°C to +85°C 2.7 ~ 3.6V 44pin TSOPII AS7C34098B-10BIN* 10ns Industrial -40°C to +85°C 2.7 ~ 3.6V 48-ball TFBGA * : indicates Tray and add TR =Tape Reel packing type Confidential - 2 of 14 - Rev.2.0. June 2017 AS7C34098B FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0-A17 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# WE# OE# LB# UB# DECODER I/O DATA CIRCUIT 256Kx16 MEMORY ARRAY COLUMN I/O SYMBOL DESCRIPTION A0 - A17 Address Inputs DQ0 - DQ15 Data Inputs/Outputs CE# Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground NC No Connection CONTROL CIRCUIT PIN DESCRIPTION Confidential - 3 of 14 - Rev.2.0. June 2017 AS7C34098B PIN CONFIGURATION A0 1 44 A17 A1 2 43 A16 A2 3 42 A15 A3 4 41 OE# 5 40 UB# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 36 DQ13 35 DQ12 34 Vss 33 Vcc 32 DQ11 31 DQ10 30 DQ9 29 DQ8 28 NC 27 A14 AS7C34098B-10TIN XXXXXXXX XXXXXXXX A4 CE# DQ2 9 DQ3 10 Vcc 11 Vss 12 DQ4 13 DQ5 14 DQ6 15 DQ7 16 WE# 17 A5 18 A6 19 A7 20 A8 21 24 A11 A9 22 23 A10 26 A13 25 A12 TSOP II A LB# OE# A0 A1 B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D Vss DQ11 A17 A7 DQ3 Vcc E Vcc DQ12 NC A16 DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC NC A8 NC A12 A13 WE# DQ7 A9 A10 A11 NC 1 2 3 4 5 6 TFBGA(See through with Top View) Confidential AS7C34098B-10BIN XXXXXXXX XXXXXXXX H A2 TFBGA (Top View) - 4 of 14 - Rev.2.0. June 2017 AS7C34098B ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 RATING -0.5 to 4.6 -0.5 to VCC+0.5 UNIT V V TA -40 to 85 ℃ TSTG PD IOUT -65 to 150 1 50 ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# OE# H L L L L L L L L X H X L L L X X X WE# LB# X H X H H H L L L X X H L H L L H L UB# X X H H L L H L L I/O OPERATION DQ0 - DQ7 DQ8 - DQ15 High-Z High-Z High-Z High-Z High-Z High-Z DOUT High-Z High-Z DOUT DOUT DOUT DIN High-Z High-Z DIN DIN DIN SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 H = VIH, L = VIL, X = Don't care Confidential - 5 of 14 - Rev.2.0. June 2017 AS7C34098B DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Voltage VCC Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VIH *2 VIL ILI MIN. *1 ILO VOH VOL ICC Average Operating Power supply Current ICC1 Standby Power Supply Current TEST CONDITION ISB ISB1 VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, Output Disabled IOH = -4mA IOL = 8mA Cycle time = MIN. CE# = VIL, II/O = 0mA, Others at VIL or VIH CE# ≦ 0.2, Others at 0.2V or VCC-0.2V II/O = 0mA; f=MAX. CE# =VIH, Others at VIL or VIH CE# ≧ VCC - 0.2V, Others at 0.2V or VCC - 0.2V TYP. *4 MAX. UNIT 2.7 3.3 3.6 V 2.2 - 0.3 -1 - VCC+0.3 0.8 1 V V µA -1 - 1 µA 2.4 - - 0.4 V V - 50 70 mA - 40 55 mA - - 30 mA - 2 10 mA Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX. 8 10 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Speed Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load Confidential 10ns 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA - 6 of 14 - Rev.2.0. June 2017 AS7C34098B AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* AS7C34098B-10 MIN. MAX. 10 10 10 4.5 2 0 4 4 2 4.5 4 0 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW AS7C34098B-10 MIN. MAX. 10 8 8 0 8 0 6 0 2 4 8 - UNIT ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Confidential - 7 of 14 - Rev.2.0. June 2017 AS7C34098B TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ Confidential - 8 of 14 - Rev.2.0. June 2017 AS7C34098B WRITE CYCLE 1 (WE# Controlled) (1,2,4,5) tWC Address tAW CE# tCW tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout tOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,4,5) tWC Address tAW CE# tAS tWR tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Data Valid Din Confidential tDH - 9 of 14 - Rev.2.0. June 2017 AS7C34098B WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5) tWC Address tAW tWR CE# tAS tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW tDH Data Valid Din Notes : 1.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Confidential - 10 of 14 - Rev.2.0. June 2017 AS7C34098B DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 1.5V, CE# ≧ VCC - 0.2V IDR Others at 0.2V or VCC – 0.2V Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time tCDR MIN. 1.5 See Data Retention Waveforms (below) tR TYP. MAX. UNIT 3.6 V - 2 10 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ≥ 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# Confidential VIH tR CE# ≥ Vcc-0.2V - 11 of 14 - VIH Rev.2.0. June 2017 AS7C34098B PACKAGE OUTLINE DIMENSION 44-pin 400 mil TSOP Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ Confidential DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 0 3 6 - 12 of 14 - DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 Rev.2.0. June 2017 AS7C34098B 48-ball 6mm × 8mm TFBGA Package Outline Dimension Confidential - 13 of 14 - Rev.2.0. June 2017 AS7C34098B ORDERING INFORMATION (Speed/ns) Temperature Range(℃) 44-pin (400mil) TSOP II 10 -40℃~85℃ 48-ball (6mm x 8mm) TFBGA 10 -40℃~85℃ Package Type Access Time Packing Type Tray Tape Reel Tray Tape Reel Alliance Memory Part Number AS7C34098B-10TIN AS7C34098B-10TINTR AS7C34098B-10BIN AS7C34098B-10BINTR Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential - 14 of 14 - Rev.2.0. June 2017