AS7C38096A-10BINTR

FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM FEATURES GENERAL DESCRIPTION  Fast access time : 10ns  Very low power consumption: Operating current: 80mA(TYP. 10ns) Standby current (Normal version): 3mA(TYP.)  Single 3.3V power supply  All inputs and outputs TTL compatible  Fully static operation  Tri-state output  Data retention voltage : 1.5V (MIN.)  Green package available Package: 44-pin 400 mil TSOP-II 48-ball 6mmx8mm TFBGA The AS7C38096A is a 8M-bit high speed CMOS static random access memory organized as 1,024K words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS7C38096A operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed AS7C38096A -40 ~ 85℃ 2.7 ~ 3.6V 10ns 1 Power Dissipation Standby(ISB1,TYP.) Operating(Icc1,TYP.) 3mA 80/70mA FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A19 DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# WE# OE# CONTROL CIRCUIT 1024Kx8 MEMORY ARRAY COLUMN I/O 2 SYMBOL DESCRIPTION A0 - A19 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE# Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM PIN CONFIGURATION 44-pin TSOP(Type II) 48-ball 6mmx8mm TFBGA A NC OE# A0 A1 A2 NC B NC NC A3 A4 CE# NC C DQ0 NC A5 A6 NC DQ4 D Vss DQ1 A17 A7 E Vcc DQ2 NC A16 DQ6 Vss F DQ3 NC A14 A15 G NC NC A12 A13 WE# NC H A18 A8 A9 A10 A11 A19 1 2 3 4 TFBGA 5 6 DQ5 Vcc NC DQ7 3 FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature SYMBOL VT1 VT2 RATING -0.5 to 4.6 -0.5 to VCC+0.5 UNIT V V TA -40 to 85 ℃ TSTG -65 to 150 ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H L L L OE# X H L X WE# X H H L SUPPLY CURRENT ISB1 ICC ICC ICC I/O OPERATION High-Z High-Z DOUT DIN H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC -10 *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled MIN. 2.7 2.2 - 0.3 -1 -1 Output High Voltage VOH IOH = -8mA Output Low Voltage VOL IOL =4mA Icc CE# = VIL , II/O = 0mA ;f=max Average Operating Power supply Current Icc1 Standby Power Supply Current Standby Power Supply Current Isb ISB1 -10 CE# ≧VCC - 0.2V, Other pin is at 0.2V or Vcc-0.2V -10 II/O = 0mA;f=max CE# ≧Vih Other pin is at Vil or Vih CE# ≧VCC - 0.2V; Other pin is at 0.2V or Vcc-0.2V Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4 TYP. 3.3 - *4 MAX. 3.6 VCC+0.3 0.8 1 UNIT V V V µA - 1 µA 2.4 - - V - - 0.4 V - 100 130 mA 80 110 mA 40 mA 25 mA 3 FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 8 10 - Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS speed Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 10ns 0.2V to Vcc-0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH AS7C38096A-10 MIN. 10 2 0 2 MAX. 10 10 4.5 4 4 - UNIT ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER SYM. Data to Write Time Overlap tWC tAW tCW tAS tWP tWR tDW Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z tDH tOW * tWHZ* Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time AS7C38096A-10 UNIT MIN. 10 8 8 0 8 0 MAX. - 6 - ns 0 2 - 4 ns ns ns *These parameters are guaranteed by device characterization, but not production tested. 5 ns ns ns ns ns ns UNIT pF pF FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. 6 High-Z FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 7 FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC =1.5V IDR CE# ≧VCC - 0.2V; Other pin is at 0.2V or Vcc-0.2V See Data Retention tCDR Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 3 25 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ¡Ù 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ¡Ù Vcc-0.2V 8 VIH FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 0 3 6 9 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension 10 FEBRUARY 2012 AS7C38096A 1M X 8 BIT HIGH SPEED CMOS SRAM ORDERING INFORMATION BGA : 48-ball 6 mm x 8 mm TFBGA Industrial -40°C ~ +85°C AS7C38096A-10BIN TSOP II : 44-pin 400 mil TSOP II Industrial -40°C ~ +85°C AS7C38096A-10TIN 11