AS7C38098A-10BIN

FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM FEATURES GENERAL DESCRIPTION  Fast access time : 10ns  low power consumption: Operating current: 80mA (TYP. 10/ns) Standby current: 3mA(TYP)  Single 3.3V power supply  All inputs and outputs TTL compatible  Fully static operation  Tri-state output  Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15)  Data retention voltage : 1.5V (MIN.)  Green package available  Package : 44-pin 400 mil TSOP-II 48-ball 6mmx8mm TFBGA The AS7C38098A is a 8M-bit high speed CMOS static random access memory organized as 512K words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS7C38098A operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed AS7C38098A -40 ~ 85℃ 2.7 ~ 3.6V 10ns 1 Power Dissipation Standby(ISB1,TYP.) Operating(Icc1,TYP.) 3mA 80/70mA FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A18 Address Inputs DQ0 – DQ15 Data Inputs/Outputs 2 CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM PIN CONFIGURATION A LB# OE# A0 A1 B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D Vss DQ11 A17 A7 DQ3 Vcc E Vcc DQ12 NC A16 DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 WE# DQ7 A10 H A18 A8 A9 1 2 3 4 TFBGA A2 NC A11 NC 5 6 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM RATING -0.5 to 4.6 UNIT V TA -40 to 85 ℃ TSTG -65 to 150 ℃ PD IOUT 1 50 W mA TSOLDER 260 ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. 3 FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM TRUTH TABLE MODE CE# OE# H L L L L L L L L X H X L L L X X X Standby Output Disable Read Write Note: WE# LB# X H X H H H L L L X X H L H L L H L UB# X X H H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT DIN High – Z High – Z DIN DIN DIN SUPPLY CURRENT ISB1 ICC ICC ICC H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage SYMBOL TEST CONDITION VCC MIN. -10 *1 TYP. *4 MAX. UNIT 2.7 3.3 3.6 V 2.2 - 0.3 -1 - VCC+0.3 0.8 1 V V µA -1 - 1 µA Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VIH *2 VIL ILI Output High Voltage VOH IOH = -8mA 2.4 - - V Output Low Voltage VOL IOL =4mA - - 0.4 V Icc CE# = VIL , II/O = 0mA ;f=max - 100 130 mA 80 110 mA 40 mA 25 mA ILO Average Operating Power supply Current Icc1 Standby Power Supply Current Standby Power Supply Current Isb ISB1 VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, Output Disabled -10 CE# ≧VCC - 0.2V, Other pin is at 0.2V or Vcc-0.2V -10 II/O = 0mA;f=max CE# ≧Vih Other pin is at Vil or Vih CE# ≧VCC - 0.2V; Other pin is at 0.2V or Vcc-0.2V Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ 4 3 FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 8 10 - Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS speed Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 10ns 0.2V to Vcc-0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* AS7C38098A-10 MIN. 10 2 0 2 0 MAX. 10 10 4.5 4 4 4.5 4 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* tBW AS7C38098A-10 MIN. 10 8 8 0 8 0 6 0 2 8 MAX. 4 - *These parameters are guaranteed by device characterization, but not production tested. 5 UNIT ns ns ns ns ns ns ns ns ns ns ns UNIT pF pF FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. 6 FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid 7 FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tAS tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 8 FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 1.5V CE# ≧VCC - 0.2V; IDR Other pin is at 0.2V or Vcc-0.2V See Data Retention tCDR Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 3 25 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ¡Ù 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ¡Ù Vcc-0.2V 9 VIH FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 0 3 6 10 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension 11 FEBRUARY 2012 AS7C38098A 512K X 16 BIT HIGH SPEED CMOS SRAM ORDERING INFORMATION BGA : 48-ball 6 mm x 8 mm TFBGA Industrial -40°C ~ +85°C AS7C38098A-10BIN TSOP II : 44-pin 400 mil TSOP II Industrial -40°C ~ +85°C AS7C38098A-10TIN 12