AS7C4098A

February 2006 ® AS7C4098A 5.0 V 256 K × 16 CMOS SRAM Features • Pin compatible with AS7C4098 • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 5/6 ns output enable access time • Easy memory expansion with CE, OE inputs • TTL- and CMOS-compatible, three-state I/O • 44-pin JEDEC standard packages • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA - 400-mil SOJ - TSOP 2 • Low power consumption: ACTIVE - 990mW/max @ 10 ns • Low power consumption: STANDBY - 55mW/max CMOS • Individual byte read/write controls Logic block diagram A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 WE VCC 1024 × 256 × 16 Array (4,194,304) GND Pin arrangement for SOJ and TSOP 2 44-pin (400 mil) SOJ TSOP2 A0 A1 A2 A3 A4 CE I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 I/O buffer Row Decoder Control circuit Column decoder A5 A9 A10 A11 A14 A15 A16 A17 UB OE LB CE Selection guide –10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current 10 5 180 10 –12 12 6 160 10 –15 15 6 140 10 –20 20 6 120 10 Unit ns ns mA mA 2/21/06, v 1.2 Alliance Semiconductor P. 1 of 11 Copyright © Alliance Semiconductor. All rights reserved. AS7C4098A ® Functional description The AS7C4098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/ O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16. All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 5.0V (AS7C4098A) supply. The device is available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2 packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min –0.50 –0.50 – –65 –55 – Max +7.0 VCC +0.50 1.5 +150 +125 ±20 Unit V V W °C °C mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L WE X H X OE X H X LB X X H L L H L H L L L L X H L Key: X = Don’t care, L = Low, H = High. UB X X H H L L H L L I/O1–I/O8 High Z High Z DOUT High Z DOUT DIN High Z DIN I/O9–I/O16 High Z High Z High Z DOUT DOUT High Z DIN DIN Write (ICC) Read (ICC) Mode Standby (ISB, ISB1) Output disable (ICC) 2/21/06, v 1.2 Alliance Semiconductor P. 2 of 11 AS7C4098A ® Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature commercial industrial Symbol VCC (10/12/15/20) VIH* VIL** TA TA Min 4.5 2.2 –0.5 0 –40 Typical 5.0 – – – – Max 5.5 VCC + 0.5 0.8 70 85 Unit V V V °C °C * VIH max = VCC + 1.5V for pulse width less than 5 nS. **V min = –1.0V for pulse width less than 5 nS. IL DC operating characteristics (over the operating range)1 –10 Parameter Symbol Input leakage current Output leakage current Operating power supply current Standby power supply current |ILI| Test conditions VCC = Max VIN = GND to VCC VCC = Max CE = VIH or OE = VIH or WE = VIL VI/O = GND to VCC VCC = Max CE < VIL, f = fmax, IOUT = 0 mA VCC = Max CE > VIH, f = Max VCC = Max CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0 IOL = 6 mA, VCC = Min IOL = 8 mA, VCC = Min IOH = –4 mA, VCC = Min –12 –15 –20 Min Max Min Max Min Max Min Max Unit Notes – 1 – 1 – 1 – 1 µA |ILO| – 1 – 1 – 1 – 1 µA ICC ISB ISB1 VOL VOH – – 2.4 180 60 10 0.4 0.5 – – – 2.4 160 55 10 0.4 0.5 – – – 2.4 140 50 10 0.4 0.5 – – – 2.4 120 mA 45 10 0.4 0.5 – mA mA Output voltage V V 4 4 Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)4 Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE, UB, LB I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 6 8 Unit pF pF 2/21/06, v 1.2 Alliance Semiconductor P. 3 of 11 AS7C4098A ® Read cycle (over the operating range)2,8 –10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE Low to output in low Z CE High to output in high Z OE Low to output in low Z OE High to output in high Z LB, UB access time LB, UB Low to output in low Z LB, UB High to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tBA tBLZ tBHZ tPU tPD Min 10 – – – 3 3 – 0 – – 0 – 0 – Max – 10 10 5 – – 5 – 5 5 – 5 – 10 12 – – – 3 3 – 0 – – 0 – 0 – –12 Min Max – 12 12 6 – – 6 – 6 6 – 6 – 12 15 – – – 3 3 – 0 – – 0 – 0 – –15 Min Max – 15 15 6 – – 7 – 7 7 – 7 – 15 20 – – – 3 3 – 0 – – 0 – 0 – –20 Min Max – 20 20 6 – – 9 – 9 8 – 9 – 20 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 4 4 3, 4 3, 4 3, 4 3, 4 Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled)5,6,8 tRC Address tOH DataOUT Previous data valid tAA Data valid tOH 2/21/06, v 1.2 Alliance Semiconductor P. 4 of 11 AS7C4098A ® Read waveform 2 (CE, OE, UB, LB controlled)5,7,8 tRC Address tAA OE tOLZ CE tACE tCLZ LB, UB tBLZ DataOUT tBA Data valid tBHZ tCHZ tOE tOHZ tOH Write cycle (over the operating range)9 –10 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width (OE = High) Write pulse width (OE = Low) Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in High-Z Output active from write end Byte enable Low to write end Symbol Min tWC tCW tAW tAS tWP1 tWP2 tWR tAH tDW tDH tWZ tOW tBW 10 7 7 0 7 10 0 0 5 0 2 3 7 Max – – – – – – – – – – 5 – – 12 8 8 0 8 12 0 0 6 0 2 3 8 – 6 – – –12 Min Max – – – – – – – – Min 15 10 10 0 10 15 0 0 7 0 2 3 10 –15 Max – – – – – – – – – – 7 – – Min 20 12 12 0 12 20 0 0 9 0 2 3 12 –20 Max – – – – – – – – – – 9 – – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 3, 4 3, 4 3, 4 3, 4 Note 2/21/06, v 1.2 Alliance Semiconductor P. 5 of 11 AS7C4098A ® Write waveform 1(WE controlled)9 tWC tAH tWR Address tCW CE tBW LB, UB tAS WE tDW DataIN DataOUT Data undefined tWZ tDH Data valid tOW High Z tAW tWP Write waveform 2 (CE controlled)9 tWC Address tAS CE tCW tAW tBW LB, UB WE DataIN tWP tDW Data valid tDH tAH tWR 2/21/06, v 1.2 Alliance Semiconductor P. 6 of 11 AS7C4098A ® Write waveform 3 9 tWC tAH tWR Address tAS CE tAW tBW LB, UB WE DataIN DataOUT High Z tWZ Data undefined tWP tDW Data valid tDH High Z tCW AC test conditions Output load: see Figure B. Input pulse level: GND to VCC - 0.5V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. 90% 10% 2 ns Figure A: Input pulse 90% 10% DOUT 255Ω +5.0V 480Ω C10 DOUT Thevenin equivalent: 168Ω +1.728V VCC - 0.5V GND GND Figure B:5.0V Output load Notes 1 2 3 4 5 6 7 8 9 10 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. All write cycle timings are referenced from the last valid address to the first transitioning address. C = 30 pF, except on High Z and Low Z parameters, where C = 5 pF. 2/21/06, v 1.2 Alliance Semiconductor P. 7 of 11 AS7C4098A ® Package dimensions 44 434241403938373635343332313029282726252423 c 44-pin TSOP 2 e He 1 2 3 4 5 6 7 8 9 101112131415161718 19202122 d A2 A1 b E l A 0–5° A A1 A2 b c d e He E l 44-pin TSOP 2 Min (mm) Max (mm) 1.2 0.05 0.15 0.95 1.05 0.30 0.45 0.21 0.12 18.31 18.52 10.06 10.26 11.68 11.94 0.80 (typical) 0.40 0.60 e 44-pin SOJ Pin 1 B A1 b D E1E2 c A Seating Plane A2 E A A1 A2 B b c D E E1 E2 e 44-pin SOJ 400 mils Min(mils) Max(mils) 0.128 0.148 0.025 0.105 0.115 0.026 0.032 0.015 0.020 0.007 0.013 1.120 1.130 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM 2/21/06, v 1.2 Alliance Semiconductor P. 8 of 11 AS7C4098A ® Ordering Codes Package SOJ Version 5.0V industrial TSOP 2 5.0V industrial 10 ns AS7C4098A-10JI AS7C4098A-10TI 12 ns AS7C4098A-12JC AS7C4098A-12JI AS7C4098A-12TC AS7C4098A-12TI 15 ns AS7C4098A-15JC AS7C4098A-15JI AS7C4098A-15TC AS7C4098A-15TI 20 ns AS7C4098A-20JC AS7C4098A-20JI AS7C4098A-20TC AS7C4098A-20TI 5.0V commercial AS7C4098A-10JC 5.0V commercial AS7C4098A-10TC Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts. (EX: AS7C4098A - 10TCN) Part numbering system AS7C SRAM prefix 4098A –XX J or T Packages: J: SOJ 400 mil T: TSOP 2 X Temperature ranges: C: Commercial, 0°C to 70°C I: Industrial, –40°C to 85°C X N = Lead Free Parts Device Access number time 2/21/06, v 1.2 Alliance Semiconductor P. 9 of 11 AS7C4098A ® Revision History Rev. No. v1.0 v1.1 v1.2 Initial release Included ICC, ISB & ISB1 parameters Corrected the following: TOE, VIH, VOL & tWZ Removed the title “PRELIMINARY INFORMATION” History Revised Date 11/08/04 05/27/05 02/21/06 2/21/06, v 1.2 Alliance Semiconductor P. 10 of 11 ® AS7C4098A ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C4098A Document Version: v 1.2 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. 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