AS7C513B-12TI

March 2004 AS7C513B ® 5V 32K×16 CMOS SRAM Features • Industrial and commercial temperature • Organization: 32,768 words × 16 bits • Center power and ground pins • High speed • 10/12/15/20 ns address access time • 5, 6, 7, 8 ns output enable access time • Low power consumption: ACTIVE • 605mW / max @ 10 ns • Low power consumption: STANDBY • 55 mW / max CMOS I/O • 6T 0.18u CMOS Technology • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • 44-pin JEDEC standard package • 400 mil SOJ • 400 mil TSOP 2 • ESD protection > 2000 volts • Latch-up current > 200 mA Logic block diagram A0 A2 A3 A4 A5 A6 A7 I/O0–I/O7 I/O8–I/O15 Pin arrangement VCC 44-Pin SOJ, TSOP 2 (400 mil) NC A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A14 A13 A12 A11 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A4 A5 A6 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A7 A8 A9 A10 NC Row decoder A1 32K × 16 Array GND I/O buffer Control circuit Column decoder A8 A9 A10 A12 A13 A14 A11 WE UB OE LB CE Selection guide -10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current -12 12 6 100 10 -15 15 7 90 10 AS7C513B -20 20 8 80 10 Unit ns ns mA mA 10 5 110 10 3/26/04, v.1.3 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. AS7C513B ® Functional description The AS7C513B is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high, the device enters standby mode. If inputs are still toggling, the device consumes ISB power. If the bus is static, then the full standby power is reached (ISB1). The AS7C513B is guaranteed not to exceed 55mW power consumption under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0 - I/O7, and/or I/O8 – I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 – I/O7, and UB controls the higher bits, I/O8 – I/O15. All chip inputs and outputs are TTL-compatible. The AS7C513B is packaged in common industry standard packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied Symbol Vt1 Vt2 PD Tstg Tbias Min –0.50 –0.50 – –65 –55 Max +7.0 VCC +0.50 1.0 +150 +125 Unit V V W oC oC DC current into outputs (low) IOUT – 20 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L L L L L L L WE X H H H L L L H X OE X L L L X X X H X LB X L H L L L H X H UB X H L L L H L X H I/O0–I/O7 High Z DOUT High Z DOUT DIN DIN High Z High Z I/O8–I/O15 High Z High Z DOUT DOUT DIN High Z DIN High Z Mode Standby (ISB, ISBI) Read I/O0–I/O7 (ICC) Read I/O8–I/O15 (ICC) Read I/O0–I/O15 (ICC) Write I/O0–I/O15 (ICC) Write I/O0–I/O7 (ICC) Write I/O8–I/O15 (ICC) Output disable (ICC) Key: X = Don’t care; L = Low; H = High 3/26/04, v.1.3 Alliance Semiconductor P. 2 of 9 AS7C513B ® Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature commercial industrial Symbol VCC VIH VIL TA TA Min 4.5 2.2 –0.5 0 –40 Typical 5 – – – – Max 5.5 VCC + 0.5 0.8 70 85 Unit V V °C °C VIL min = -1.0V for pulse width less than 5ns VIH max = VCC+2.0V for pulse width less than 5ns. DC operating characteristics (over the operating range)1 -10 Parameter Input leakage current Sym | ILI | Test conditions VCC = Max VIN = GND to VCC VCC = Max VOUT = GND to VCC VCC = Max, CE ≤ VIL f = fMax , IOUT = 0mA VCC = Max, CE ≥ VIH f = fMax VCC = Max, CE ≥ VCC - 0.2V VIN ≤ 0.2V or VIN ≥ VCC –0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = –4 mA, VCC = Min Min Max -12 Min Max Min -15 Max Min -20 Max Unit – – – – – – 2.4 1 1 110 50 10 0.4 – – – – – – – 2.4 1 1 100 45 10 0.4 – – – – – – – 2.4 1 1 90 45 10 0.4 – – – – – – – 2.4 1 1 80 40 10 0.4 – µA µA mA mA mA V V Output leakage | ILO | current Operating power supply current ICC ISB Standby power supply current ISB1 VOL VOH Output voltage Capacitance (f = 1MHz, Ta = 25o C, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Symbol CIN CI/O I/O Signals A, CE, WE, OE, LB, UB Test conditions Vin = 0V Vin = Vout = 0V Max 5 7 Unit pF pF Read cycle (over the operating range) 3,9 -10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change -12 Max – 10 10 5 – Min 12 – – – 3 Max – 12 12 6 – Min 15 – – – 3 -15 Max – 15 15 7 – Min 20 – – – 3 -20 Max – 20 20 8 – Unit ns ns ns ns ns 5 3 3 Notes Symbol tRC tAA tACE tOE tOH Min 10 – – – 3 3/26/04, v.1.3 Alliance Semiconductor P. 3 of 9 AS7C513B ® -10 Parameter CE low to output in low Z CE high to output in high Z OE low to output in low Z Byte select access time Byte select Low to low Z Byte select High to high Z OE high to output in high Z Power up time Power down time -12 Max – 4 – 5 – 5 4 – 10 Min 3 – 0 – 0 – – 0 – Max – 5 – 6 – 6 5 – 12 Min 3 – 0 – 0 – – 0 – -15 Max – 6 – 7 – 6 6 – 15 Min 3 – 0 – 0 – – 0 -20 Max – 7 – 8 – 7 7 – 20 Unit ns ns ns ns ns ns ns ns ns 4,5 4,5 4,5 4,5 4,5 Notes 4,5 4,5 4,5 Symbol tCLZ tCHZ tOLZ tBA tBLZ tBHZ tOHZ tPU tPD Min 3 – 0 – 0 – – 0 – Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tOH tAA Data valid tOH Data OUT Previous data valid Read waveform 2 (CE, OE, UB, LB controlled)3,6,8,9 tRC Address tAA OE tOE tOLZ CE tACE tLZ LB, UB tBA tBLZ Data OUT Data valid tBHZ tOHZ tHZ tOH 3/26/04, v.1.3 Alliance Semiconductor P. 4 of 9 AS7C513B ® Write cycle (over the operating range)11 -10 -12 Min Max Min -15 Max Min -20 Max Unit Notes Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Byte select low to end of write Symbol Min Max tWC tCW tAW tAS tWP tWR tAH tDW tDH tWZ tOW tBW 10 8 8 0 7 0 0 5 0 – 1 7 – – – – – – – – – 5 – – 12 9 9 0 8 0 0 6 0 – 1 8 – – – – – – – – – 6 – – 15 10 10 0 9 0 0 8 0 – 1 9 – – – – – – – – – 7 – – 20 12 12 0 12 0 0 10 0 – 2 9 – – – – – – – – – 8 – – ns ns ns ns ns ns ns ns ns ns ns ns 5 4,5 4,5 Write waveform 1(WE controlled)11 tWC Address tBW LB, UB tAS WE tDW Data IN tWZ Data OUT Data undefined Data valid tOW High-Z tDH tAW tWP tWR 3/26/04, v.1.3 Alliance Semiconductor P. 5 of 9 AS7C513B ® Write waveform 2 (CE controlled)11 tWC Address tAS CE tCW tAW tBW LB, UB tWP WE tDW Data IN tCLZ Data OUT High-Z tWZ Data undefined High-Z Data valid tOW tDH tAH & tWR AC test conditions Output load: see Figure B. Input pulse level: GND to 3.5V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent: 168Ω Dout +1.728V +5.0V 480Ω +3.5V GND 90% 10% 2 ns 90% 10% Dout 255Ω C13 Figure A: Input pulse GND Figure B: 5.0V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5pF, as in Figure B. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C=30pF, except on High Z and Low Z parameters, where C=5pF. 3/26/04, v.1.3 Alliance Semiconductor P. 6 of 9 AS7C513B ® Package dimensions 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 c 44-pin TSOP 2 Symbol A Min (mm) 0.05 0.95 0.3 0.12 18.31 10.06 11.68 Max (mm) 1.2 0.15 1.05 0.45 0.21 18.52 10.26 11.94 44-pin TSOP 2 e He A1 A2 b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 c d e d l 0–5° A1 b E A A2 He E l 0.80 (typical) 0.40 0.60 44-pin SOJ 44-pin SOJ 400 mil Symbol Min 0.128 0.025 0.105 0.026 0.015 0.007 1.120 Max 0.148 0.115 0.032 0.020 0.013 1.130 e D A A1 E1 E2 A2 B Pin 1 B A1 b Seating Plane A A2 E c b c D E E1 E2 e 0.370 NOM 0.395 0.435 0.405 0.445 0.050 NOM 3/26/04, v.1.3 Alliance Semiconductor P. 7 of 9 AS7C513B ® Ordering codes Package\Access time Plastic SOJ, 400 mil TSOP 2, 18.4×10.2 mm 10 ns AS7C513B-10JC AS7C513B-10JI AS7C513B-10TC AS7C513B-10TI 12 ns AS7C513B-12JC AS7C513B-12JI AS7C513B-12TC AS7C513B-12TI 15 ns AS7C513B-15JC AS7C513B-15JI AS7C513B-15TC AS7C513B-15TI 20 ns AS7C513B-20JC AS7C513B-20JI AS7C513B-20TC AS7C513B-20TI Commercial Industrial Commercial Industrial Part numbering system AS7C SRAM prefix 513B Device number –XX Package: Access time X J = SOJ 400 mil T =TSOP 2 18.4×10.2 mm C Temperature range: C = Commercial, 0°C to 70°C I = Industrial, -40°C to 85°C 3/26/04, v.1.3 Alliance Semiconductor P. 8 of 9 ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C513B Document Version: v.1.3 © Copyright 2003 Alliance Semiconductor Corporation. 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