128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Description
Features
◆
◆
◆
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AS8C403625
AS8C401825
TheAS8C403625/1825 are high-speed SRAMs organized as
128K x 36/256K x 18. The AS8C403625/1825 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the
end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the AS8C403625/1825 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The AS8C403625/1825 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP)
128K x 36, 256K x 18 memory configurations
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP),
Pin Description Summary
A0-A17
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS 0, CS1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
VSS
Ground
Supply
N/A
NOTE:
1. BW3 and BW4 are not applicable for the AS8C401825.
5280 tbl 01
1
.
SEPTEMBER 2010
DSC-5280/08
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Synchronous Addre ss Status from Cache Controller. ADSC is an active LOW input that is used to load the
address registers with new addresses.
ADSP
Address Status
(Processor)
I
LOW
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
ADV
Burst Address
Advance
I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,
controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not
incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte
write causes all outputs to be disabled.
CE
Chip Enable
I
LOW
Synchronous chip enable. CE is used with CS 0 and CS1 to enable AS8C403625/1825. CE also gates ADSP.
CLK
Clock
I
N/A
This is the clock input. All timing references for the device are made with respect to this input.
CS 0
Chip Select 0
I
HIGH
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
CS1
Chip Select 1
I
LOW
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
Enable
I
LOW
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Synchronous data inp ut/output (I/O) pins. The data input path is registered, triggered by the rising edge of
CLK. The data output path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected.
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
TMS
Test ModeSelect
I
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK
Test Clock
I
N/A
Clock input of TAP co ntroller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TDO
Test DataOutput
O
N/A
Serial output of registers placed be tween TDI and TDO. This output is active depending on the state of the
TAP controller.
TRST
JTAG Reset
(Optional)
I
LOW
Optional Asynchronous JTAG rese t. Can be used to reset the TAP contro ller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
ZZ
Sleep Mode
I
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down theAS8C403625/1825
to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull
down.
VDD
Power Supply
N/A
N/A
3.3V core power supply.
VDDQ
Power Supply
N/A
N/A
3.3V I/O Supply.
VSS
Ground
N/A
N/A
Ground.
NC
No Connect
N/A
N/A
NC pins are not electrically connected to the device.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
5280 tbl 02
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Functional Block Diagram
LBO
ADV
CLK
2
Binary
Counter
ADSC
CLK EN
ADDRESS
REGISTER
A0 - A16/17
GW
BWE
Burst
Logic
Q0
CLR
ADSP
INTERNAL
ADDRESS
Burst
Sequence
CEN
Q1
2
A0,A1
17/18
A0*
A1*
A2 - A17
36/18
17/18
Byte 1
Write Register
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
9
Byte 3
Write Register
Byte 3
Write Driver
BW3
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
9
CE
CS0
CS1
D
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
Powerdown
OE
OE
I/O0 - I/O31
I/OP1 - I/OP4
36/18
Byte 1
Write Driver
BW1
ZZ
128K x 36/
256K x 18BIT
MEMORY
ARRAY
OUTPUT
BUFFER
36/18
TMS
TDI
TCK
TRST
(Optional)
5280 drw 01
JTAG
(SA Version)
TDO
6.42AA
3
,
AS8C403625, AS8C401825 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Absolute Maximum Ratings(1)
Symbol
(2)
Rating
Commercial &
Industrial Values
Unit
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
VTERM(4,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
V
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
V
Commercial
Operating Temperature
-0 to +70
o
Industrial
Operating Temperature
-40 to +85
o
C
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-55 to +125
PT
Power Dissipation
2.0
W
IOUT
DC Output Current
50
mA
TA
(7)
TBIAS
Recommended Operating
Temperature Supply Voltage
VSS
VDD
V DDQ
Commercial
0°C to +70°C
0V
3.3V±5%
3.3V±5%
Industrial
-40°C to +85°C
0V
3.3V±5%
3.3V±5%
C
Symbol
C
Input Capacitance
CI/O
I/O Capacitance
Input Capacitance
CI/O
I/O Capacitance
Unit
Core Supply Voltage
3.135
3.3
3.465
V
VDDQ
I/O Supply Voltage
3.135
3.3
3.465
V
0
0
0
V
2.0
____
VDD +0.3
2.0
____
-0.3(2)
____
Supply Voltage
Input High Voltage - Inputs
VIH
Input High Voltage - I/O
VIL
Input Low Voltage
Parameter(1)
Conditions
Max.
Unit
Symbol
VIN = 3dV
5
pF
CIN
Input Capacitance
VOUT = 3dV
7
pF
CI/O
I/O Capacitance
(TA = +25° C, f = 1.0mhz)
CIN
Max.
V
(1)
VDDQ +0.3
0.8
V
V
(TA = +25° C, f = 1.0mhz)
165 fBGA Capacitance
Parameter(1)
Typ.
5280 tbl 06
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
5280 tbl 07
Symbol
Min.
119 BGA Capacitance
(TA = +25° C, f = 1.0mhz)
CIN
Parameter
VDD
VSS
100 Pin TQFP Capacitance
(1)
5280 tbl 04
Recommended DC Operating
Conditions
5280 tbl 03
Parameter
Temperature(1)
NOTES:
1. TA is the "instant on" case temperature.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Symbol
Grade
VIH
o
Commercial Temperature Range
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
pF
5280 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
pF
5280 tbl 07a
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ran
A6
A7
CE
CS0
BW4
BW3
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration – 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VSS(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
51
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ (2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
5280 drw 02a
,
ges
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ra nges
A6
A7
CE
CS0
NC
NC
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration – 256K x 18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
80
2
79
3
78
77
4
5
6
76
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
66
15
16
65
64
17
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A11
A12
A13
A14
A15
A16
A17
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VSS(1)
VDD
NC
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
1
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL .
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
51
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
VDD
ZZ(2)
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
5280 drw 02b
,
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
5
µA
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to V DD
___
|ILI|
ZZ , LBO and JTAG Input Leakage Current(1)
VDD = Max., VIN = 0V to V DD
___
30
µA
VOUT = 0V to V DDQ , Device Deselected
___
5
µA
IOL = +8mA, VDD = Min.
___
0.4
V
2.4
___
|ILO|
Output Leakage Current
Output Low Voltage
VOL
Output High Voltage
VOH
IOH = -8mA, VDD = Min.
V
5280 tbl 08
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ in will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1)
7.5ns
Symbol
Parameter
Test Conditions
8ns
8.5ns
Com'l Only
Com'l
Ind
Com'l
Ind
Unit
IDD
Operating Power Supply Current
Device Se lected, Outputs Open, V DD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
255
200
210
180
190
mA
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
30
30
35
30
35
mA
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = fMAX (2,.3)
90
85
95
80
90
mA
IZZ
Full Sleep Mode Supply Current
ZZ > VHD, VDD = Max.
30
30
35
30
35
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
AC Test Load
(VDDQ = 3.3V)
Input Pulse Levels
2ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
AC Test Load
VDDQ/2
50Ω
0 to 3V
Input Rise/Fall Times
mA
5280 tbl 09
I/O
,
Z0 = 50Ω
5280 drw 03
Figure 1. AC Test Load
6
See Figure 1
5
5280 tbl 10
4
∆tCD 3
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
Figure 2. Lumped Capacitive Load, Typical Derating
7
200
5280 drw 05
,
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Synchronous Truth Table (1,3)
Address
Used
CE
CS0
CS1
ADSP
ADSC
ADV
GW
BWE
BWx
OE(2)
CLK
I/O
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
X
H
L
X
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
L
X
L
X
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
X
H
X
L
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
L
X
X
L
X
X
X
X
X
↑
HI-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
H
↑
HI-Z
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
H
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
H
↑
HI-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L
X
↑
DIN
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
X
X
↑
DIN
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
H
↑
HI-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
H
↑
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
H
↑
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
H
↑
HI-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
X
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
X
X
↑
DIN
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
H
↑
HI-Z
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
H
↑
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
H
↑
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
H
↑
HI-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
X
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
X
X
↑
DIN
Operation
5280 tbl 11
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ - low for the table.
88
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Synchronous Write Function Truth Table (1, 2)
Operation
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
(3)
H
L
L
H
H
H
(3)
H
L
H
L
H
H
(3)
H
L
H
H
L
H
(3)
H
L
H
H
H
L
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
5280 tbl 12
NOTES:
1. L = VIL, H = V IH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the AS8C401825.
3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table (1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z – Data In
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
5280 tbl 13
NOTES:
1. L = VIL, H = V IH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table ( LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
1
0
0
1
0
0
5280 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table ( LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
0
0
0
1
1
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
99
5280 tbl 15
AS8C403625,AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
8ns
7.5ns(5)
Symbol
Parameter
8.5ns
Min.
Max.
Min.
Max.
Min.
Max.
Unit
8.5
____
10
____
11.5
____
ns
Clock Parameter
tCYC
Clock Cycle Time
tCH(1)
Clock High Pulse Width
3
____
4
____
4.5
____
ns
tCL(1)
Clock Low Pulse Width
3
____
4
____
4.5
____
ns
____
7.5
____
8
____
8.5
ns
2
____
2
____
ns
0
____
0
____
ns
Output Parameters
tCD
Clock High to Valid Data
tCDC
Clock High to Data Change
2
____
tCLZ(2)
Clock High to Output Active
0
____
tCHZ(2)
Clock High to Data High-Z
2
tOE
Output Enable Access Time
tOLZ(2)
Output Enable Low to Output Active
tOHZ(2)
Outp ut Enable High to Output High-Z
3.5
2
3.5
2
3.5
ns
____
3.5
____
3.5
____
3.5
ns
0
____
0
____
0
____
ns
____
3.5
____
3.5
____
3.5
ns
1.5
____
2
____
2
____
ns
2
____
2
____
ns
Set Up Times
tSA
Address Setup Time
tSS
Address Status Setup Time
1.5
____
tSD
Data In Setup Time
1.5
____
2
____
2
____
ns
tSW
Write Setup Time
1.5
____
2
____
2
____
ns
2
____
2
____
ns
tSAV
Address Advance Setup Time
1.5
____
tSC
Chip Enable/Select Setup Time
1.5
____
2
____
2
____
ns
Hold Times
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tHS
Address Status Hold Time
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.5
____
tHW
Write Hold Time
0.5
____
0.5
____
0.5
____
ns
tHAV
Address Advance Hold Time
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
Sleep Mode and Configuration Parameters
tZZPW
ZZ Pulse Width
100
____
100
____
100
____
ns
tZZR(3)
ZZ Recovery Time
100
____
100
____
100
____
ns
tCFG (4)
Configuration Set-up Time
34
____
40
____
50
____
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
6.42
10
ns
5280 tbl 16
6.42
13
Output
Disabled
tSC
tSA
tSS
tHS
tOLZ
tOE
O1(Ax)
tHC
tHA
Flow-through
Read
Ax
tOHZ
Ay
(1)
tCH
tCD
tSAV
tHAV
O1(Ay)
tCDC
tSW
tCL
O3(Ay)
O4(Ay)
(Burst wraps around
to its initial state)
ADV HIGH suspends burst
Burst Flow-through Read
O2(Ay)
tHW
O1(Ay)
tCHZ
O2(Ay)
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
OE
ADV
(Note 3)
CE, CS1
GW, BWE, BWx
ADDRESS
ADSC
ADSP
CLK
tCYC
5280 drw 06
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ran
Timing Waveform of Flow-Through Read Cycle (1,2)
,
ges
6.42
14
Ax
(2)
Single Read
tSA
tHA
tSS
tHS
tCLZ
tCD
tOE
O1(Ax)
tOHZ
tSW
Ay
tCH
Write
I1(Ay)
tSD tHD
tCL
tHW
Az
tCD
tOLZ
O2(Az)
O3(Az)
Flow-through Burst Read
O1(Az)
tCDC
5280 drw 07
O4(Az)
,
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
DATAOUT
DATAIN
OE
ADV
GW
ADDRESS
ADSP
CLK
tCYC
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ra nges
Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3)
6.42
15
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tHC
Ax
O4(Aw)
(1)
Ay
tCL
tOHZ
I1(Ax)
I1(Ay)
I2(Ay)
(ADV suspends burst)
tSAV
GW is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge
tCH
I2(Ay)
(2)
I3(Ay)
tHAV
I4(Ay)
tSD
I1(Az)
tHW
tSW
Az
I2(Az)
tHD
5280 drw 08
I3(Az)
Timing Waveform of Write Cycle No. 1 - GW Controlled
,
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the
LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
O3(Aw)
tSC
tSA
tHA
tSS
tHS
tCYC
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ran
ges
(1,2,3)
6.42
16
tHC
Burst
Read
O3(Aw)
tSC
tSA
tHA
tSS
tHS
O4(Aw)
Ax
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
Burst Write
I2(Ay)
(ADV HIGH suspends burst)
I2(Ay)
BWx is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge
BWE is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge
tCH
I3(Ay)
I4(Ay)
tSD
Extended
Burst Write
I1(Az)
tSAV
tHW
tSW
tHW
tSW
Az
I2(Az)
tHD
5280 drw 09
I3(Az)
Timing Waveform of Write Cycle No. 2 - Byte Controlled
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the
LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
BWx
BWE
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ra nges
(1,2,3)
6.42
17
tSS
tSC
tSA
tHS
tOLZ
tOE
Ax
Single Read
O1(Ax)
tHC
tHA
tCH
tCL
tZZPW
Snooze Mode
tZZR
NOTES:
1. Device must power up in deselected Mode.
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signaals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ZZ
DATAOUT
OE
ADV
(Note 4)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
Az
5280 drw 13
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ran
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
,
ges
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW, BWE, BWx
CE, CS1
CS0
OE
(Av)
DATAOUT
(Aw)
(Ax)
(Ay)
5280 drw 10
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
,
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
(Ax)
(Ay)
(Az)
GW
CE, CS1
CS0
DATAIN
(Av)
(Aw)
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
16
5280 drw 11
,
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
JTAG Interface Specification (SA Version only)
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
x
TRST(3)
M5280 drw 01
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
5(1)
ns
tJF
JTAG Clock Fall Time
____
5(1)
ns
tJRST
JTAG Reset
50
____
ns
tJ RSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
20
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
25
____
ns
25
____
ns
tJH
JTAG Hold
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
Note (1)
I5280 tbl 03
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
I5280 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
17717172
17
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Value
Revision Number (31:28)
Device ID (27:12)
Description
0x2
Reserved for version number.
0x22C, 0x22E
Defines AS8C403625/1825
JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Allows unique identification of device vendor .
1
Indicates the presence of an ID register.
I5280 tbl 02
Available JTAG Instructions
Instruction
Description
OPCODE
EXTEST
Forces contents of the boundary scan cells onto the device outputs(1) .
Places the boundary scan register (BSR) between TDI and TDO.
0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
0001
DEVICE_ID
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
0010
HIGHZ
Places the bypass register (BYR) between TDI and TDO. Forces all
device o utput drivers to a High-Z state.
0011
RESERVED
RESERVED
RESERVED
0100
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
RESERVED
CLAMP
0101
0110
0111
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the byp ass registe r (BYR) between TDI and TDO.
RESERVED
1000
1001
RESERVED
1010
Same as above.
RESERVED
1011
RESERVED
1100
VALIDATE
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mand ated by the IEEE std. 1149.1 specification.
1101
RESERVED
Same as above.
1110
BYPASS
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
1111
I5280 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
2 18
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
ORDERING INFORMATION
VCC
Range
Package
Operating Temp
128K x 36
3.1 - 3.4V
100 pin TQFP
Comercial 0 - 70C
7.5
256K x 18
3.1 - 3.4V
100 pin TQFP
Comercial 0 - 70C
7.5
Alliance
Organization
AS8C403625-QC75N
AS8C401825-QC75N
Speed
ns
PART NUMBERING SYSTEM
Device
AS8C
Sync.
SRAM prefix
40 = 4M
Conf.
18= x18
36 = x36
Mode
Package
01= ZBT
00 = Pipelined
25 = Flow- Thru
Q = 100 Pin TQFP
Operating Temp
0 ~ 70C
N
Speed
7.5 ns
N= Leadfree
ORDERING INFORMATION
Alliance
VCC
Range
Organization
AS6C8016A -55ZIN
512K x 16
AS6C8016A -55BIN
Package
2.7 - 5.5V
512K x 16
2.7 - 5.5V
Speed
ns
Operating Temp
44pin TSOP II
Industrial ~ -40 C - 85 C
55
48ball FBGA
Industrial ~ -40 C - 85 C
55
PART NUMBERING SYSTEM
AS6C
8016
-55
Device Number
low power
SRAM prefix
®
Alliance Memory, Inc.
551 Taylor way, suite#1,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS8C403625/401825
Document Version: v. 1.0
www.alliancememory.com
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any
product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or
warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's
Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in
life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all
claims arising from such use.
192 19
80 = 8M
16 = x16
Access
Time
X
X
Package Option
Temperature Range
Z - 44pin TSOP
I = Industrial
B = 48ball TFBGA
(-40 to + 85 C)
N
N = Lead Free
RoHS
compliant part
