AS8C801825-QC75N

256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect AS8C803625 AS8C801825 Features         256K x 36, 512K x 18 memory configuration Supports fast access times: - 7.5ns up to 117MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP) Description The 803625/801825 are high-speed SRAMs organized as 256K x 36/512K x 18. The 803625/801825 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flowthrough architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the 803625/801825 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The orders of these three addresses are defined by the internal burst counter and the LBO input pin. The 803625/801825 SRAMs utilize Alliance’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP). Pin Description Summary A0 – A18 CE CS0, CS1 OE GW BWE BW1, BW2, BW3, BW4(1) CLK ADV ADSC ADSP LBO ZZ I/O0 – I/O31, I/OP1 – I/OP4 VDD, VDDQ VSS Address Inputs Chip Enable Chip Selects Output Enable Global Write Enable Byte Write Enable Individual Byte Write Selects Clock Burst Address Advance Address Status (Cache Controller) Address Status (Processor) Linear / Interleaved Burst Order Sleep Mode Data Input / Output Core Power, I/O Power Ground NOTE: 1. BW3 and BW4 are not applicable for 803625/801825. Input Input Input Input Input Input Input Input Input Input Input Input Input I/O Supply Supply Synchronous Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Synchronous Synchronous DC Asynchronous Synchronous N/A N/A 5309 tbl 01 NOVEMBER 2010 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 3 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 4 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 5 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 6 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 7 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 8 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 9 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 10 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 11 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 12 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 13 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 14 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 15 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 16 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 17 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 18 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 19 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 20 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 21 AS8C803625, AS8C801825, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Alliance Part numbering system Alliance Memory 7 = FAST Async 6 = Low Power 8 = SSRAM C = CMOS SRAM Voltage: Blank = 5V CMOS, 3 = 3.3V CMOS Device number assigned by Alliance Memory A suffix denotes die revision Access time in nanoseconds/megaherz Packages: J = SOJ 400 mil TJ = SOJ 300 mil T = TSOP ST = shrink TSOP (sTSOP) QC = 100pin TQFP S = SOP P = DIP B = TFBGA Z = TSOP II Temperature Ranges: C = Commercial 0ºC to 70ºC I = Industrial -40º to 85ºC N = ROHS compliant lead free part Tape and Reel AS 7 C 3 4098 A -12 J C N Ordering Information Alliance AS8C803625 AS8C801825 Organization 256K x 36 512K x 18 VCC Range Operating Temp 3.1 - 3.4V Comercial 0 - 70C 3.1 - 3.4V Comercial 0 - 70C 22 Speed 7.5 ns 7.5 ns TR