AS9C25256M2018L-200FC

September 2004 Preliminary Information ® AS9C25512M2018L AS9C25256M2018L 2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface Features • True Dual-Port memory cells that allow simultaneous access of the same memory location • Organisation: 524,288/262,144 × 18[1] • Fully Synchronous, independent operation on both ports • Selectable Pipeline or Flow-Through output mode • Fast clock speeds in Pipeline output mode: 250 MHz operation (9Gbps bandwidth) • Fast clock to data access: 2.8ns for Pipeline output mode • Asynchronous output enable control • Fast OE access times: 2.8ns • Double Cycle Deselect (DCD) for Pipeline Output Mode • 19/18[1]-bit counter with Increment, Hold and Repeat features on each port Note: 1. AS9C25512M2018L/AS9C25256M2018L • • • • • • • • Dual Chip enables on both ports for easy depth expansion Interrupt and Collision Detection Features 2.5 V power supply for the core LVTTL compatible, selectable 3.3V or 2.5V power supply for I/Os, addresses, clock and control signals on each port Snooze modes for each port for standby operation 15mA typical standby current in power down mode Available in 256-pin Ball Grid Array (BGA), 144-pin Thin Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array (fpBGA) Supports JTAG features compliant with IEEE 1149.1 Selection guide Feature Minimum cycle time Maximum Pipeline clock frequency Maximum Pipeline clock access time Maximum flow-through clock frequency Maximum flow-through clock access time Maximum operating current Maximum snooze mode current -250 4 250 2.8 150 6.5 TBD 18 -200 5 200 3.4 133 7.5 350 18 -166 6 166 3.6 100 10 300 18 -133 7.5 133 4.2 83 12 260 18 Units ns MHz ns MHz ns mA mA 9/24/04; v.1.2 Alliance Semiconductor P. 1 of 30 Copyright © Alliance Semiconductor. All rights reserved. AS9C25512M2018L AS9C25256M2018L ® Dual port logic block diagram R/W Control R/W Control BE1A-BE0A CE0A CE1A R/WA REGISTER BANK D Q REGISTER BANK D Q REGISTER BANK Q D REGISTER BANK Q D BE1B-BE0B CE0B CE1B R/WB O/P Control O/P Control O/P Control O/P Control 1 1 0 PL/FT 0 PL/FT PL/FTA OEA PL/FT QoutA QoutB PL/FT PL/FTB OEB REGISTER BANK Q D REGISTER BANK 1 True Dual Port Memory Array 512/256K X 18 D Q REGISTER BANK REGISTER BANK DQ17A-DQ0A D Q DinA DinB Q D RPTA ADSA INCA A18[1]A-A0A Address Decoding Increment Logic Mirror Register REGISTER BANK D Q Address Decoding REGISTER BANK Q D Address Counter A CE0A OPTA CLKA CE1A R/WA PL/FTA CLKA OPTA INTA COLA CE0B Address Counter B Interrupt/Collision Detection Logic/Registers CE1B R/WB PL/FTB CLKB OPTB INTB COLB OPTB CLKB ZZA Snooze Logic Snooze Logic ZZB TDI TDO TCK JTAG TMS TRST Note: 1. Address A18 is a NC for AS9C25256M2018L 9/24/04, v.1.2 Alliance Semiconductor 0 1 DQ17B-DQ0B RPTB ADSB INCB 0 Increment Logic Mirror Register A18[1]B-A0B P. 2 of 30 AS9C25512M2018L AS9C25256M2018L ® General Description The AS9C25512M2018L/AS9C25256M2018L is a high-speed CMOS 9/4.5-Mbit synchronous Dual-Port Static Random Access Memory device, organized as 524,288/262,144 × 18 bits. It incorporates a selectable Flow-Through/Pipeline output feature for user flexibility. Clockto-data valid time is 2.8ns at 250 MHz for “Pipeline output” mode of operation. Each port contains a 19/18 bit linear burst counter on the input address register that can loop through the whole address sequence. After externally loading the counter with the initial address, it can be Incremented or Held for the next cycle. A new address can also be Loaded or the “Previous Loaded” address can be re-accessed (Repeated) using counter controls (More description to follow). The Registers on control, data, and address inputs provide minimal setup and hold times. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. A particular port can write to a certain location while another port is reading from the same location, but the validity of read data is not guaranteed. However, the reading port is informed about the possible collision through its collision alert signal. The result of writing to the same location by more than one port at the same time is undefined. The Asynchronous Output Enable input pin allows asynchronous disabling of output buffers at any given time. The Byte Enable inputs allow individual byte read/write operations (refer Byte Control Truth Table). An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. AS9C25512M2018L/AS9C25256M2018L can support an operating voltage of either 3.3V or 2.5V on either or both ports, which is controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. This device is available in 256-pin Ball Grid Array (BGA), 208-pin fine pitch Ball Grid Array (fpBGA) and 144-pin Thin Quad Flatpack (TQFP) Address Counter The AS9C25512M2018L/AS9C25256M2018L carries an internal 19/18 bit address counter for each port which can loop through the entire memory array. The Address counter features are discussed below: Load: Any required external address can be loaded on to the counter. This feature is similar to normal address load in conventional memories. Increment: The address counter has the capability to internally increment the address value, potentially covering the entire memory array. Once the whole address space is completed, the counter will wrap around. The address counter is not initailized on Power-up, hence a known location has to be loaded before Increment operation. Hold: The value of the counter register can be held for an unlimited number of clock cycles by de-asserting ADS, INC, and RPT inputs. Repeat: The previously loaded address (loaded using a valid Load operation) can be re-accessed by asserting RPT input. A separate 19/18 bit register called “Mirror register” is used to hold the last loaded address.This register is not initialized on Power-up, hence a known location has to be loaded before Repeat operation (Refer Counter control truth table for details). 9/24/04, v.1.2 Alliance Semiconductor P. 3 of 30 AS9C25512M2018L AS9C25256M2018L ® Ball Assignment - 256-ball BGA AS9C25512M2018L/AS9C25256M2018L B - 256 Top view 1 A NC 2 TDI 3 NC 4 A17A A18[1]A A16A 5 A14A A15A A13A 6 A11A A12A A10A 7 A8A A9A A7A 8 NC 9 CE1A CE0A BE0A 10 OEA R/WA CLKA 11 INCA RPTA ADSA 12 A5A A4A A6A 13 A2A A1A A3A VDD 14 A0A VDD 15 NC 16 NC A B INTA COLA NC NC TDO BE1A NC NC NC B C DQ9A DQ9B VSS OPTA NC NC DQ8A DQ8B DQ7B DQ6A NC C D NC PL/FTA VDDQA VDDQA VDDQB VDDQB VDDQA VDDQA VDDQB VDDQB VDDQA VDD VDD NC VSS VSS VSS VDD VDD NC D E DQ10B DQ10A DQ11A NC NC NC VDDQB NC DQ7A NC E F DQ11B VDDQA DQ12A VDDQB NC VDDQB VDD NC NC VSS VSS VSS VSS VDD VDDQB DQ6B VDDQA DQ5A VDDQA NC F G NC VSS VSS VSS VSS VSS VSS VSS VSS NC G H NC DQ12B VSS VSS VSS VSS VSS VSS VSS VSS NC DQ5B DQ4A DQ3A DQ2B NC H J DQ13A DQ14B DQ13B VDDQA NC NC DQ14A VDDQA DQ15B VDDQB NC VDDQB ZZB VSS VSS VSS VSS VSS VSS VSS ZZA VSS VDDQB DQ4B VDDQB NC DQ3B NC J K VSS VSS VSS VSS VSS VSS K L DQ15A NC VDD NC NC VSS VSS VSS VSS VDD VDDQA DQ2A VDDQA DQ1B VDD NC NC L M DQ16B DQ16A NC DQ17B DQ17A NC VDD VDD NC VSS VSS VSS VDD VDD DQ1A DQ0B NC M N NC PL/FTB VDDQB VDDQB VDDQA VDDQA VDDQB VDDQB VDDQA VDDQA A16B A18[1]B A17B A13B A15B A14B A10B A12B A11B A7B A9B A8B NC BE0B CE0B CE1B CLKB R/WB OEB ADSB RPTB INCB A6B A4B A5B NC N P COLB INTB NC TMS A3B A1B A2B NC DQ0A NC P R TRST BE1B NC OPTB A0B NC R T TCK NC NC NC T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: 1. Address A18 is a NC for AS9C25256M2018L 9/24/04, v.1.2 Alliance Semiconductor P. 4 of 30 AS9C25512M2018L AS9C25256M2018L ® Ball Assignment - 208-ball fpBGA 1 A DQ9A NC 2 INTA VSS 3 VSS 4 TDO 5 NC 6 A16A A13A 7 A12A A9A A10A A7A 8 A8A NC 9 NC 10 VDD 11 CLKA ADSA R/WA RPTA 12 INCA A5A A6A A3A 13 A4A A1A A2A VDD 14 A0A NC 15 OPTA 16 NC 17 VSS A B COLA TDI A17A CE0A CE1A VDD VSS VDDQB DQ8A DQ8B NC NC B C VDDQA DQ9B VDDQB PL/FTA A18[1] A14A A NC VSS DQ10A NC A15A A11A BE1A BE0A VSS VDD VSS C D OEA NC VDDQA DQ7A NC VSS DQ7B NC D E DQ11A NC VDDQB DQ10B NC VSS DQ6A VSS E F VDDQA DQ11B NC VSS DQ6B NC VDDQB NC F G DQ12A NC NC VDDQA DQ5A NC VSS G H VDD NC VDDQB DQ12B VSS ZZB VSS VDD DQ5B VDDQB VSS H J VDDQA VDD DQ14B NC VSS K DQ13B AS9C25512M2018L/AS9C25256M2018L F - 208 Top view ZZA VDD VSS J DQ3B VDDQA DQ4B NC DQ3A NC VSS K L DQ14A VDDQB DQ13A NC DQ15B NC VSS DQ4A L M VDDQA NC VSS DQ2B VDDQB NC DQ2A NC M N VSS DQ15A TRST A16B A13B A12B A9B A10B A7B A8B NC NC VDD CLKB ADSB R/WB RPTB INCB A5B A6B A3B A4B A1B A2B A0B DQ1B VDDQA NC DQ1A N P DQ16B DQ16A VDDQB COLB VSS NC DQ17B TCK VSS P R A17B CE0B CE1B VDD VSS NC VDDQA DQ0B VDDQB NC VSS NC R T NC DQ17A VDDQA TMS INTB PL/FTB NC A18[1]B A14B A15B A11B BE1B BE0B VSS VSS T U VSS OEB VDD OPTB NC DQ0A U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Note: 1. Address A18 is a NC for AS9C25256M2018L 9/24/04, v.1.2 Alliance Semiconductor P. 5 of 30 AS9C25512M2018L AS9C25256M2018L ® Pin Assignment - 144-pin TQFP VSS VDDQB VSS DQ9A DQ9B DQ10A DQ10B DQ11A DQ11B VDDQA VSS DQ12A DQ12B VDDQB ZZB VDD VDD VSS VSS VDDQA VSS DQ13B DQ13A DQ14B DQ14A VDDQB VSS DQ15B DQ15A DQ16B DQ16A DQ17B DQ17A VSS VDDQA NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PL/FTA NC NC A18[1]A A17A A16A A15A A14A A13A A12A A11A A10A A9A A8A A7A BE1A BE0A CE1A CE0A VDD VSS CLKA OEA R/WA ADSA INCA RPTA A6A A5A A4A A3A A2A A1A A0A VDD NC AS9C25512M2018L/AS9C25256M2018L T - 144 Top view OPTA VDDQB VSS DQ8A DQ8B DQ7A DQ7B DQ6A DQ6B VSS VDDQA DQ5A DQ5B VSS VDDQB VDD VDD VSS VSS ZZA VDDQA DQ4B DQ4A DQ3B DQ3A VSS VDDQB DQ2B DQ2A DQ1B DQ1A DQ0B DQ0A VSS VDDQA OPTB Note: 1. Address A18 is a NC for AS9C25256M2018L 9/24/04, v.1.2 PL/FTB NC NC [1] A18 B A17B A16B A15B A14B A13B A12B A11B A10B A9B A8B A7B BE1B BE0B CE1B CE0B VDD VSS CLKB OEB R/WB ADSB INCB RPTB A6B A5B A4B A3B A2B A1B A0B VDD NC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Alliance Semiconductor P. 6 of 30 AS9C25512M2018L AS9C25256M2018L ® Signal description Signal Port A CLKA Port B CLKB I/O Properties Description Notes 1 6 A0A - A18A A0B - A18B DQ0A - DQ17A DQ0B - DQ17B CE0A, CE1A R/WA BE0A - BE1A ADSA INCA RPTA OEA ZZA PL/FTA CE0B, CE1B R/WB BE0B - BE1B ADSB INCB RPTB OEB ZZB PL/FTB OPTA INTA COLA VDDQA VDD VSS TCK TDI TDO TMS TRST OPTB INTB COLB VDDQB Clock. Each port has an independent Clock input that can be of different frequencies. All I CLOCK inputs except OEx and ZZx are synchronous to the corresponding port’s clock and must meet setup and hold time about the rising edge of the clock. I SYNC External Address. Sampled on the rising edge of corresponding port clock I/O SYNC Bidirectional data pins Chip enable inputs. Active low and high, respectively. Sampled on the rising edge of I SYNC corresponding port clock. I SYNC Read/Write enable. Drive this pin LOW to write to, or HIGH to Read from the memory array. Byte Enable Inputs. Active low. Asserting these signals enables Read and Write operations to I SYNC the corresponding bytes of the memory array. (Refer Byte Control Truth Table) Address Strobe Enable.Active low. Loads external address onto the counter. (Refer Counter I SYNC Control Truth Table) Address Counter Increment. Active low. Increments the counter value. (Refer Counter Control I SYNC Truth Table) Address Counter Repeat. Active low. Reloads the counter with the previously loaded external I SYNC address.(Refer Counter Control Truth Table) Asynchronous output enable. I/O pins are driven when the OE is low and the chip is in Read I ASYNC mode. A high on OE tristates the I/O pins. Snooze Mode Input. Places the device in low power mode. Data is retained. This pin has an I ASYNC internal pull-down and can be floating. Pipeline/Flow-Through Select. When low, enables single register flow-through mode. When I STATIC high, enables double register Pipeline mode. This pin has an internal pull-up and can be left floating to operate in pipeline mode. VDDQx Option. OPTx selects the operating voltage levels for the I/Os, addresses, clock, and I STATIC controls on that port. This pin has an internal pull-up and can be left floating to operate in 3.3V mode. Interrupt Flag. Used for message passing between two ports. (Refer Interrupt Logic Truth O SYNC Table) Collision Alert Flag. Used to indicate collision during simultaneous memory access to the O SYNC same location by both the ports (Refer Collision Detection Truth Table) I POWER Power to I/O bus. Can be 3.3V or 2.5V depending on OPTx input. I POWER Power Inputs (To be connected to 2.5V Power supply) I GROUND Ground Inputs (To be connected to Ground supply) CLOCK I JTAG Test Clock Input. All JTAG signals except TRST are synchronous to this clock. (JTAG) SYNC JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. I (JTAG) SYNC JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally O (JTAG) tristated except when the captured data is shifted out of the JTAG TAP. SYNC JTAG Test Mode Select Input. It controls the JTAG TAP state machine. State machine I (JTAG) transitions occur on the rising edge of TCK. ASYNC JTAG Test Reset Input. Asynchronous input used to initialize TAP controller. I (JTAG) 1,2,3 5 5 1,2,3 2 4,5 4,5 5 4,5 4,5 Notes: 1. Subscript 'x' represents 'A' for Port A and 'B' for Port B. 2. OPTx,VDDQx and VDD must be set to appropriate operating levels before applying inputs on the I/Os and controls for that port. 3. OPTx = VDD (2.5V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 3.3V level and VDDQx must be supplied at 3.3V. OPTx = VSS (0V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 2.5V level and VDDQx must be supplied at 2.5V. Each port can independently operate on either of the VDDQ levels. 4. If unused JTAG inputs may be left unconnected. 5. JTAG, Collision Detection & Interrupt features are not supported in TQFP package. 6. Address A18 is a NC for AS9C25256M2018L. 9/24/04, v.1.2 Alliance Semiconductor P. 7 of 30 AS9C25512M2018L AS9C25256M2018L ® Byte control truth table[1,2,3,4,5] BE1 H H L BE0 H L H CLK L to H L to H L to H Read or Write Byte 0 Read or Write Byte 1 Mode All Bytes Deselected - NOP Notes: 1. L = low, H = high 2. CE0 = L, CE1 = H (Chip in Select mode) 3. R/W = H for a Read operation, R/W = L for a Write operation 4. Byte 1 - DQ[17:9], Byte 0 - DQ[8:0] 5. More than one byte enable may be simultaneously asserted Read/write control truth table[1,4] CE[2] H L L L R/W X X L H BEn[3] X H L L CLK L to H L to H L to H L to H Operation Chip Deselect Byte Deselect Byte Write Byte Read DQn[0:8][3,7] Hi-Z[5,9] Hi-Z[5,9] Din[6] Qout[5,8] Notes: 1. L = low, H = high, X = don't care 2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H) 3. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DQn refers to the corresponding Byte 4. Snooze de-asserted (ZZ=L) 5. True in flow-through mode. For Pipeline mode there will be a 1 cycle latency [refer timing diagrams] 6. For a write command issued before the completion of a read command, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. All DQs are tristated on power-up 8. OE should be asserted (OE = L) (Refer Read timing waveform) 9. In pipeline mode the DQs are HighZ-ed in the same cycle if R/W=L Counter control truth table[1,2,5,6] CLK L to H L to H L to H L to H ADS[3] L H H X INC[3] X L H X RPT[3] H H H L External Address An X X X Previous Address Accessed X An An X Mirror Register Content[4] An Am Am Am Address Accessed An An + 1 An Am Load Hold Repeat Operation [4] Increment Notes: 1. L = low, H = high, X = don't care 2. Cycle can be Read, Write or Deselect (Controlled by appropriate setting of R/W, CE0, CE1 and BEn) 3. ADS, INC, RPT are independent of all other memory controls including R/W, CE0,CE1 and BEn (i.e Counter works independent of R/W, CE0,CE1 and BEn) 4. The 'Mirror register' used for the Repeat operation is loaded with External address during every valid ADS access. “Am” refers to the mirror register content. 5. Clock to the counter is disabled during Snooze mode (True for both ports). 6. The counter and the mirror registers are not initialized on Power-up (refer Counter description). 9/24/04, v.1.2 Alliance Semiconductor P. 8 of 30 AS9C25512M2018L AS9C25256M2018L ® Package Thermal Resistance Description Conditions BGA Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 fpBGA TQFP Symbol θJA θJA θJA θJC Typical TBD TBD TBD TBD Units °C/W °C/W °C/W °C/W Thermal Resistance (junction to ambient)[1] Thermal Resistance (junction to top of case)[1] Notes: 1. This parameter is sampled. Capacitance[1] (TA = +25 °C, F = 1.0 Mhz)[2] Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CI/O Signals Address and Control pins I/O pins Test Condition[3] VIN = L to H or H to L VI/O = L to H or H to L BGA (Max) TBD TBD TBD fpBGA (Max) TBD TBD TBD TQFP (Max) TBD TBD TBD Unit pF pF pF Flag Output pins VOUT = L to H or H to L Notes: 1. Sampled, not 100% tested 2. TA stands for 'Ambient temperature'. 3. L = 0V; H = 3V Absolute maximum ratings[1] Rating Parameter Core supply voltage relative to VSS I/O supply voltage relative to VSS Input and I/O voltage relative to VSS Power Dissipation Short circuit output current Storage Temperature Storage Temperature under Bias Junction Temperature Symbol VDD VDDQ VIN PD IOUT TSTG TBIAS TJN Min -0.5 -0.3 -0.3 -65 -55 Max 3.6 3.9 VDDQ + 0.3 TBD TBD 150 125 TBD Unit V V V W mA °C °C °C Notes: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating for extended periods may affect reliability. 9/24/04, v.1.2 Alliance Semiconductor P. 9 of 30 AS9C25512M2018L AS9C25256M2018L ® Recommended operating Temperature Grade Commercial Industrial Ambient Temperature (TA) 0°C to 70°C -40°C to 85°C Recommended operating conditions Parameter Core Supply Voltage I/O supply Voltage Ground Symbol VDD VDDQ VSS Min 2.4 2.4 0 VDDQ = 2.5V[1] Typ 2.5 2.5 0 Max 2.6 2.6 0 Min 2.4 3.15 0 VDDQ = 3.3V[2] Typ 2.5 3.3 0 Max 2.6 3.45 0 Unit V V V Notes: 1. OPT pin for a given port must be set to VSS(0V) to operate at VDDQ = 2.5V levels on the I/Os, addresses, clock and controls of that port. 2. OPT pin for a given port must be set to VDD(2.5V) to operate at VDDQ = 3.3V levels on the I/Os, addresses, clock and controls of that port. DC Electrical Characteristics (VDD = 2.5 V ± 100 mV) VDDQ = 2.5V Parameter Input Leakage Current PL/FT and ZZ Input Leakage Current Output Leakage Current[1] Input high (logic 1) voltage (Address, Control, Clock & Data Inputs) Input high voltage (ZZ,OPT,PL/FT) Input low (logic 0) voltage (Address, Control, Clock & Data Inputs) Input low voltage (ZZ,OPT,PL/FT) Output low voltage Output high voltage Symbol |ILI| |ILI| |ILO| Test Conditions VDDQ = Max; 0V < VIN < VDDQ VDD = Max; 0V < VIN < VDD OE>=VIH; 0V < VOUT < VDDQ Min Max 2 2 2 Test Conditions VDDQ = Max; 0V < VIN < VDDQ VDD = Max; 0V < VIN < VDD OE>=VIH; 0V < VOUT < VDDQ VDDQ = 3.3V Min Max 2 2 2 Units µA µA µA VIH 1.7 VDDQ + 0.1V 2 VDDQ + 0.15V V VIH - VDD - 0.2V VDD + 0.1V - VDD - 0.2V VDD + 0.1V V VIL - -0.3 0.7 - -0.3 0.8 V VIL VOL VOH IOL = +2mA; VDDQ = Min IOH = -2mA; VDDQ = Min -0.3 2.0 0.2 0.4 - IOL = +4mA; VDDQ = Min IOH = -4mA; VDDQ = Min -0.3 2.4 0.2 0.4 - V V V Notes: 1. Outputs disabled (High-Z condition). 9/24/04, v.1.2 Alliance Semiconductor P. 10 of 30 AS9C25512M2018L AS9C25256M2018L ® IDD operating conditions and maximum limits[4] (VDD = 2.5 V ± 100 mV) Parameter Operating current (Both ports active) Pipeline mode -(PL/FT > VIH) Operating current (Both ports active) Flow-through mode (PL/FT < VIL) Standby current (Both ports) Both ports disabled (CEA = CEB = H), ISB1 ZZA = ZZB < VIL, f=fMax ISB2 [1] TBD TBD TBD 105 TBD 90 TBD 80 Symbol Test Conditions -250 -200 -166 -133 Units Typ Max Typ Max Typ Max Typ Max Both ports enabled (CEA = CEB = L[3]), ICC Outputs disabled (IOUT = 0mA), ZZA = ZZB < VIL, f=fMax[1] TBD TBD TBD 350 TBD 300 TBD 260 mA TBD TBD TBD TBD TBD TBD TBD TBD mA mA Standby current (One port) One port enabled (CEA = L and CEB = H)[5], Active port's outputs disabled, ZZA = ZZB < VIL, f=fMax ISB3 [1] TBD TBD TBD 265 TBD 225 TBD 190 mA Full standby current (Both ports) Both ports disabled (CEA = CEB = H), ZZA = ZZB < VIL, f=0 [2] 20 25 20 25 20 25 20 25 mA Full standby current (One port) Snooze mode current Notes: ISB4 One port in Snooze (ZZA > VIH, ZZB < VIL, and CEB = L)[5], Active port's outputs disabled, f=fMax[1] Both ports in Snooze (ZZA = ZZB > VIH), f=fMax[1] TBD TBD TBD 265 TBD 225 TBD 190 mA IZZ 15 18 15 18 15 18 15 18 mA 1. f=fMax implies address and controls (except OE) are cycling at maximum clock frequency using AC test conditions (Refer AC test conditions). 2. f = 0 implies address and controls are static. Corresponding current numbers indicated are true for both CMOS (VIN > VDDQ - 0.2V or VIN < 0.2V) and TTL (VIN > VIH or VIN < VIL) level inputs. 3. CEA and CEB are internal signals (CEx = L implies CE0x < VIL and CE1x > VIH, CEx = H implies CE0x > VIH or CE1x < VIL). 4. Subscript 'x' represents 'A' for Port A and 'B' for Port B. 5. “A” and “B” are interchangeable. 9/24/04, v.1.2 Alliance Semiconductor P. 11 of 30 AS9C25512M2018L AS9C25256M2018L ® AC timing characteristics[1,2,5,6] (VDD = 2.5 ± 100mV) Parameter Symbol -250 Min. Max. 4 1.7 1.7 6.5 1.7 1.7 -200 Min. Max. 5 2 2 7.5 2 2 -166 Min. Max. 6 2.4 2.4 10 2.4 2.4 -133 Min. Max. 7.5 3 3 12 3 3 Unit Notes Clock Cycle Time (Pipeline) Clock High Pulse Width (Pipeline) Clock Low Pulse Width (Pipeline) Cycle Time (Flow-Through) Clock High Pulse Width (Flow-Through) Clock Low Pulse Width (Flow-Through) Output Clock access time (Pipeline) Output Data Hold from Clock High (Pipeline) Clock High to Output Low-Z (Pipeline) Clock High to Output High-Z (Pipeline) Clock access time (Flow-Through) Output Data Hold from Clock High (Flow-Through) Clock High to Output Low-Z (Flow-Through) Clock High to Output High-Z (Flow-Through) Output Enable to Data Valid Output Enable Low to Output Low-Z Output Enable High to Output High-Z Setup Address Setup to Clock High Chip Enable Setup to Clock High Byte Enable Setup to Clock High R/W Setup to Clock High Input Data Setup to Clock High ADS Setup to Clock High INC Setup to Clock High RPT Setup to Clock High Hold Address Hold from Clock High Chip Enable Hold from Clock High Byte Enable Hold from Clock High R/W Hold from Clock High Input Data Hold from Clock High ADS Hold from Clock High INC Hold from Clock High RPT Hold from Clock High Flag Interrupt Flag Set Time Interrupt Flag Reset Time Collision Flag Set Time Collision Flag Reset Time Port-to-Port Delay Clock-to-Clock Delay tCYCP tCHP tCLP tCYCF tCHF tCLF tCDP tOHP tLZCP tHZCP tCDF tOHF tLZCF tHZCF tOE tLZOE tHZOE tAS tCES tBS tWS tDS tADSS tINCS tRPTS tAH tCEH tBH tWH tDH tADSH tINCH tRPTH tSINT tRINT tSCOL tRCOL tCCO 2.8 3.4 3.6 4.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 3 3 3 3 3 3,8 3,8 3 3,8 3,8 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 2.8 6.5 3.4 7.5 3.6 10 4.2 12 1 1 1 1 1 1 1 1 1 1 1 1 2.8 2.8 3.4 3.4 3.6 3.6 4.2 4.2 1 1 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 1 1 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1 1 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1 1 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 2.8 3.4 3.6 4.2 6 6 2.8 2.8 6 6 3.4 3.4 6 6 3.6 3.6 7 7 4.2 4.2 3.0 3.5 4 5 - - - - 7 Notes: 1. All timings are same for both ports. 2. These values are valid for either level of VDDQ (2.5V/3.3V) 3. A particular port will operate in Pipeline output mode if PL/FT = VDD and in flow-through output mode if PL/FT = 0V. Each port can independently operate in any of these modes. 4. Output Enable (OE) is an asynchronous input. 5. PL/FT and OPT should be treated as DC signals and should reach steady state before normal operation. 6. Refer AC Test Conditions to view the test conditions used for these measurements. 7. This parameter has to be taken care to avoid collision during simultaneous memory access of the same location. 8. To avoid bus contention, at a given voltage and temperature tLZC is more than tHZC (True in both Pipeline and flow-through output mode). 9/24/04, v.1.2 Alliance Semiconductor P. 12 of 30 AS9C25512M2018L AS9C25256M2018L ® Timing waveform of read cycle[7] tCYC[2] tCL Don’t care Undefined tCH CLK tCES tCEH CE[3] tBS tBH BEn[4] R/W tAS tAH ADDRESS[5] tWH tWS A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A1 OE[6] [Pipeline Mode] tLZOE tOHP DATA OUT[1] [Pipeline Mode] tHZCP Q2 tHZOE Q6 tLZCP tOE Q8 Q10 Q1 Q1 tLZOE tCDP tLZOE OE[6] [Flow-through Mode] tLZCF DATA OUT[1] [Flow-through Mode] tOHF Q1 Q1 tHZCF Q2 tHZOE Q6 tOE Q8 Q10 Q12 tLZOE tCDF Read (A1) Read (A2) Dsel Read[8] (A4) Dsel Read (A6) Read (A7) Read (A8) Dsel Read (A10) Dsel Read (A12) Notes: 1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low, and in Pipeline mode if PL/FT is driven high or left unconnected. 2. Parameters tCYC, tCH and tCL are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics). 3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H). Timings indicated for CE hold good for CE0 and CE1 4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte. 5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H). 6. OE is an asynchronous input. 7. All timings are similar for both ports. 8. Read with Byte disabled. Data is not read out.Bus in High-Z condition. 9/24/04, v.1.2 Alliance Semiconductor P. 13 of 30 AS9C25512M2018L AS9C25256M2018L ® Timing wave form read/write cycle[7] tCH CLK tCES tCEH tBS tBH BEn[4] tCYC[2] tCL Don’t care Undefined CE[3] R/W tAS tAH [5] ADDRESS A1 A2 A3 A3 A4 tWH tWS A5 A6 A7 A8 A9 A10 A11 A12 OE[6] [Pipeline Mode] [1] DATA IN [Pipeline Mode] tDS tDH D3 D6 D8 tCDP Q1 tHZCP tHZOE Q9 [1] DATA OUT [Pipeline Mode] tLZCP OE[6] [Flow-through Mode] [1] DATA IN [Flow-through Mode] D3 D6 D11 tCDF Q1 tOHF Q2 tHZCF Q4 tHZOE Q7 Q9 [1] DATA OUT [Flow-through Mode] tDS tDH tLZCF Read (A1) Read (A2) Write[8] Write (A3) Read (A4) Read (A5) Write (A6) Read (A7) Write[9] (A8) Read (A9) Dsel Write[9] (A11) Notes: 1. Both Flow-through and Pipeline Inputs/Outputs indicated.A particular port is configured in Flow-through mode if PL/FT for that port is driven low, and in Pipeline mode if PL/FT is driven high or left unconnected. 2. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline modes of operation.(Refer AC Timing characteristics) 3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H). Timings indicated for CE hold good for CE0 and CE1 4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte. 5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H). 6. OE is an asynchronous input. 7. All timings are similar for both ports. 8. Invalid write. Memory Content of the selected location may get corrupted and should be re-written before future readback. 9. Write (A11) is invalid in Pipeline mode and Write (A8) is invalid in Flow-through mode. Memory Content of the selected location may get corrupted and should be re-written before future readback. 9/24/04, v.1.2 Alliance Semiconductor P. 14 of 30 AS9C25512M2018L AS9C25256M2018L ® Timing waveform of address counter[6] tCH CLK tCES tCEH CE[3] tCYC[2] tCL Don’t care Undefined [4] R/W tAS tAH ADDRESS tWH tWS A2 A1 INTERNAL ADDRESS A1 A1+1 A1+2 A1+2 A1 A1+1 A1+2 A1+2 A2 A2+1 A2+1 A2 tADSS tADSH ADS tINCS tINCH INC tRPTS tRPTH RPT tDS tDH D1 DATA IN D1+1 D1+2 D1+2 tCDP DATA OUT[1] [Pipeline Mode] tOHP [5] Q1 Q1+1 tHZCP Q4 Q3 Q1+2 Q4 tCDF DATA OUT[1] [Flow-through Mode] tLZCP Q1 tOHF Q1+1 tHZCF [5] Q1+2 Write Load (A1) Write Incr Write Incr Write Hold tLZCF Read Rept Read Incr Read Incr Read Hold Dsel Load (A2) Dsel Incr Dsel Hold Dsel Rept Notes: 1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low, and in Pipeline mode if PL/FT is driven high or left unconnected. 2. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics). 3. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H). Timings indicated for CE hold good for CE0 and CE1. 4. These cycles indicate that Counter works independent of all memory controls including R/W,CE and BEn. 5. If a Hold operation is performed for a Read access, the Data-out is held valid for the subsequent clock cycle also. 6. All timings are similar for both ports. 9/24/04, v.1.2 Alliance Semiconductor P. 15 of 30 AS9C25512M2018L AS9C25256M2018L ® Mailbox Interrupts The AS9C25512M2018L/AS9C25256M2018L has an Inbuilt Mailbox Logic that can be used for communication between the two ports. One memory location is assigned as mail box (message center) for each port. The location 7FFFE (HEX) is assigned as the message center for Port A and 7FFFF (HEX) for Port B (3FFFE and 3FFFF for AS9C25256M2018L). The port A interrupt flag (INTA) is asserted when the port B writes to memory location 7FFFE (HEX) (3FFFE for AS9C25256M2018L). The port A clears the interrupt flag by reading the address location 7FFFE (HEX) (3FFFE for AS9C25256M2018L). Likewise, the port B interrupt flag (INTB) is asserted when the port A writes to memory location 7FFFF (HEX) (3FFFF for AS9C25256M2018L) and to clear the interrupt flag (INTB), the port B must read the memory location 7FFFF (3FFFF for AS9C25256M2018L).(Refer Interrupt Logic Truth Table). The interrupt flag is asserted in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flowthrough mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without de-asserting the interrupt and each port can write to its own mailbox without asserting the interrupt. If an application does not require message passing, INT pins can be ignored. Interrupt logic truth table[1,4,5] CLKA R/WA CEA[2] A18A-A0A[3,6] CLKB R/WB CEB[2] A18B-A0B[3,6] INTA INTB Function Assert Port B Interrupt Flag De-assert Port B Interrupt Flag Assert Port A Interrupt Flag De-assert Port A Interrupt Flag L to H L to H L to H L to H L X X H L X X L 7FFFF X X 7FFFE L to H L to H L to H L to H X H L X X L L X X 7FFFF 7FFFE X X X L H L H X X Notes: 1. L = low, H = high, X = don't care 2. CEx is an internal signal ('x' = 'A' or 'B'). CEx = H implies 'Chip is Deselected' (CE0x = H or CE1x =L), CEx = L implies 'Chip is Selected' (CE0x = L and CE1x =H) 3. Address specified here is the internal address (refer Counter control truth table). 4. Both Interrupt Flags are De-asserted on power-up. 5. Interrupt feature is not supported in TQFP package. 6. Address A18 is a NC for AS9C25256M2018L, hence Interrupt addresses are 3FFFF and 3FFFE 9/24/04, v.1.2 Alliance Semiconductor P. 16 of 30 AS9C25512M2018L AS9C25256M2018L ® Interrupt timing wave form[2] tCYC[1] CLKA Don’t care tWS tWH R/WA[2] tCH[1] tCL[1] ADDRESSA[3] [4] 7FFFF 7FFFF Aa Aa tAS tAH Aa [5] Aa 7FFFE Aa tSINT INTA tRINT tCYC[1] CLKB tWS tCH[1] tWH R/WB[2] tCL[1] [5] ADDRESSB[3] Ab Ab 7FFFF [4] 7FFFE 7FFFE Ab tAS tAH Ab Ab tSINT INTB tRINT Notes: 1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics). 2. Chip Selected (CE0 = L and CE1 =H). True for both ports. 3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle. 4. 7FFFF (3FFFF for AS9C25256M2018L) is the Mailbox for port B and 7FFFE (3FFFE for AS9C25256M2018L) is the Mailbox for port A. 5. “Aa” and “Ab” refer to any other valid address other than 7FFFF or 7FFFE (3FFFF or 3FFFE for AS9C25256M2018L). 9/24/04, v.1.2 Alliance Semiconductor P. 17 of 30 AS9C25512M2018L AS9C25256M2018L ® Collision detection Three different cases of collisions can be listed depending on the type of access from two ports: Simultaneous Read: A true dual-ported memory cell allows data to be read simultaneously from both ports of the device. Hence no data is corrupted, lost, or incorrectly output, and none of the collision alert flags is asserted. Simultaneous Write: When both ports are writing simultaneously to the same location, both write operations would fail. Therefore, the collision flag is asserted on both ports. Simultaneous Read and Write: When one port is writing and the other port is reading from the same location in the memory, the data written will be valid. However, the read operation would fail and hence the reading port's collision flag is asserted. The alert flag (COLx) is asserted on the 3rd (for both pipe-lined and flow-through output mode) rising clock edge of the affected port following the collision, and remains low for one cycle. On continuous collisions (one or both ports writing during each access), the collision alert flag will be asserted and de-asserted every alternate cycle. Collision detection truth table[1,2,4,5] CLKA R/WA CLKB R/WB Port address[3] COLA COLB Function L to H L to H L to H L to H L to H H H L L L L to H L to H L to H L to H L to H H L H L H MATCH MATCH MATCH MATCH NO MATCH H L H L H H H L L H Both ports reading. Not a valid collision. No collision flag asserted on either port. Port A reading, Port B writing. Valid collision. Collision flag asserted on port A. Port B reading, Port A writing. Valid collision. Collision flag asserted on port B. Both ports writing. Valid collision. Collision flag asserted on both ports. No match. No collision flag asserted on either port. Notes: 1. L = low, H = high, X = don't care 2. Chip Selected (CE0 = L and CE1 =H). True for both ports. Collision flag is not affected if any one or both ports are deselected. 3. “MATCH” indicates that internal addresses of both the ports are the same (refer Counter control truth table). 4. Both Collision Flags are De-asserted on power-up. 5. Collision detection feature is not supported in TQFP package. 9/24/04, v.1.2 Alliance Semiconductor P. 18 of 30 AS9C25512M2018L AS9C25256M2018L ® Collision timing waveform[2] tCYC[1] CLKA tCCO R/WA tAS tAH Aa Aa Am Aa Am Am Am Am Aa Don’t care [5] tCH[1] tCL[1] tWS tWH [4] ADDRESSA[3] Am Aa Am tSCOL COLA tRCOL tCYC[1] CLKB tWS tWH R/WB tAS tAH ADDRESSB[3] tCH[1] tCL[1] [4] Am Ab Ab Am Ab Am Am Am Am Ab Am Ab tSCOL COLB tRCOL Notes: 1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics). 2. Chip Selected (CE0 = L and CE1 =H). True for both ports. 3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle. 4. “Am” refers to matched address. “Aa” and “Ab” refer to any other valid address. 5. During address collision the data validity is guaranteed only if tCCO is greater than the minimum specified (Refer AC timing characteristics). 9/24/04, v.1.2 Alliance Semiconductor P. 19 of 30 AS9C25512M2018L AS9C25256M2018L ® Depth and Width expansion AS9C25512M2018L/AS9C25256M2018L has two chipselects (one active high and other active low) for simple depth expansion. This permits easy upgrade from 512/256K depth to 1M/512K depth without extra logic. Two such parts can also be combined to obtain an expanded width of 36 bits or wider. Data Address DQ A[2] DQ DQ DQ A[1] A[1] A[1] A[1] DQ Microprocessor Clock A[3] A[1] DQ A[3] A[1] CE0 CE1 CE0 CE1 Clock CLK Controller R/W BE OE ADS INC RPT 512/256Kx18 DPSRAM CLK BANK 1 R/W BE OE ADS INC RPT 512/256Kx18 DPSRAM BANK 0 Notes: 1. A for AS9C25512M2018L, A for AS9C25256M2018L 2. A for AS9C25512M2018L, A for AS9C25256M2018L 3. A for AS9C25512M2018L, A for AS9C25256M2018L Timing waveform of multi device read[4,5,6] tCH CLK R/W tAS tAH A1 A2 A3 A4 A5 A6 A7 A8 tCYC[1] tCL Don’t care DQ Undefined tWS tWH A[0:18][2] A[19][3] tCDP DATA OUT [0:35] (BANK 0) [Pipeline Mode] tOHP Q1 Q2 tHZCP Q4 DATA OUT [0:35] (BANK 1) [Pipeline Mode] tLZCP Q3 tCDP Q5 tOHP Q6 tHZCP tCDF Q1 tOHF Q2 tHZCF Q4 tLZCP tCDF Q3 Q5 DATA OUT [0:35] (BANK 0) [Flow-through Mode] DATA OUT [0:35] (BANK 1) [Flow-through Mode] tLZCF tOHF Q6 tHZCF Read (Bank0) Read (Bank0) Read (Bank1) Read (Bank0) tLZCF Read (Bank1) Read (Bank1) Read (Bank0) Notes: 1. Parameters tCYC, tCH and tCL are different in Flow-through and Pipeline mode of operation (Refer AC Timing characteristics). 2. A for AS9C25512M2018L, A for AS9C25256M2018L 3. A for AS9C25512M2018L, A for AS9C25256M2018L 4. Refer to the above block diagram for the assumed setup. 5. One Bank is assumed to have two AS9C25512M2018L/AS9C25256M2018Ls combined to have an expanded width of 36 bits. Two such Banks are used for depth expansion. 6. All BEn's = L, Counter set in “Load” mode (ADS = L, INC = X, RPT = H), OE =L. 9/24/04, v.1.2 Alliance Semiconductor P. 20 of 30 AS9C25512M2018L AS9C25256M2018L ® Snooze mode Snooze mode is a low-current, power-down mode in which the corresponding port is deselected and its current is reduced to a very low value. Both ports are equipped with independent SNOOZE inputs (ZZ). During Snooze mode, all inputs of the port except ZZ are internally disabled and all its Outputs go to High-Z. ZZ is an asynchronous, active HIGH input that causes the selected port to enter Snooze mode. If both ports go into Snooze mode, the device is deselected and current is reduced to IZZ. When ZZA and ZZB become a logic HIGH, IZZ is guaranteed after the setup time tSCZZ is met. Any READ or WRITE operation pending when the port enters Snooze mode is not guaranteed to complete. Therefore, Snooze mode must not be initiated until valid pending operations are completed. Similarly during the time tRCZZ, when the port is transitioning out of snooze mode, only DESELECT cycles should be given. Snooze mode electrical characteristics Description SNOOZE MODE Current ZZ active to input ignored ZZ inactive to input sampled ZZ active to enter Snooze Current ZZ inactive to exit Snooze Current Conditions ZZA = ZZB >= VIH Symbol IZZ tSCZZ tRCZZ tSIZZ tRIZZ Min 15 2 0 Max 18 2 2 Units mA cycle cycle cycle cycle Snooze mode timing waveform[1,3] Don’t care tCYC CLK CE[2,4] tCES tCEH tCH tCL Undefined ZZ tSIZZ ISupply tSCZZ INPUTS (Except ZZ) OUTPUTS[5] Valid IZZ tRIZZ tRCZZ ZZ recovery cycles Valid ZZ setup cycles tHZC High-Z tLZC (Qout) Notes: 1. During Snooze mode, all dynamic inputs are disabled (except JTAG inputs). During JTAG operations, ZZx must be held Low in order to capture the parallel inputs of the boundary scan register. All static inputs (i.e. PL/FTx,OPTx) and ZZx themselves are not affected during snooze mode. 2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H). 3. All timings are same for Port A and Port B. 4. Minimum of two deselect cycles should be given before asserting snooze and minimum of two deselect cycles should be given after de-asserting snooze to guarantee data integrity. 5. Select cycles indicated before and after Snooze are Read cycles. They can also be Write cycles. 9/24/04, v.1.2 Alliance Semiconductor P. 21 of 30 AS9C25512M2018L AS9C25256M2018L ® AC test conditions Input Pulse Level (Address and Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference levels Output Load (for tLZC, tHZC, tLZOE, tHZOE) Output Load (for all other measurements) GND to 3.0V/GND to 2.4V GND to 3.0V/GND to 2.4V 2V/ns 1.5V/1.25V 1.5V/1.25V Fig. C Fig. B Thevenin equivalent: +3.0/2.4 V 90% GND 10% 90% 10% DOUT Z0 = 50 Ω 50 Ω VL = 1.5/1.25 V 10 pF* 353Ω / 1538Ω +3.3/2.5 V; 319Ω / 1667Ω Figure A: Input Waveform Figure B: Output Load (A) 5 pF* GND Figure C: Output Load (B) * Including scope and jig capacitance 9/24/04, v.1.2 Alliance Semiconductor P. 22 of 30 AS9C25512M2018L AS9C25256M2018L ® IEEE 1149.1 Serial boundary scan (JTAG) The SRAM incorporates a serial boundary scan Test Access Port (TAP). All JTAG pins operate using JEDEC standard 2.5V I/O logic levels. In order to operate the device without using the JTAG feature, all JTAG pins may be left unconnected. On power-up, the device will start in a reset state which will not interfere with normal device operation. TAP Controller block diagram 0 Bypass Register TDI Selection Circuitry 3 2 10 Instruction Register 31 30 29 . . . 2 1 0 Identification Register x[1] Selection Circuitry TDO . . . . . 2 10 Boundary Scan Register1 TCK TMS TAP Controller Note: 1. x = 111 JTAG timing waveform tJCYC tJCH TEST CLK TCK tJIS tJIH TMS/TDI tJCD TDO tJOH tJCL Don’t care Undefined tJRS TRST tJRR 9/24/04, v.1.2 Alliance Semiconductor P. 23 of 30 AS9C25512M2018L AS9C25256M2018L ® TAP AC electrical characteristics[2] Description Clock Clock cycle time Clock frequency Clock high time Clock low time Output Times TCK low to TDO unknown TCK low to TDO valid Setup Times TMS/TDI setup Capture setup Hold Times TMS/TDI hold Capture hold Reset Times JTAG Reset JTAG Reset Recovery tJRS tJRR 50 50 ns ns tJCH[1] tJIH 10 10 ns ns tJIS tJCS 10 10 ns ns [1] Symbol tJCYC fJTAG tJCH tJCL tJOH tJCD Min 100 40 40 0 - Max 10 20 Units ns MHz ns ns ns ns Notes: 1. tJCS and tJCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in the figure TAP AC output load equivalent. TAP AC test conditions & output load equivalent Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vss to 2.5V 1V/ns 1.25V 1.25V 1.25V TDO ZO=50Ω 50Ω 20pF 1.25V TAP DC electrical characteristics and operating conditions (VDD=2.5V ± 100 mV) Description Input high (logic 1) voltage Input low (logic 0) voltage Input leakage current Output leakage current Output low voltage Output low voltage Output high voltage Output high voltage Symbol VIH VIL |ILI| |ILO| VOLC VOLT VOHC VOHT VDD = Max; 0V < VIN < VDD Outputs disabled, 0V < VOUT < VDDQ (DQx) IOLC = 100µA IOLT = 2mA IOHC = -100µA IOHT = -2mA 2.1 1.7 Conditions Min 1.7 -0.3 0 0 Max VDD + 0.3 0.7 10 10 0.2 0.7 Units V V µA µA V V V V 9/24/04, v.1.2 Alliance Semiconductor P. 24 of 30 AS9C25512M2018L AS9C25256M2018L ® Identification register definitions Instruction field Revision number (31:28) Device depth (27:12) JEDEC ID code (11:1) Indicator Bit (0) Value TBD TBD 00001010010 1 Description Version Number ALSC part number Manufacturer Identity Code (ALSC) ID Register presence indicator Scan register sizes Register name Instruction Register (IR) Bypass Register (BYR) Identification Register (IDR) Boundary Scan Register (BSR) Bit size 4 1 32 112 Instruction codes Instruction EXTEST SAMPLE/PRELOAD IDCODE CLAMP HIGHZ RESERVED BYPASS Code 0000 0001 0010 0011 0100 1111 Description Forces contents of the BSR onto the device outputs. Samples the I/O ring contents. Preloads test data into the BSR. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Forces contents of the BSR onto the device outputs. Forces all device 2-state and 3-state outputs to High-Z. Places the BYR between TDI and TDO. Selected Reg BSR BSR IDR BYR BYR BYR BYR 0101 - 1110 Reserved states. Do not use. 9/24/04, v.1.2 Alliance Semiconductor P. 25 of 30 AS9C25512M2018L AS9C25256M2018L ® Package Diagram: 256-ball Ball Grid Array (BGA) All measurements are in mm. Min A B C D E F G H I J 0.40 0.50 0.70 0.35 Typ 1.00 16.95 17.00 17.05 15.00 16.95 17.00 17.05 15.00 0.36 0.50 1.60 0.60 Max A1 corner index Top View Bottom View 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D E F G H J K L M N P R T D J A B C oooooooooooooooo + oooooooooooooooo oooooooooooooooo + oooooooooooooooo + oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo + + ++ A E 0.35 Z A B C D E F G H J K L M N P R T D oooooooooooooooo 0.70 0.36 0.35 ~ 0.50 1.60 MAX F 0.20 Z G H oo oo I / 0.50±0.10 (256X) Ø 0.25 M Z X Y Ø 0.15 M Z Side View Detail of Solder Ball 9/24/04, v.1.2 Alliance Semiconductor P. 26 of 30 AS9C25512M2018L AS9C25256M2018L ® Package Diagram: 208-ball fine pitch Ball Grid Array (fpBGA) All measurements are in mm. Min A B C D E F G H I J 0.40 0.45 0.70 0.25 Typ 0.80 14.95 15.00 15.05 12.80 14.95 15.00 15.05 12.80 0.26 0.40 1.40 0.50 Max A1 corner index Top View Bottom View 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A B C D E F G H J K L M N P R T U D J 0.70 A B C ooooooooooooooooo + ooooooooooooooooo ooooooooooooooooo + ooooooooooooooooo + oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo ooooooooooooooooo ooooooooooooooooo ooooooooooooooooo ooooooooooooooooo + ++ + A E 0.20 Z A B C D E F G H J K L M N P R T U ooooooooooooooooo 0.26 0.25 ~ 0.40 1.40 MAX F 0.15 Z G H oo oo D I / 0.45±0.05 (208X) Ø 0.15 M Z X Y Ø 0.08 M Z Side View Detail of Solder Ball 9/24/04, v.1.2 Alliance Semiconductor P. 27 of 30 AS9C25512M2018L AS9C25256M2018L ® Package Diagram: 144-pin Thin Quad Flat Pack (TQFP) TQFP Min Typ Max A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.17 0.20 0.27 c 0.09 0.20 D 20.00 nominal E 20.00 nominal e 0.50 nominal Hd 22.00 nominal He 22.00 nominal L 0.45 0.60 0.75 L1 1.00 nominal α 0° 3.5° 7° Dimensions in millimeters Hd D b e He E c α L1 L A1 A2 9/24/04, v.1.2 Alliance Semiconductor P. 28 of 30 AS9C25512M2018L AS9C25256M2018L ® Ordering Information Package & Width 512K X 18 BGA X 18 fpBGA X 18 TQFP X 18 256K X 18 BGA X 18 fpBGA X 18 TQFP X 18 AS9C25256M2018L - 250BC AS9C25256M2018L - 250BI AS9C25256M2018L - 250FC AS9C25256M2018L - 250FI AS9C25256M2018L - 250TC AS9C25256M2018L - 250TI AS9C25256M2018L - 200BC AS9C25256M2018L - 200BI AS9C25256M2018L - 200FC AS9C25256M2018L - 200FI AS9C25256M2018L - 200TC AS9C25256M2018L - 200TI AS9C25256M2018L -166BC AS9C25256M2018L - 166BI AS9C25256M2018L - 166FC AS9C25256M2018L - 166FI AS9C25256M2018L - 166TC AS9C25256M2018L - 166TI AS9C25256M2018L - 133BC AS9C25256M2018L - 133BI AS9C25256M2018L - 133FC AS9C25256M2018L - 133FI AS9C25256M2018L - 133TC AS9C25256M2018L - 133TI AS9C25512M2018L - 250BC AS9C25512M2018L - 250BI AS9C25512M2018L - 250FC AS9C25512M2018L - 250FI AS9C25512M2018L - 250TC AS9C25512M2018L - 250TI AS9C25512M2018L - 200BC AS9C25512M2018L - 200BI AS9C25512M2018L - 200FC AS9C25512M2018L - 200FI AS9C25512M2018L - 200TC AS9C25512M2018L - 200TI AS9C25512M2018L -166BC AS9C25512M2018L - 166BI AS9C25512M2018L - 166FC AS9C25512M2018L - 166FI AS9C25512M2018L - 166TC AS9C25512M2018L - 166TI AS9C25512M2018L - 133BC AS9C25512M2018L - 133BI AS9C25512M2018L - 133FC AS9C25512M2018L - 133FI AS9C25512M2018L - 133TC AS9C25512M2018L - 133TI -250 -200 -166 -133 Part Numbering Guide AS 1 9C 2 25 3 512/256 4 M20 5 18 6 L 7 -XXX 8 T or B or F 9 C/I 10 1. Alliance Semiconductor prefix 2. Speciality Memory 3. Operating Voltage: 25 - VDD = 2.5V 4. Device depth: 512 - 512K; 256 - 256K 5. M20 - Multiport - 2port, SSRAM, DCD 6. I/O width - 18 7. I/O interface: L - LVTTL 8. Clock speed (MHz) 9. Package Type: T - TQFP, B - BGA, F - fpBGA 10. Operating Temperature: C - Commercial (00C to 700C); I -Industrial (-400C to 850C) 9/24/04, v.1.2 Alliance Semiconductor P. 29 of 30 ® AS9C25512M2018L AS9C25256M2018L ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Preliminary Information Part Number: AS9C25512M2018L/ AS9C25256M2018L Document Version: v.1.2 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. 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