ASM1232LPU

January 2005 rev 1.5 ASM1232LP/LPS 5V µP Power Supply Monitor and Reset Circuit • • Low-cost surface mount packages: 8-pin/16-pin SO, 8-pin DIP and 8-pin Micro SO packages Wide operating temperature -40°C to +85°C (N suffixed devices) General Description The ASM1232LP/LPS is a fully integrated microprocessor supervisor. It can halt and restart a “hung-up” microprocessor, restart a microprocessor after a power failure. It has a watchdog timer and external reset override. A precision temperature-compensated reference and Applications • • • • • • Microprocessor Systems Computers Controllers Portable Equipment Intelligent Instuments Automotive Systems comparator circuits monitor the 5V, VCC input voltage status. During power-up or when the VCC power supply falls outside selectable tolerance limits, both RESET and RESET become active. When VCC rises above the threshold voltage, the reset signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to stabilize. The trip point tolerance signal, TOL, selects the trip level tolerance to be either 5% or 10%. Each device has both a push-pull, active HIGH reset output and an open drain active LOW reset output. A debounced manual reset input, PBRST, activates the reset outputs for a minimum period of 250ms. There is a watchdog timer to stop and restart a microprocessor that is “hung-up”. The watchdog timeouts periods are selectable: 150ms, 610ms and 1200ms. If the ST input is not strobed LOW before the time-out period expires, a reset is generated. Devices are available in 8-pin DIP, 16-pin SO and compact 8pin MicroSO packages. Typical Operating Circuit +5V ASM1232LP/LPS ST RESET GND TD TOL 10kΩ I/O µP RESET Block Diagram ASM1232LP/LPS VCC TOL Tolerance Selection + Reference VCC 40kΩ Key Features • • • • • • • • 5V supply monitor Selectable watchdog period Debounce manual push-button reset input Precision temperature-compensated voltage reference and comparator. Power-up, power-down and brown out detection 250ms minimum reset time Active LOW open drain reset output and active HIGH push-pull output Selectable trip point tolerance: 5% or 10% RESET - RESET PBRST TD Push Button Debounce Voltage Sense Comparators Watchdog Transition Detector Reset & Watchdog Timer ST GND Alliance Semiconductor 2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com Notice: The information in this document is subject to change without notice January 2005 rev 1.5 ASM1232LP/LPS Pin Configuration DIP/SO/MicroSO PBRST TD TOL GND 1 2 3 4 ASM1232LP ASM1232LPS-2 ASM1232LPU 8 7 6 5 VCC ST RESET RESET NC 1 SO 16 NC 15 VCC 14 NC ST NC RESET NC RESET PBRST 2 NC TD NC TOL NC GND 3 4 5 6 7 8 ASM1232LPS 13 12 11 10 9 Pin Description Pin # 8-Pin Package 1 2 Pin # 16-Pin Package 2 4 Pin Name PBRST TD Function Debounced manual pushbutton RESET input. Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms for TD=Open, and tTD = 1200ms for TD = VCC). Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC) trip point tolerance. Ground. Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 5 9 RESET 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. Active LOW reset output. (See RESET). Strobe input. 5V power. No internal connection. 3 4 6 8 TOL GND 6 7 8 - 11 13 15 1,3,5,7, 10,12,14,16 RESET ST VCC NC 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 2 of 10 January 2005 rev 1.5 ASM1232LP/LPS Detailed Description The ASM1232LP/LPS monitors the microprocessor or microcontroller power supply and generates reset signal, both active HIGH and Active LOW, that halt processor operation whenever the power supply voltage levels are outside a predetermined tolerance. VCC VCCTP(MIN) tR VCCTP(MAX) VCCTP tRPU RESET VOH ~ ~ RESET and RESET outputs RESET is an active HIGH signal developed by a CMOS push-pull output stage and is the logical opposite to RESET. VOL RESET ~~ ~~ RESET is an active LOW signal. It is developed with an open drain driver. A pull up resistor of typical value 10kΩ to 50kΩ is required to connect with the output. Figure 1: Timing Diagram : Power Up Trip Point Tolerance Selection The TOL input is used to determine the level VCC can vary below 5V without asserting a reset. With TOL conected to VCC, RESET and RESET become active whenever VCC falls below 4.5V. RESET and RESET become active when the VCC falls below 4.75V if TOL is connected to ground. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. On power-down, once VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or less until VCC drops below 1.2V. The active HIGH reset signal is valid down to a VCC level of 1.2V also. RESET VOH RESET tRPD VCC VCCTP (MAX) VCCTP VCCTP (MIN) tF Figure 2: Timing Diagram : Power Down Tolerance Select TOL = VCC TOL = GND Tolerance TRIP Point Voltage (V) Min Nom 4.37 4.62 Max 4.49 4.74 Application Information Manual Reset Operation Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset signals. The pushbutton input is debounced and is pulled HIGH through an internal 40kΩ resistor. 10% 5% 4.25 4.5 ~ ~~ VOL ~~ 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 3 of 10 January 2005 rev 1.5 When PBRST is held LOW for the minimum time tPB, both resets become active and remain active for a minimum time period of 250ms after PBRST returns HIGH. The debounced input is guaranteed to recognize pulses greater than 20ms. No external pull-up resistor is required, since PBRST is pulled HIGH by an internal 40kΩ resistor. ST ASM1232LP/LPS power-up after the supply voltage returns to an in-tolerance condition, the reset signal remains active for 250ms minimum, be detected. Valid Strobe Valid Strobe Invalid Strobe allowing the power supply and system microprocessor to stabilize. ST pulses as short as 20ns can The PBRST can be driven from a TTL or CMOS logic line or shorted to ground with a mechanical switch. tPB tPDLY VIL VIH RESET tST tRST tTD (min) tTD (max) ~ PBRST Note: ST is ignored whenever a reset is active Figure 5: Timing Diagram: Strobe Input Timeouts periods of approximately 150ms, 610ms or 1,200ms are selected through the TD pin. VOH VOL ~ ~ tRST RESET RESET Figure 3: Timing Diagram: Pushbutton Reset ASM1232LP/LPS 1 2 3 4 PBRST TD TOL GND VCC 8 ST RESET RESET Figure 4: Application Circuit: Pushbutton Reset Watchdog Timer and ST Input A watchdog timer stops and restarts a microprocessor that is “hung-up”. The µP must toggle the ST input within a set period (as selectable through TD input) to verify proper software execution. If the ST is not toggled low within the minimum timeout period, reset signals become active. In ~~ ~~ 5V 7 6 5 I/O TD Voltage level Watchdog Time-out Period (ms) Min Nom 150 610 1200 Max 250 1000 2000 GND Floating VCC 62.5 250 500 The watchdog timer can not be disabled. It must be strobed µP RESET 5V with a high-to-low transition to avoid watchdog timeout and reset. ASM1232 LP/LPS 1 2 3 4 PBRST TD TOL GND VCC 8 ST RESET MREQ 10kΩ 7 6 5 µP RESET Address Bus Decoder Figure 6: Application Circuit: Watchdog Timer 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 4 of 10 January 2005 rev 1.5 ASM1232LP/LPS Absolute Maximum Ratings Parameter Voltage on VCC Voltage on ST, TD Voltage on PBRST, RESET, RESET Operating Temperature Range (N suffixed devices) Operating Temperature Range (others) Soldering Temperature (for 10 sec) Storage Temperature ESD rating HBM MM Min -0.5 -0.5 -0.5 -40 0 Max 7 VCC + 0.5 VCC + 0.5 +85 70 +260 Unit V V V °C °C °C °C KV V -55 +125 2 200 Note: 1. Voltages are measured with respect to ground 2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC Electrical Characteristics Unless otherwise stated, 4.5V