ASM2I2314AGNZ-28-SR

June 2005 rev 0.4 ASM2I2314ANZ 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Features One input to 14 output Buffer/Driver Supports up to three SDRAM DIMMs Two additional outputs for feedback Serial interface for output control Low skew outputs Up to 133MHz operation Multiple VDD and VSS pins for noise reduction Dedicated OE pin for testing Low EMI outputs 28 Pin SOIC (300-mil) package 3.3V operation Functional Description The ASM2I2314ANZ is a 3.3V buffer designed to distribute high-speed clocks in desktop PC applications. The part has 14 outputs, 12 of which can be used to drive up to three SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 133MHz, thus making it compatible with Pentium®* II processors. The ASM2I2314ANZ can be used in conjunction with the clock synthesizer for a complete Pentium II motherboard solution. The ASM2I2314ANZ also includes a serial interface which can enable or disable each output clock. On power-up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE. *Pentium is a registered trademark of Intel Corporation. Block Diagram BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDATA Serial Interface Decoding SCLOCK SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 OE SDRAM13 Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. June 2005 rev 0.4 Pin Configuration 28- Pin SOIC Package -- Top View VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN SDRAM4 SDRAM5 SDRAM12 VDDIICC SDATA 1 2 3 4 5 6 7 28 27 26 25 24 23 22 ASM22314ANZ VDD SDRAM11 SDRAM10 VSS VDD SDRAM9 SDRAM8 VSS OE SDRAM7 SDRAM6 SDRAM13 VSSIIC SCLK ASM2I2314ANZ 8 9 10 11 12 13 14 21 20 19 18 17 16 15 Pin Description Pins 1, 5, 24, 28 4, 8, 21, 25 13 16 9 20 14 15 2, 3, 6, 7, 10, 11, 18, 19, 22, 23, 26, 27, 12, 17 VDD VSS VDDIIC VSSIIC BUF_IN OE SDATA SCLK SDRAM [0-13] Name Type P P P P I I I/O I O Ground Description 3.3V Digital voltage supply 3.3V Serial Interface Voltage supply Ground for serial interface Input clock .5V Tolerant Output Enable, three-states outputs when LOW. Internal pull-up to VDD Serial data input, internal pull-up to VDD. 5V Tolerant Serial clock input, internal pull-up to VDD. 5V Tolerant SDRAM Clock Outputs Device Functionality OE 0 1 SDRAM [0-13] High-Z 1 x BUF_IN 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 2 of 13 June 2005 rev 0.4 Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved bits should be programmed to “0” or “1”. • Serial interface address for the ASM2I2314ANZ is: ASM2I2314ANZ Byte 1: SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 27 26 23 22 --19 18 Description SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved Reserved SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---- Byte 0:SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 2: SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 11 10 --7 6 3 2 Description SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Reserved Reserved SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Pin # 17 12 ------- Description SDRAM13 (Active/Inactive) SDRAM12 (Active/Inactive) Reserved Reserved Reserved Reserved Reserved Reserved Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value of all the bits is high after chip is powered up. IIC Byte Flow Byte 1 2 3 4 5 6 Description IIC Address Command (dummy value, ignored) Byte Count (dummy value, ignored) IIC Data Byte 0 IIC Data Byte 1 IIC Data Byte 2 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 3 of 13 June 2005 rev 0.4 Absolute Maximum Ratings Symbol VDD VIN VBUFIN TSTG TJ TDV ASM2I2314ANZ Parameter Supply Voltage to Ground Potential DC Input Voltage (Except BUF_IN) DC Input Voltage (BUF_IN) Storage Temperature Junction Temperature Static Discharge Voltage (As per JEDEC STD 22- A114-B) Rating –0.5 to +7.0 –0.5 to VDD + 0.5 –0.5 to +7.0 –65 to +150 150 2 Unit V V V °C °C KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions1 Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.135 0 0.05 Max 3.465 70 30 7 50 Unit V °C pF pF mS Note: 1. Electrical parameters are guaranteed under the operating conditions specified. 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 4 of 13 June 2005 rev 0.4 Electrical Characteristics (Test condition: All parameters values are valid within the Operating range, unless otherwise stated) ASM2I2314ANZ Parameter VIL VILIIC VIH VOL VOH ICC IOZ IOFF ∆ICC Ii IDD IDD IDD IDD IDD IDD IDDS Description Input LOW Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage 1 Test Conditions Except serial interface pins For serial interface pins only IOL= 25 mA IOH = –36 mA VDD= 3.465V, Vi = VDD or GND, IO =0 VDD= 3.465V, Vi = VDD or GND VDD= 0V, Vi = 0V or 5.5V VDD= 3.135V to 3.465V One Input at VDD-0.6, All other Inputs at VDD or GND VDD= 3.465V or GND (Applicable to all Input Pins) Unloaded outputs, 133 MHz Loaded outputs, 30pF, 133 MHz Unloaded outputs, 100 MHz Loaded outputs, 30pF ,100 MHz Unloaded outputs, 66.67 MHz Loaded outputs, 30pF ,66.67 MHz BUF_IN=VDD or VSS All other inputs at VDD Min 2.0 2.4 Typ Max 0.8 0.7 0.4 - Unit V V V V V µA µA µA µA µA mA mA mA mA mA mA µA Output HIGH Voltage1 Quiescent Supply Current High Impedance Output Current Off-State Current (for SCL ,SDATA) Change in Supply Current Input Leakage Supply Current Supply Current Supply Current Supply Current Supply Current 1 1 1 50 100 ±10 50 500 -5 +5 266 360 - 200 290 150 185 500 Supply Current1 1 1 Supply Current Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 5 of 13 June 2005 rev 0.4 Switching Characteristics1 Parameter Fin tD t3 t4 t5 t6 t7 tPLZ, tPHZ tPZL, tPZH tr tf Duty cycle 2,3 ASM2I2314ANZ Name Maximum Operating Frequency = t2 ÷ t1 Rising Edge Rate3 Falling Edge Rate3 Output to Output Skew3 SDRAM Buffer LH Prop. Delay SDRAM Buffer Enable Delay 3 3 3 Test Conditions Measured at 1.5V Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V All outputs equally loaded Input edge greater than 1 V/nS Input edge greater than 1 V/nS Input edge greater than 1 V/nS Input edge greater than 1 V/nS CL = 10pF CL = 400pF CL = 10pF CL = 400pF Min 45.0 1 1 Typ 50.0 2 2 150 Max 133 55.0 4 4 225 3.5 3.5 5 5 250 Unit MHz % V/nS V/nS pS nS nS nS nS nS nS 1 1 1 1 6 20 2.7 2.7 3 3 SDRAM Buffer HL Prop. Delay SDRAM Buffer Disable Delay3 Rise Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3 Fall Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3 250 Note: 1. All parameters specified with loaded outputs. 2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. Test Circuit for SDRAM Enable and Disable Times S1 2 * VDD Open VSS VDD 500Ω VI PULSE GENERATOR RT D.U.T 500Ω VO CL TEST t6/t7 tPLZ/tPZL tPHZ/tPZH S1 Open 2* VDD VSS Figure 1. Load circuit for Switching times 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 6 of 13 June 2005 rev 0.4 SDRAM Enable and Disable Times VM = 1.5V VX = VOL +0.3V VY = VOH -0.3V VOH and VOL are the typical Output Voltage drop that occur with the output load VI OE INPUT GND tPLZ VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VDD OUTPUT HIGH-to-OFF OFF-to-HIGH VSS Outputs enabled Outputs disabled Outputs enabled tPZH tPZL VM VX VDD ASM2I2314ANZ VM VY VM Figure 2. 3-State Enable and Disable times Test Circuit for IIC Rise and Fall Times VO = 3.3V RL = 1kΩ DUT CL = 10pF or CL = 400pF GND Figure 3. Test Circuit for IIC 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 7 of 13 June 2005 rev 0.4 Switching Waveforms ASM2I2314ANZ Duty Cycle Timing t1 t2 1.5 V 1.5 V 1.5 V All Outputs Rise/Fall Time 2.4 V OUTPUT 0.4 V 2.4 V 0.4 V 3.3 V 0V t3 t4 Output - Output Skew 1.5 V OUTPUT 1.5 V OUTPUT t5 SDRAM Buffer LH and HL Propagation Delay INPUT OUTPUT t6 t7 Test Circuit VDD 0.1 µ F OUTPUTS CLK Out CLOAD GND 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 8 of 13 June 2005 rev 0.4 Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. ASM2I2314ANZ Application Circuit Rs CPUCLK BUF_IN Rs SDRAM (0.13) SDRAM (0.13) SDATA SCLK VDD 3.3V SDATA Ct SCLK VDD VSS Cd = 0.1 µ F ASM2I2314ANZ 28-Pin SOIC Cd = DECOUPLING CAPACITORS Ct = OPTIONAL EMI-REDUCING CAPACITORS Rs = SERIES TERMINATING RESISTORS Summary • • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1µF. In some cases, smaller value capacitors may be required. The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • • • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7pF to 22pF. A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. If a Ferrite Bead is used, a 10µF–22µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 9 of 13 June 2005 rev 0.4 IIC Serial Interface Information The information in this section assumes familiarity with IIC programming. ASM2I2314ANZ How to program ASM2I2314ANZ through IIC: • • • • • • • • • • • • • • Master (host) sends a start bit. Master (host) sends the write address D3(H). ASM2I2314ANZ device will acknowledge. Master (host) sends the Command Byte. ASM2I2314ANZ device will acknowledge the Command Byte. Master (host) sends a Byte count ASM2I2314ANZ device will acknowledge the Byte count. Master (host) sends the Byte 0 ASM2I2314ANZ device will acknowledge Byte 0 Master (host) sends the Byte 1 ASM2I2314ANZ device will acknowledge Byte 1 Master (host) sends the Byte 2 ASM2I2314ANZ device will acknowledge Byte 2 Master (host) sends a Stop bit. Controller (Host) Start Bit Slave Address D3(H) ASM22314ANZ (slave/receiver) ACK Command Byte ACK Byte count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Stop Bit 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 10 of 13 June 2005 rev 0.4 Package Information 28L SOIC Package (300 mil) ASM2I2314ANZ Dimensions Symbol A A1 A2 D h E H R1 b b1 c c1 L e θ Inches Min Max 0.093 0.004 0.088 0.697 0.010 0.291 0.394 0.003 0.013 0.013 0.009 0.009 0.016 0° 0.104 0.012 0.094 0.712 0.029 0.299 0.419 …. 0.022 0.020 0.015 0.013 0.050 8° Millimeters Min Max 2.35 0.10 2.25 17.70 0.25 7.40 10.00 0.08 0.33 0.33 0.23 0.23 0.40 0° 2.65 0.30 2.40 18.10 0.75 7.60 10.65 ….. 0.56 0.51 0.38 0.33 1.27 8° 0.050 BSC 1.27 BSC 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 11 of 13 June 2005 rev 0.4 Ordering Information Ordering Code ASM2I2314ANZ-28-ST ASM2I2314ANZ-28-SR ASM2I2314AGNZ-28-ST ASM2I2314AGNZ-28-SR ASM2I2314ANZ Marking 2I2314ANZ 2I2314ANZ 2I2314AGNZ 2I2314AGNZ Package Type 28 Pin SOIC, Tube 28 Pin SOIC, Tape and Reel 28 Pin SOIC, Tube, Green 28 Pin SOIC, Tape and Reel, Green Operating Range Industrial Industrial Industrial Industrial Device Ordering Information ASM2I2314ANZG-28-SR R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 12 of 13 June 2005 rev 0.4 ASM2I2314ANZ Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2I2314ANZ Document Version: 0.4 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2004 Alliance Semiconductor Corporation. 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