ASM2I2318ANZ-48-AT

June 2005 rev 0.3 ASM2I2318ANZ 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Features One input to 18 output Buffer/Driver Supports up to four SDRAM DIMMs Two additional outputs for feedback Serial interface for individual output control Low skew outputs (< 250 pS) Up to 133 MHz operation Dedicated OE pin for testing Space-saving 48 Pin SSOP package 3.3V operation Functional Description The ASM2I2318ANZ is a 3.3V buffer designed to distribute high-speed clocks in PC applications. The part has 18 outputs, 16 of which can be used to drive up to four SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 133MHz, thus making it compatible with Pentium II®* processors. The ASM2I2318ANZ can be used in conjunction with the clock synthesizer for a complete Pentium II motherboard solution. The ASM2I2318ANZ also includes a serial interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull up). A separate Output Enable pin facilitates testing on ATE. *Pentium is a registered trademark of Intel Corporation. Block Diagram BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 Serial Interface Decoding SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17 SDATA SCLOCK OE Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. June 2005 rev 0.3 Pin Configuration 48-Pin SSOP Package -- Top View NC 1 NC 2 VDD 3 SDRAM0 4 SDRAM1 5 VSS 6 VDD 7 SDRAM2 8 SDRAM3 9 VSS 10 BUF_IN 11 VDD 12 SDRAM4 13 SDRAM5 14 VSS 15 VDD 16 SDRAM6 17 SDRAM7 18 VSS 19 VDD 20 SDRAM16 21 VSS 22 VDDIIC 23 SDATA 24 48 NC 47 NC 46 VDD 45 SDRAM15 44 SDRAM14 43 VSS 42 VDD 41 SDRAM13 40 SDRAM12 39 VSS ASM2I2318ANZ ASM2I2318ANZ 38 OE 37 VDD 36 SDRAM11 35 SDRAM10 34 VSS 33 VDD 32 SDRAM9 31 SDRAM8 30 VSS 29 VDD 28 SDRAM17 27 VSS 26 VSSIIC 25 SCLOCK Pin Description Pins 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 23 26 11 38 24 25 4, 5, 8, 9 13, 14, 17, 18 31, 32, 35, 36 40, 41, 44, 45 21, 28 NC VDD VSS VDDIIC VSSIIC BUF_IN OE SDATA SCLK SDRAM [0–3] SDRAM [4–7] SDRAM [8–11] SDRAM [12–15] SDRAM [16–17] 1, 2, 47, 48 Name Type P P P P I I I/O I O O O O O 3.3V Digital voltage supply Ground Description Serial interface voltage supply Ground for serial interface Input clock. 5V tolerant Output Enable (active HIGH), Three-state outputs when low1 Serial data input1. 5V tolerant Serial clock input1. 5V tolerant SDRAM byte 0 clock outputs SDRAM byte 1 clock outputs SDRAM byte 2 clock outputs SDRAM byte 3 clock outputs SDRAM clock outputs usable for feedback Reserved for future modifications, do not connect in system Note: 1. Internal pull-up resistor to VDD (value > 100 KOhms) 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 2 of 13 June 2005 rev 0.3 Device Functionality OE 0 1 ASM2I2318ANZ SDRAM [0-17] Hi-Z 1 x BUF_IN Byte 1: SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 45 44 41 40 36 35 32 31 Description SDRAM15 (Active/Inactive) SDRAM14 (Active/Inactive) SDRAM13 (Active/Inactive) SDRAM12 (Active/Inactive) SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved bits should be programmed to “0” or ”1”. • Serial interface address for the ASM2I2318ANZ is: Byte 2: SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---- Pin # 28 21 ------- Description SDRAM17 (Active/Inactive) SDRAM16 (Active/Inactive) Reserved Reserved Reserved Reserved Reserved Reserved Byte 0:SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 18 17 14 13 9 8 5 4 Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value of all the bits is high after chip is powered up. IIC Byte Flow Byte 1 2 3 4 5 6 Description IIC Address Command (dummy value, ignored) Byte Count (dummy value, ignored) IIC Data Byte 0 IIC Data Byte 1 IIC Data Byte 2 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 3 of 13 June 2005 rev 0.3 Absolute Maximum Ratings Symbol VDD VIN VBUFIN TSTG TJ TDV ASM2I2318ANZ Parameter Supply Voltage to Ground Potential DC Input Voltage (Except BUF_IN) DC Input Voltage (BUF_IN) Storage Temperature Junction Temperature Static Discharge Voltage (As per JEDEC STD 22- A114-B) Rating –0.5 to +7.0 –0.5 to VDD + 0.5 –0.5 to +7.0 –65 to +150 150 2 Unit V V V °C °C KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions1 Parameter VDD VDDIIC TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min 3.135 0 20 Max 3.465 70 30 7 50 Unit V °C pF pF mS Note: 1. Electrical parameters are guaranteed under the operating conditions specified. 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 4 of 13 June 2005 rev 0.3 Electrical Characteristics (Test condition: All parameters values are valid within the Operating range, unless otherwise stated) ASM2I2318ANZ Parameter VIL VILiic VIH VOL VOH ICC IOZ IOFF ∆ICC Ii IDD IDD IDD IDD IDD IDD IDDS Description Input LOW Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage1 Output HIGH Voltage1 Quiescent Supply Current High Impedance Output Current Off-State Current (for SCL ,SDATA) Change in Supply Current Input Leakage Supply Current Supply Current1 Supply Current1 Supply Current1 Supply Current1 Supply Current1 Supply Current 1 Test Conditions For all pins except serial interface pins For serial pins only Min Typ Max 0.8 0.7 Unit V V V V V µA µA µA µA µA mA mA mA mA mA mA µA 2.0 IOL= 25 mA IOH = –36 mA VDD= 3.465V, Vi = VDD or GND, IO =0 VDD= 3.465V, Vi = VDD or GND VDD= 0V, Vi = 0V or 5.5V VDD= 3.135V to 3.465V One Input at VDD-0.6, All other Inputs at VDD or GND VDD= 3.465V or GND (Applicable to all Input Pins) Unloaded outputs, 133 MHz Loaded outputs, 30pF,133 MHz Unloaded outputs, 100 MHz Loaded outputs, 30pF, 100 MHz Unloaded outputs, 66.67 MHz Loaded outputs, 30pF, 66.67 MHz BUF_IN=VDD or VSS, all other inputs at VDD 0.4 2.4 50 100 ±10 50 500 -5 +5 150 400 110 300 80 200 500 Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 5 of 13 June 2005 rev 0.3 Switching Characteristics1 Parameter Fin tD t3 t4 t5 t6 t7 tPLZ, tPHZ tPZL, tPZH tr tf Duty cycle ASM2I2318ANZ Name Maximum Operating Frequency 2,3 Test Conditions Measured at 1.5V Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V All outputs equally loaded 3 3 Min 45.0 1 1 Typ 50.0 2 2 150 Max 133 55.0 4 4 225 3.5 3.5 5 5 250 Unit MHz % V/nS V/nS pS nS nS nS nS nS nS = t2 ÷ t1 Rising Edge Rate3 Falling Edge Rate3 Output to Output Skew3 SDRAM Buffer LH Prop. Delay SDRAM Buffer Enable Delay 3 Input edge greater than 1 V/nS Input edge greater than 1 V/nS Input edge greater than 1 V/nS Input edge greater than 1 V/nS CL = 10pF CL = 400pF CL = 10pF CL = 400pF 1 1 1 1 6 20 2.7 2.7 3 3 SDRAM Buffer HL Prop. Delay SDRAM Buffer Disable Delay3 Rise Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3 Fall Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3 250 Note: 1. All parameters specified with loaded outputs. 2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. Test Circuit for SDRAM Enable and Disable Times S1 2 * VDD Open VSS VDD 500Ω VI PULSE GENERATOR RT D.U.T 500Ω VO CL TEST t6/t7 tPLZ/tPZL tPHZ/tPZH S1 Open 2* VDD VSS Figure 1. Load circuit for Switching times 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 6 of 13 June 2005 rev 0.3 SDRAM Enable and Disable Times VM = 1.5V VX = VOL +0.3V VY = VOH -0.3V VOH and VOL are the typical Output Voltage drop that occur with the output load ASM2I2318ANZ VI OE INPUT GND VM VDD tPLZ VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VDD OUTPUT HIGH-to-OFF OFF-to-HIGH VSS Outputs enabled Outputs disabled tPZL VM VX tPZH VY VM Outputs enabled Figure 2. 3-State Enable and Disable times Test Circuit for IIC Rise and Fall Times VO = 3.3V RL = 1kΩ DUT CL = 10pF or CL = 400pF GND Figure 3. Test Circuit for IIC 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 7 of 13 June 2005 rev 0.3 Switching Waveforms ASM2I2318ANZ Duty Cycle Timing t1 t2 1.5 V 1.5 V 1.5 V All Outputs Rise/Fall Time 2.4 V OUTPUT 0.4 V 2.4 V 0.4 V 3.3 V 0V t3 t4 Output - Output Skew 1.5 V OUTPUT 1.5 V OUTPUT t5 SDRAM Buffer LH and HL Propagation Delay INPUT OUTPUT t6 t7 Test Circuit VDD 0.1 µ F OUTPUTS CLK Out CLOAD GND 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 8 of 13 June 2005 rev 0.3 Application Circuit +3.3V Rs CPUCLK BUF_IN VDDiic 0.1ụF VDD 0.1ụF ASM2I2318ANZ SDRAM(0:17) Rs SDRAM(0:17) Ct SDATA SCLK VDDiic VSS ASM2I2318ANZ 48-Pin SSOP Rs = Series termination resistor Ct = Optional cap to reduce EMI Summary • • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1µF. In some cases, smaller value capacitors may be required. The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • • • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7pF to 22pF. A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. If a Ferrite Bead is used, a 10µF–22µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 9 of 13 June 2005 rev 0.3 IIC Serial Interface Information The information in this section assumes familiarity with IIC programming. ASM2I2318ANZ How to program ASM2I2318ANZ through IIC: • • • • • • • • • • • • • • Master (host) sends a start bit. Master (host) sends the write address D3 (H). ASM2I2318ANZ device will acknowledge. Master (host) sends the Command Byte. ASM2I2318ANZ device will acknowledge the Command Byte. Master (host) sends a Byte count ASM2I2318ANZ device will acknowledge the Byte count. Master (host) sends the Byte 0 ASM2I2318ANZ device will acknowledge Byte 0 Master (host) sends the Byte 1 ASM2I2318ANZ device will acknowledge Byte 1 Master (host) sends the Byte 2 ASM2I2318ANZ device will acknowledge Byte 2 Master (host) sends a Stop bit. Controller (Host) Start Bit Slave Address D3(H) ASM2I2318ANZ (slave/receiver) ACK Command Byte ACK Byte count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Stop Bit 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 10 of 13 June 2005 rev 0.3 Package Information 48L SSOP Package (300 mil) ASM2I2318ANZ Dimensions Symbol A A1 B C D E H L e α Inches Min Max 0.095 0.008 0.008 0.005 0.620 0.291 0.395 0.020 0° 0.110 0.016 0.012 0.009 0.630 0.299 0.420 0.040 8° Millimeters Min Max 2.413 0.203 0.203 0.127 15.75 7.39 10.033 0.508 0° 2.794 0.406 0.305 0.228 16.002 7.59 10.67 1.016 8° 0.025 BSC 0.635 BSC 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 11 of 13 June 2005 rev 0.3 Ordering Information Ordering Code ASM2I2318ANZ-48-AT ASM2I2318ANZ-48-AR ASM2I2318AGNZ-48-AT ASM2I2318AGNZ-48-AR ASM2I2318ANZ Marking 2I2318ANZ 2I2318ANZ 2I2318AGNZ 2I2318AGNZ Package Type 48 Pin SSOP, Tube 48 Pin SSOP, Tape and Reel 48 Pin SSOP, Tube, Green 48 Pin SSOP, Tape and Reel, Green Operating Range Industrial Industrial Industrial Industrial Device Ordering Information ASM2I2318ANZG-48-AR R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 12 of 13 June 2005 rev 0.3 ASM2I2318ANZ Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2I2318ANZ Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 13 of 13