ASM2I9942PG-32-ER

May 2005 rev 0.3 Low Voltage 1:18 Clock Distribution Chip Features LVPECL Clock Input 2.5V LVCMOS Outputs for Pentium IITM* ASM2I9942P With low output impedance (≈12Ω), in both the HIGH and LOW logic states, the output buffers of the ASM2I9942P are ideal for driving series terminated transmission lines. With an output impedance of 12Ω, the ASM2I9942P can Output–to–Output drive two series terminated transmission lines from each output. This capability gives the ASM2I9942P an effective fanout of 1:36. The ASM2I9942P provides enough copies of low skew clocks for most high performance synchronous systems. The differential LVPECL inputs of the ASM2I9942P allow the device to interface directly with a LVPECL fanout buffer to build very wide clock fanout trees or to couple to a high frequency clock source. The OE pins will place the outputs into a high impedance state. The OE pin has an internal pullup resistor. The ASM2I9942P is a single supply device. The VCC power pins require either 2.5V or 3.3V. The 32 lead LQFP and TQFP package is chosen to optimize performance, board space and cost of the device. The 32–lead LQFP and TQFP have a 7x7mm2 body size with conservative 0.8mm pin spacing. Microprocessor Support 200pS Skew Maximum Output Frequency of 250MHz @3.3 VCC 32–Lead LQFP and TQFP Packaging Single 3.3V or 2.5V Supply Pin and Function compatible with MPC942P Maximum Targeted Functional Description The ASM2I9942P is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device is offered in two versions; the ASM2I9942C has an LVCMOS input clock while the ASM2I9942P has a LVPECL input clock. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50Ω series or parallel terminated transmission lines. With output-to-output skews of 200pS, the ASM2I9942P is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V outputs also make the device ideal for supplying clocks for a high performance Pentium IITM microprocessor based design. * Pentium II is a trademark of Intel Corporation Block Diagram Q0 PECL_CLK PECL_CLK OE (Int. Pullup) Q1-Q16 Q17 Table 1. Function Table OE 0 1 Output HIGH IMPEDANCE OUTPUTS ENABLED Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. May 2005 rev 0.3 Pin Diagram GND Q10 Q11 VCC Q6 Q7 Q8 Q9 ASM2I9942P 24 GND Q5 Q4 Q3 VCC Q2 Q1 Q0 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 17 16 15 14 VCC Q12 Q13 Q14 GND Q15 Q16 Q17 ASM2I9942P 13 12 11 10 9 2 3 4 5 6 7 8 VCC PECL_CLK Table 2. Pin Description Pin # 5 6 3 4 32,31,30,28,27,26,24,23,22,20,19,18,15, 14,13,11,10,9 1,2,12,17,25 7,8,16,21,29 Pin Name PECL_CLK, PECL_CLK OE NC Q0 – Q17 GND VCC I/O Input Input Output Supply Supply PECL_CLK GND GND VCC OE NC Type LVPECL LVCMOS LVCMOS Ground VCC Function LVPECL Clock Inputs Output enable/disable (high–impedance tristate) No connect Clock outputs Negative power supply (GND) for I/O and core. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 3. Absolute Maximum Rating1 Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range Parameter Min –0.3 –0.3 –40 Max 3.6 VCC + 0.3 ±20 125 Unit V V mA °C Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 2 of 10 May 2005 rev 0.3 Table 4. DC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%) Symbol VIH VIL VPP VX VOH VOL IIN CIN CPD ZOUT ICC ASM2I9942P Characteristic Input HIGH Voltage Input LOW Voltage Input Swing PECL_CLK Input Crosspoint PECL_CLK Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current Min 2.0 0.6 VCC–1.0 2.0 Typ Max VCC 0.8 1.0 VCC–0.6 0.5 ±200 Unit V V V V V V µA pF pF Ω Condition IOH = –16 mA IOL = 16 mA 4.0 14 12 0.5 5.0 Per Output mA Table 5. AC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%) Symbol Fmax tPLH tPHL tsk(o) tsk(pr) tsk(pr) tr, tf Characteristic Maximum Frequency Propagation Delay Propagation Delay Output-to-Output Skew within one bank Part–to–Part Skew 1 Part–to–Part Skew 2 Min 1.8 2.0 Typ Max 200 4.0 4.3 150 2.2 1.3 Unit MHz nS nS pS nS pS nS Condition Output Rise/Fall Time 0.1 1.0 Note: 1. Across temperature and voltage ranges, includes output skew. 2. For a specific temperature and voltage, includes output skew. Table 6. DC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%) Symbol VIH VIL VPP VX VOH VOL IIN CIN CPD ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Input Swing PECL.CLK Input Crosspoint PECL_CLK Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current Min 2.4 0.6 VCC–1.0 2.4 Typ Max VCC 0.8 1.0 VCC–0.6 0.6 ±200 Unit V V V V V V µA pF pF Ω Condition IOH = –20 mA IOL = 20 mA 4.0 14 12 0.5 5.0 Per Output mA Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 3 of 10 May 2005 rev 0.3 Table 7. AC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%) Symbol Fmax tPLH tPHL tsk(o) tsk(pr) tsk(pr) tr, tf ASM2I9942P Characteristic Maximum Frequency Propagation Delay Propagation Delay Output-to-output Skew within one bank Part–to–Part Skew 1 Min 1.5 1.5 Typ Max 250 3.2 3.6 150 1.7 1.0 Unit MHz nS nS pS nS pS nS Condition Part–to–Part Skew2 Output Rise/Fall Time 0.1 1.0 Note: 1. Across temperature and voltage ranges, includes output skew. 2. For a specific temperature and voltage, includes output skew. Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 4 of 10 May 2005 rev 0.3 Power Consumption of the ASM2I9942P and Thermal Management The ASM2I9942P AC specification is guaranteed for the entire operating frequency range up to 250MHz. The ASM2I9942P power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the ASM2I9942P die junction temperature and the associated device reliability. ASM2I9942P per output, (Μ)ΣCL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the ASM2I9942P). The ASM2I9942P supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, ΣCL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used ΣCL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 8, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the ASM2I9942P in a series terminated transmission line system, equation 4. Table 8. Die junction temperature and MTBF Junction temperature (°C) 100 110 MTBF (Years) 20.4 9.1 120 4.2 130 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the ASM2I9942P needs to be controlled and the thermal impedance of the board/package should be optimized.The power dissipated in the ASM2I9942P is represented in equation 1. Where ICCQ is the static current consumption of the ASM2I9942P, CPD is the power dissipation capacitance    PTOT =  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  ⋅ VCC M       PTOT = VCC ⋅  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  + ∑ DC Q ⋅ I OH (VCC − VOH ) + (1 − DC Q ) ⋅ I OL ⋅ VOL M  P   T J = T A + PTOT ⋅ Rthja Equation 1 [ ] Equation 2 Equation 3 Equation 4 f CLOCKMAX = C PD 1 2 ⋅ N ⋅ VCC T  − TA ⋅  JMAX − (I CCQ ⋅ VCC )  Rthja    Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 5 of 10 May 2005 rev 0.3 TJ,MAX should be selected according to the MTBF system requirements and Table 8. Rthja can be derived from Table 9. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in lower thermal impedance than indicated below. ASM2I9942P If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the ASM2I9942P. The charts were calculated for a maximum tolerable die junction temperature of 110°C (120°C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. Table 9. Thermal package impedance of the 32LQFP Convection, Rthja (1P2S Rthja (2P2S board), °C/W board), °C/W LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm 86 76 71 68 66 60 61 56 54 53 52 49 Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 6 of 10 May 2005 rev 0.3 Package Information 32-lead TQFP Package ASM2I9942P SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e Inches Min Max …. 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7° 0.03937 REF 1.00 REF 0.031 BASE Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 7 of 10 May 2005 rev 0.3 32-lead LQFP Package ASM2I9942P SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a Inches Min Max …. 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7° 0.03937 REF 1.00 REF 0.031 BASE 0.8 BASE Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 8 of 10 May 2005 rev 0.3 Ordering Information Ordering Code ASM2I9942P-32-LT ASM2I9942P-32-LR ASM2I9942PG-32-LT ASM2I9942PG-32-LR ASM2I9942P-32-ET ASM2I9942P-32-ER ASM2I9942PG-32-ET ASM2I9942PG-32-ER ASM2I9942P Marking ASM2I9942PL ASM2I9942PL ASM2I9942PGL ASM2I9942PGL ASM2I9942PE ASM2I9942PE ASM2I9942PGE ASM2I9942PGE Package Type 32-pin LQFP, Tray 32-pin LQFP,Tape and Reel 32-pin LQFP, Tray, Green 32-pin LQFP,Tape and Reel, Green 32-pin TQFP, Tray 32-pin TQFP,Tape and Reel 32-pin TQFP, Green 32-pin TQFP,Tape and Reel, Green Operating Range Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Device Ordering Information ASM2I9942PG-32-LR R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 9 of 10 May 2005 rev 0.3 ASM2I9942P Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2I9942P Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 10 of 10