ASM2P20805A-20-DR

June 2005 rev 0.2 2.5V CMOS Dual 1-To-5 Clock Driver Features Advanced CMOS Technology Guaranteed low skew < 200pS (max.) Very low propagation delay < 2.5nS (max) Very low duty cycle distortion < 270pS (max) Very low CMOS power levels Operating frequency up to 166MHz TTL compatible inputs and outputs Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output VCC = 2.5V ± 0.2V Available in SSOP and QSOP packages ASM2P20805A Functional Description The ASM2P20805A is a 2.5V Clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The ASM2P20805A offers low capacitance inputs. The ASM2P20805A is designed for high speed clock distribution where signal quality and skew are critical. The ASM2P20805A also allows single point-topoint transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality. Block Diagram Pin Diagram OEA INA 5 OA1 – OA5 VCCA OA1 OA2 OA3 GNDA 1 2 3 4 5 6 7 8 9 10 20 VCCB OB1 OB2 OB3 GNDB OB4 OB5 MON OEB INB INB OEB 5 OB1 – OB5 OA4 OA5 GNDQ MON OEA INA A S M 2 P 2 0 8 0 5 A 19 18 17 16 15 14 13 12 11 Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. June 2005 rev 0.2 Pin Description Pin # 9,12 10,11 2,3,4,6,7 19,18,17,15,14 1 20 5 16 8 13 ASM2P20805A Pin Names OEA, OEB ¯¯ ¯¯ INA, INB OA1-OA5 OB1-OB5 VCCA VCCB GNDA GNDB GNDQ MON Description 3-State Output Enable Inputs (Active LOW) Clock Inputs Clock Outputs Clock Outputs Power supply for Bank A Power supply for Bank B Ground for Bank A Ground for Bank B Ground Monitor Output Function Table Inputs OEA, OEB ¯¯ ¯¯ L L H H Note: H = HIGH; L = LOW; Z = High-Impedance Outputs INA, INB L H L H OAn, OBn L H Z Z MON L H L H Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter* Input Capacitance Output Capacitance Conditions VIN= 0V VOUT = 0V Typ 3 - Max 4 6 Unit pF pF *This parameter is measured at characterization but not tested. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 2 of 11 June 2005 rev 0.2 Absolute Maximum Ratings Symbol VCC VI VO TJ Ts TSTG TDV ASM2P20805A Description Input Power Supply Voltage Input Voltage Output Voltage Junction Temperature Max. Soldering Temperature (10 sec) Storage Temperature Static Discharge Voltage (As per JEDEC STD 22- A114-B) Max -0.5 to +4.6 -0.5 to +5.5 -0.5 to VCC+0.5 150 260 -65 to +165 2 Unit V V V °C °C °C KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. DC Electrical Characteristics over Operating Range Following Conditions Apply Unless Otherwise Specified Industrial: TA = -40°C to +85°C, VCC = 2.5V ± 0.2V Symbol VIH VIL IIH IIL IOZH IOZL VIK IODH IODL IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Outputs Pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Short Circuit Current Output HIGH Voltage VCC= Max. VCC= Max. VCC= Max. Test Conditions1 Min 1.7 -0.5 Typ2 -0.7 -35 55 -50 0.2 - Max 5.5 0.7 ±1 ±1 ±1 ±1 -1.2 -90 100 -120 0.4 0.2 Unit V V VI = 5.5V VI = GND VO = VCC VO = GND 3,4 3,4 µA VCC= Min., IIN = -18mA VCC= 2.5V, VIN = VIH or VIL, VO = 1.25V VCC= 2.5V, VIN = VIH or VIL, VO = 1.25V VCC= Max., VO = GND VCC= Min. VIN = VIH or VIL VCC= Min. VIN = VIH or VIL 3,4 V mA mA mA V -15 25 -30 IOH= -8mA IOH= -100µA IOL= 8mA IOL= 100µA 1.7 5 VCC - 0.2 - VOL Output LOW Voltage V Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 2.5V, 25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 3 of 11 June 2005 rev 0.2 Power Supply Characteristics Symbol ICCL ICCH ICCZ ∆ICC ICCD ASM2P20805A Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply 3 Current per Output Test Conditions1 VCC = Max. VIN = GND or VCC VCC = Max. VIN = VCC –0.6V VCC= Max. CL= 15pF All Outputs Toggling VCC= Max. CL= 15pF All Outputs Toggling fi = 133MHz VCC= Max. CL= 15pF All Outputs Toggling fi = 166MHz VIN = VCC VIN = GND VIN = VCC VIN = GND VIN = VCC –0.6V VIN = GND VIN = VCC VIN = GND VIN = VCC –0.6V VIN= GND Min - Typ2 0.1 35 65 Max 20 250 100 Unit µA µA µA/MHz - 100 100 115 115 125 125 mA 150 150 IC Total Power Supply 4 Current Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 2.5V, +25°C ambient. 3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 4. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 4 of 11 June 2005 rev 0.2 Switching Characteristics Over Operating Range3,4 Symbol tPLH tPHL tR tF tSK(O) tSK(P) tSK(PP) tPZL tPZH tPLZ tPHZ fMAX tPLH tPHL tR tF tSK(O) tSK(P) tSK(PP) tPZL tPZH tPLZ tPHZ fMAX ASM2P20805A Parameter Propagation Delay INA to OAn, INB to OBn Output Rise Time (Measured from 0.8V to 2V) Output Fall Time (Measured from 2V to 0.8V) Same device output pin to pin skew Pulse skew 6,9 5 Conditions1 Min2 1 - Max 3 1.5 1.5 270 270 550 5.2 5.2 133 2.5 1.25 1.25 200 270 550 5.2 5.2 166 Unit nS nS nS pS pS pS nS nS MHz nS nS nS pS pS pS nS nS MHz CL= 15pF f ≤133MHz 7 0.5 - Part to part skew Output Enable Time ¯¯ ¯¯ OEA to OAn, OEB to OBn Output Disable Time ¯¯ ¯¯ OEA to OAn, OEB to OBn Input Frequency Propagation Delay INA to OAn, INB to OBn Output Rise Time (Measured from 0.7V to 1.7V) Output Fall Time (Measured from 1.7V to 0.7V) Same device output pin to pin skew Pulse skew 6,9 5 CL= 15pF 133MHz ≤ f ≤166MHz - Part to part skew 7 Output Enable Time ¯¯ ¯¯ OEA to OAn, OEB to OBn Output Disable Time ¯¯ ¯¯ OEA to OAn, OEB to OBn Input Frequency Notes: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH and tPHL are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 5. Skew measured between all outputs under identical transitions and load conditions. 6. Skew measured is difference between propagation delay times tPHL and tPLH of same outputs under identical load conditions. 7. Part to part skew for all outputs given identical transitions and load conditions at identical VCC levels and temperature. 8. Airflow of 1m/s is recommended for frequencies above 133MHz. 9. This parameter is measured using f = 1MHz. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 5 of 11 June 2005 rev 0.2 Test Circuits and Waveforms ASM2P20805A Switch Position Test Disable Low Enable Low Disable High Enable High Test Conditions Switch 4.6V Symbol CL RT RL t R / tF Definitions: VCC = 2.5V ±0.2V 15 ZOUT of pulse generator 33 1 (0V to 2.5V or 2.5V to 0V) Unit pF Ω Ω nS GND CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 6 of 11 June 2005 rev 0.2 Test Circuits and Waveforms ASM2P20805A 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 7 of 11 June 2005 rev 0.2 Package Information 20-lead SSOP ( 150 mil ) Package ASM2P20805A Dimensions Symbol A A1 A2 D c E E1 L L1 b R1 a e Inches Min Max 0.053 0.004 …. 0.337 0.007 0.228 0.150 0.016 0.203 0.003 0° 0.069 0.010 0.059 0.344 0.012 0.244 0.157 0.035 0.325 …. 8° Millimeters Min Max 1.346 0.102 …. 8.560 0.178 5.791 3.810 0.406 0.008 0.08 0° 1.753 0.254 1.499 8.738 0.274 6.198 3.988 0.890 0.014 ….. 8° 0.010 BASIC 0.254 BASIC 0.025 BASIC 0.635 BASIC 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 8 of 11 June 2005 rev 0.2 20-lead QSOP Package ASM2P20805A Symbol A A1 b c D E e H h L S a Dimensions Inches Millimeters Min Max Min Max 0.060 0.004 0.009 0.007 0.337 0.150 0.230 0.010 0.016 0.056 0° 0.068 0.008 0.012 0.010 0.344 0.157 0.244 0.016 0.035 0.060 8° 1.52 0.10 0.23 0.18 8.56 3.81 5.84 0.25 0.41 1.42 0° 1.73 0.20 0.30 0.25 8.74 3.99 6.20 0.41 0.89 1.52 8° 0.025 BSC 0.64 BSC 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 9 of 11 June 2005 rev 0.2 Ordering Information Part Number ASM2P20805A-20-AR ASM2P20805A-20-AT ASM2P20805A-20-DR ASM2P20805A-20-DT ASM2I20805AG-20-AR ASM2I20805AG-20-AT ASM2I20805AG-20-DR ASM2I20805AG-20-DT ASM2P20805A Marking 2P20805A 2P20805A 2P20805A 2P20805A 2I20805AG 2I20805AG 2I20805AG 2I20805AG Package Type 20-Pin SSOP, TAPE & REEL 20-Pin SSOP, TUBE 20-Pin QSOP, TAPE & REEL 20-Pin QSOP, TUBE 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green Temperature Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Device Ordering Information ASM2P20805AG-20-AR R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 10 of 11 June 2005 rev 0.2 ASM2P20805A Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2P20805A Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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