ASM2P3805AHG-20-SR

June 2005 rev 0.2 3.3V CMOS Buffer Clock Driver Features Advanced CMOS Technology Guaranteed low skew < 500pS (max.) Very low duty cycle distortion < 1.0nS (max) Very low CMOS power levels TTL compatible inputs and outputs Inputs can be driven from 3.3V or 5V components Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output VCC = 3.3V ± 0.3V Available in SSOP, SOIC and QSOP Packages ASM2P3805AH Functional Description The ASM2P3805AH is a 3.3V, non-inverting clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The ASM2P3805AH offers low capacitance inputs. The ASM2P3805AH is designed for high speed clock distribution where signal quality and skew are critical. The ASM2P3805AH also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality. Block Diagram Pin Diagram VCCA OA1 1 2 3 4 5 6 7 8 9 10 20 VCCB OB1 OB2 OB3 GNDB OB4 OB5 MON OEB INB OEA INA 5 OA1 – OA5 OA2 OA3 GNDA OA4 INB OEB 5 OB1 – OB5 OA5 GNDQ OEA A S M 2 3 8 0 5 A H 19 18 17 16 15 14 13 12 11 MON INA Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. June 2005 rev 0.2 Pin Description Pin # 9,12 10,11 2,3,4,6,7 19,18,17,15,14 1 20 5 16 8 13 ASM2P3805AH Pin Names OEA, OEB ¯¯ ¯¯ INA, INB OA1-OA5 OB1-OB5 VCCA VCCB GNDA GNDB GNDQ MON Description 3-State Output Enable Inputs (Active LOW) Clock Inputs Clock Outputs Clock Outputs Power supply for Bank A Power supply for Bank B Ground for Bank A Ground for Bank B Ground Monitor Output Function Table Inputs OEA, OEB ¯¯ ¯¯ L L H H Note: H = HIGH; L = LOW; Z = High-Impedance Outputs INA, INB L H L H OAn, OBn L H Z Z MON L H L H Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter1 Input Capacitance Output Capacitance Conditions VIN= 0V VOUT = 0V Typ 4.5 5.5 Max 6 8 Unit pF pF Note: 1 This parameter is measured at characterization but not tested. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 2 of 13 June 2005 rev 0.2 Absolute Maximum Ratings1 Symbol Description VTERM2 VTERM3 VTERM4 IOUT TSTG TJ Ts TDV Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND DC Output Current Storage Temperature Junction Temperature Max. Soldering Temperature (10 sec) Static Discharge Voltage (As per JEDEC STD 22- A114-B) ASM2P3805AH Max -0.5 to +4.6 -0.5 to +7 -0.5 to VCC+0.5 -60 to +60 -65 to +150 150 260 2 Unit V V V mA °C °C °C KV Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. 2. VCC terminals. 3. Input terminals. 4. Outputs and I/O terminals. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 3 of 13 June 2005 rev 0.2 DC Electrical Characteristics over Operating Range Following Conditions Apply Unless Otherwise Specified Commercial: TA = 0°C to +70°C, VCC = 3.3V ± 0.3V; Industrial: TA = -40 0°C to +85°C, VCC = 3.3V ± 0.3V ASM2P3805AH Symbol VIH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Test Conditions1 Guaranteed Logic HIGH Level Min 2 2 Typ2 -0.7 -60 90 3 0.2 0.3 -135 150 Max 5.5 VCC+ 0.5 0.8 ±1 ±1 ±1 ±1 ±1 ±1 -1.2 -110 200 0.2 0.4 0.5 ±1 -240 - Unit V VIL IIH Input LOW Level (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Guaranteed Logic LOW Level VCC= Max. VI = 5.5V VI = VCC VCC= Max. VI = GND VI = GND VO = VCC VO = GND -0.5 -36 50 VCC–0.2 2.45 - V µA IIL IOZH IOZL VIK IODH IODL VOH Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current VCC= Max. (3-State Output Pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage µA V mA mA V VCC= Min., IIN = -18mA VCC= 3.3V, VIN = VIH or 3 VIL, VO = 1.5V VCC= 3.3V, VIN = VIH or 3 VIL, VO = 1.5V VCC= Min. VIN = VIH or VIL IOH= -0.1mA IOH= -8mA IOL= 0.1mA VOL Output LOW Voltage VCC= Min. VIN = VIH or VIL IOL= 16mA IOL= 24mA V IOFF IOS VH ICCL ICCH ICCZ Input Power Off Leakage Short Circuit Current Input Hysteresis Quiescent Power Supply Current 4 VCC= 0V, VIN = 4.5V VCC= Max., VO = GND VCC= Max. VIN = GND or VCC 3 µA mA mV -60 - - 0.1 10 µA Notes:1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC - 0.6V at rated current. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 4 of 13 June 2005 rev 0.2 Power Supply Characteristics Symbol ∆ICC ASM2P3805AH Parameter Quiescent Power Supply Current TTL Inputs HIGH Test Conditions1 VCC= Max. VIN = VCC –0.6V 3 Min - Typ2 10 Max 30 Unit µA ICCD Dynamic Power Supply Current 4 VCC= Max. Outputs Open OEA = OEB= GND ¯¯ ¯¯ Per Output Toggling 50% Duty Cycle VIN= VCC VIN= GND - 0.035 0.06 mA/ MHz VIN= VCC VCC= Max. VIN= GND Outputs Open fO= 25MHz 50% Duty Cycle OEA = OEB= VCC ¯¯ ¯¯ VIN= VCC-0.6V Mon. Output Toggling VIN= GND IC Total Power Supply Current 6 - 0.9 1.6 - 0.9 1.6 mA VCC= Max. Outputs Open fO= 50MHz 50% Duty Cycle OEA = OEB= GND Eleven Outputs Toggling VIN= VCC VIN= GND - 20 33 5 VIN= VCC-0.6V VIN= GND - 20 33 5 Notes: 1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 5 of 13 June 2005 rev 0.2 Switching Characteristics Over Operating Range – Commercial3,4 Symbol tPLH tPHL tR tF tSK(O) tSK(P) ASM2P3805AH Parameter Propagation Delay INA to OAn, INB to OBn Output Rise Time (0.8V to 2.0V) Output Fall Time (2.0V to 0.8V) Output skew: skew between outputs of all banks of same package (inputs tied together) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Output Enable Time OEA to OAn, OEB to OBn ¯¯ ¯¯ Output Disable Time OEA to OAn, OEB to OBn ¯¯ ¯¯ Conditions1 ASM2P3805A Min 1.5 2 ASM2P3805AH Min2 1.5 - Max 5.8 2 2 0.5 1 Max 5 2 2 0.5 1 Unit nS nS nS nS nS CL= 50pF RL= 500Ω - tSK(T) tPZL tPZH tPLZ tPHZ - 1.5 - 1.2 nS 1.5 1.5 6.5 5.5 1.5 1.5 6 5 nS nS Switching Characteristics Over Operating Range – Industrial3,4 Symbol tPLH tPHL tR tF tSK(O) tSK(P) Parameter Propagation Delay INA to OAn, INB to OBn Output Rise Time (0.8V to 2.0V) Output Fall Time (2.0V to 0.8V) Output skew: skew between outputs of all banks of same package (inputs tied together) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Output Enable Time OEA to OAn, OEB to OBn ¯¯ ¯¯ Output Disable Time OEA to OAn, OEB to OBn ¯¯ ¯¯ Conditions1 ASM2P3805A Min 1.5 2 ASM2P3805AH Min2 1.5 - Max 5.8 2 2 0.6 1 Max 5.2 2 2 0.6 1 Unit nS nS nS nS nS CL= 50pF RL= 500Ω - tSK(T) tPZL tPZH tPLZ tPHZ - 1.5 - 1.2 nS 1.5 1.5 6.5 5.5 1.5 1.5 6 5 nS nS Note: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 6 of 13 June 2005 rev 0.2 Test Circuits and Waveforms Switch Position Test Disable Low Enable Low Disable High Enable High Definitions: ASM2P3805AH Switch 6V GND CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 7 of 13 June 2005 rev 0.2 Package Information 20-lead SSOP ( 150 mil ) Package ASM2P3805AH Dimensions Symbol A A1 A2 D c E E1 L L1 b R1 a e Inches Min Max 0.053 0.004 …. 0.337 0.007 0.228 0.150 0.016 0.203 0.003 0° 0.069 0.010 0.059 0.344 0.012 0.244 0.157 0.035 0.325 …. 8° Millimeters Min Max 1.346 0.102 …. 8.560 0.178 5.791 3.810 0.406 0.008 0.08 0° 1.753 0.254 1.499 8.738 0.274 6.198 3.988 0.890 0.014 ….. 8° 0.010 BASIC 0.254 BASIC 0.025 BASIC 0.635 BASIC 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 8 of 13 June 2005 rev 0.2 20-lead QSOP Package ASM2P3805AH Symbol A A1 b c D E e H h L S a Dimensions Inches Millimeters Min Max Min Max 0.060 0.004 0.009 0.007 0.337 0.150 0.230 0.010 0.016 0.056 0° 0.068 0.008 0.012 0.010 0.344 0.157 0.244 0.016 0.035 0.060 8° 1.52 0.10 0.23 0.18 8.56 3.81 5.84 0.25 0.41 1.42 0° 1.73 0.20 0.30 0.25 8.74 3.99 6.20 0.41 0.89 1.52 8° 0.025 BSC 0.64 BSC 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 9 of 13 June 2005 rev 0.2 20L SOIC Package (300 mil) ASM2P3805AH Dimensions Symbol A A1 A2 D L E1 R1 b c E e a Inches Min Max 0.093 0.004 0.088 0.496 0.016 0.291 0.003 0.013 0.009 0.394 0° 0.104 0.012 0.094 0.512 0.050 0.299 …. 0.022 0.015 0.419 8° Millimeters Min Max 2.35 0.10 2.25 12.60 0.40 7.40 0.08 0.33 0.23 10.00 0° 2.65 0.30 2.40 13.00 1.27 7.60 ….. 0.56 0.38 10.65 8° 0.050 BSC 1.27 BSC 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 10 of 13 June 2005 rev 0.2 Ordering Information Part Number ASM2P3805AHG-20-AR ASM2P3805AHG-20-AT ASM2P3805AHG-20-DR ASM2P3805AHG-20-DT ASM2P3805AHG-20-SR ASM2P3805AHG-20-ST ASM2I3805AHG-20-AR ASM2I3805AHG-20-AT ASM2I3805AHG-20-DR ASM2I3805AHG-20-DT ASM2I3805AHG-20-SR ASM2I3805AHG-20-ST ASM2P3805AG-20-AR ASM2P3805AG-20-AT ASM2P3805AG-20-DR ASM2P3805AG-20-DT ASM2P3805AG-20-SR ASM2P3805AG-20-ST ASM2I3805AG-20-AR ASM2I3805AG-20-AT ASM2I3805AG-20-DR ASM2I3805AG-20-DT ASM2I3805AG-20-SR ASM2I3805AG-20-ST ASM2P3805AH Marking 2P3805AHG 2P3805AHG 2P3805AHG 2P3805AHG 2P3805AHG 2P3805AHG 2I3805AHG 2I3805AHG 2I3805AHG 2I3805AHG 2I3805AHG 2I3805AHG 2P3805AG 2P3805AG 2P3805AG 2P3805AG 2P3805AG 2P3805AG 2I3805AG 2I3805AG 2I3805AG 2I3805AG 2I3805AG 2I3805AG Package Type 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green Temperature Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 11 of 13 June 2005 rev 0.2 Device Ordering Information ASM2P3805AH ASM2P3805AHG-20-DR R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 12 of 13 June 2005 rev 0.2 ASM2P3805AH Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2P3805AH Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 13 of 13