ASM2P3807AG-20-AR

June 2005 rev 0.2 3.3V CMOS 1-TO-10 CLOCK DRIVER Features • 0.5 MICRON CMOS Technology • Guaranteed low skew < 350pS (max.) • Very low duty cycle distortion < 350pS (max.) • High speed: propagation delay < 3nS (max.) • Very low CMOS power levels • TTL compatible inputs and outputs • 1:10 fanout • Maximum output rise and fall time < 1.5nS (max.) • Low input capacitance: 4.5pF typical • Operates with 3.3V ± 0.3V Supply • Inputs can be driven from 3.3V or 5V components • Available in SSOP, SOIC, and QSOP Packages ASM2P3807AH Product Description The ASM2P3807AH 3.3V clock driver is built using advanced dual metal CMOS technology. This low skew clock driver offers 1:10 fanout. The large fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. The ASM2P3807AH offers low capacitance inputs with hysteresis for improved noise margins. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution. Block Diagram O1 O2 O3 O4 O5 IN O6 O7 O8 O9 O10 Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. June 2005 rev 0.2 Pin Configuration IN GND O1 VCC O2 GND O3 VCC O4 GND 1 2 3 4 5 6 7 8 9 10 20 VCC O10 O9 GND O8 VCC O7 GND O6 O5 ASM2P3807AH A S M 2 P 3 8 0 7 A H 19 18 17 16 15 14 13 12 11 SOIC / SSOP/ QSOP Packages TOP VIEW Pin Description Pin# 1 3,5,7,9,11,12,14,16,18,19 2,6,10,13,17 4,8,15,20 Pin Names IN O 1-O10 GND Vcc Description Clock Inputs Clock Outputs Ground Power Absolute Maximum Ratings Symbol VTERM1 VTERM2 VTERM3 TSTG IOUT device reliability. NOTES: 1. VCC terminals. 2. Input terminals. 3. Outputs and I/O terminals. Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max –0.5 to +4.6 –0.5 to +7 –0.5 to VCC+0.5 –65 to +150 –60 to +60 Unit V V V °C mA Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 2 of 19 June 2005 rev 0.2 Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN COUT ASM2P3807AH Parameter1 Input Capacitance Output Capacitance Conditions VIN= 0V VOUT = 0V Typ. 4.5 5.5 Max. 6 8 Unit pF pF Note:1. This parameter is measured at characterization but not tested. Power Supply Characteristics Symbol ∆ICC Parameter Quiescent Power Supply Current TTL Inputs HIGH Test Conditions1 VCC= Max. VIN = VCC –0.6V3 VCC= Max. Min - Typ2 10 Max 30 Unit µA ICCD Dynamic Power Supply Current4 Input toggling 50% Duty Cycle Outputs Open VCC= Max. Input toggling 6 VIN = VCC VIN = GND - 0.31 0.45 mA/ MHz IC Total Power Supply Current 50% Duty Cycle Outputs Open fi = 50MHz VIN = VCC VIN = GND - 15.5 22.8 5 mA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fi = Input Frequency All currents are in milliamps and all frequencies are in megahertz. 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 3 of 19 June 2005 rev 0.2 DC Electrical Characteristics over Operating Range Following Conditions Apply Unless Otherwise Specified Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V ASM2P3807AH Symbol VIH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Input LOW Level (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedence Output Current (3-State Output Pins) Clamp Diode Voltage Output HIGH Current Test Conditions1 Guaranteed Logic HIGH Level Min 2 2 Typ -0.7 -60 Max 5.5 VCC+ 0.5 0.8 ±1 ±1 ±1 ±1 ±1 ±1 -1.2 -110 Unit V VIL Guaranteed Logic LOW Level VCC= Max VI = 5.5V VI = VCC VCC= Max VI = GND VI = GND VCC= Max VO = VCC VO = GND VCC= Min., IIN = –18mA VCC= 3.3V, VIN = VIH or VIL, VO = 1.5V3 VCC= 3.3V, VIN = VIH or VIL, VO = 1.5V3 VCC= Min. VIN = VIH or VIL IOH= –0.1mA IOH= –8mA IOL= 0.1mA IOL= 16mA IOL= 24mA -0.5 -36 V IIH µA IIL IOZH IOZL VIK IODH µA V mA IODL VOH Output LOW Current Output HIGH Voltage 50 VCC-0.2 2.4 5 90 3 0.2 0.3 -135 150 0.1 200 0.2 0.4 0.5 ±1 -240 10 mA V VOL Output LOW Voltage VCC= Min VIN = VIH or VIL V IOFF IOS VH ICCL ICCH ICCZ Input Power Off Leakage Short Circuit Current Input Hysteresis Quiescent Power Supply Current 4 VCC= 0V, VIN = 4.5V VCC= Max., VO = GND VCC= Max. VIN = GND or VCC 3 µA mA mV µA -60 - - NOTES: 1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = Vcc - 0.6V at rated current. 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 4 of 19 June 2005 rev 0.2 Switching Characteristics Over Operating Range – Commercial3,4 Symbol tPLH tPHL tR tF ASM2P3807AH Parameter Propagation Delay Output Rise Time Output Fall Time Output skew: skew between outputs of same package (same transition) Pulse skew: skew between opposite transitions of same output (|tPHL – tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Conditions1 50Ω to VCC/2 CL= 10pF (See figure 1) or 10Ω AC termination, CL= 50pF (See figure 2) f≤ 100MHz Outputs connected in groups of two ASM2P3807A Min2 Max 1.5 3.5 1.5 1.5 ASM2P3807AH Min2 Max 1.5 3 1.5 1.5 Unit nS nS nS tSK(O) - 0.5 - 0.35 nS tSK(P) - 0.5 - 0.35 nS tSK(T) - 0.9 - 0.65 nS 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 5 of 19 June 2005 rev 0.2 Symbol tPLH tPHL tR tF tSK(O) tSK(P) ASM2P3807AH Parameter Propagation Delay Output Rise Time Output Fall Time Output skew: skew between outputs of same package (same transition) Pulse skew: skew between opposite transitions of same output (|tPHL – tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Conditions1 CL= 30pF f≤ 67MHz (See figure 3) ASM2P3807A Min2 Max 1.5 4.5 1.5 1.5 0.6 0.6 ASM2P3807AH Min2 Max 1.5 4 1.5 1.5 0.45 0.45 Unit nS nS nS nS nS tSK(T) - 1 - 0.75 nS Symbol tPLH tPHL tR tF tSK(O) tSK(P) Parameter Propagation Delay Output Rise Time Output Fall Time Output skew: skew between outputs of same package (same transition) Pulse skew: skew between opposite transitions of same output (|tPHL – tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Conditions1 CL= 50pF f≤ 40MHz (See figure 4) ASM2P3807A Min 1.5 2 ASM2P3807AH Min2 1.5 - Max 4.8 1.5 1.5 0.5 0.5 Max 4.3 1.5 1.5 0.35 0.35 Unit nS nS nS nS nS tSK(T) - 1 - 0.75 nS NOTES:1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delays limits do not imply skew. 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 6 of 19 June 2005 rev 0.2 Switching Characteristics Over Operating Range - Industrial3,4 ASM2P3807A Symbol Parameter Conditions1 Min2 Max tPLH tPHL tR tF Propagation Delay Output Rise Time Output Fall Time Output skew: skew between outputs of same package (same transition) Pulse skew: skew between opposite transitions of same output (|tPHL – tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade 50Ω to VCC/2 CL= 10pF (See figure 1) or 50Ω AC termination, CL= 10pF (See figure 2) f≤ 100MHz Outputs connected in groups of two 0.6 0.6 1.5 3.5 1.5 1.5 ASM2P3807AH ASM2P3807AH Min2 Max 1.5 3 1.5 1.5 Unit nS nS nS tSK(O) 0.45 nS tSK(P) 0.45 nS tSK(T) - 0.9 - 0.65 nS Symbol tPLH tPHL tR tF tSK(O) Parameter Propagation Delay Output Rise Time Output Fall Time Output skew: skew between outputs of same package (same transition) Pulse skew: skew between opposite transitions of same output (|tPHL - tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Conditions1 CL= 30pF f≤ 67MHz (See figure 3) ASM2P3807A Min2 Max 1.5 4.5 1.5 1.5 ASM2P3807AH Min2 Max 1.5 4 1.5 1.5 Unit nS nS nS - 0.6 - 0.45 nS tSK(P) - 0.6 - 0.45 nS tSK(T) - 1 - 0.75 nS 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 7 of 19 June 2005 rev 0.2 Symbol tPLH tPHL tR tF tSK(O) Output Rise Time Output Fall Time Output skew: skew between outputs of same package (same transition) Pulse skew: skew between opposite transitions of same output (|tPHL - tPLH|) ASM2P3807AH Parameter Propagation Delay Conditions1 CL= 50pF f≤ 40MHz (See figure 4) ASM2P3807A Min2 Max 1.5 4.8 1.5 1.5 ASM2P3807AH Min2 Max 1.5 4.3 1.5 1.5 Unit nS nS nS - 0.6 - 0.45 nS tSK(P) - 0.6 - 0.45 nS tSK(T) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade - 1 - 0.75 nS NOTES:1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min and Max limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 8 of 19 June 2005 rev 0.2 TEST CIRCUITS VCC VCC ASM2P3807AH 100Ω VN PULSE GENERATOR RT O.U.T 10pF 100Ω VOUT Figure 1. ZO = 50Ω to VCC/2, CL = 10pF VCC VCC 100Ω VN PULSE GENERATOR RT O.U.T 50Ω 220pF 10pF VOUT Figure 2. ZO = 50Ω AC Termination, CL = 10pF The capacitor value for ac termination is determined by the operating frequency. For very low frequencies a higher capacitor value should be selected. VCC VN PULSE GENERATOR RT O.U.T VOUT 30pF CL Figure 3. CL = 30pF Circuit 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 9 of 19 June 2005 rev 0.2 VCC ASM2P3807AH VN PULSE GENERATOR RT O.U.T VOUT 50pF CL Figure 3. CL = 50pF Circuit 6V VCC 500Ω VN PULSE GENERATOR RT O.U.T 50pF CL 500Ω VOUT GND Figure 5. Enable and Disable Time Circuit 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 10 of 19 June 2005 rev 0.2 Enable and Disable Time Switch Position Test Disable LOW Enable LOW Disable HIGH Enable HIGH DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. ASM2P3807AH Switch 6V GND Test Waveforms 3V 1.5V INPUT tPLH tPHL OV VOH 2.0 V OUTPUT tR tF 0.8 V 1.25 V VOL Package Delay 1.5V INPUT tPLH tPLH VOH 1.5 V OUTPUT 3V tSK(p) =[ tPHL – tPLH ] VOL OV Pulse Skew - tSK(P) 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 11 of 19 June 2005 rev 0.2 3V 1.5V INPUT tPLH 1 tPLHL OV 1 ASM2P3807AH VOH 1.5 V OUTPUT 2 tSK(O tSK(0) VOL VOH 1.5 V OUTPUT 1 tPLH2 tPHL2 tSK(O) =[ tPLH2 – tPLH 1 ] or [tPHL2 - tPHL1 ] VOL Output Skew - tSK(O) 3V 1.5V INPUT tPLH 1 tPLHL OV 1 VOH 1.5 V PACKAGE 1 OUTPUT tSK(t) tSK(t) VOL VOH 1.5 V PACKAGE 2 OUTPUT tPLH2 tPHL2 VOL tSK(t) =[ tPLH2 – tPLH 1 ] or [tPHL2 - tPHL1 ] Package Skew - tSK(T) Package 1 and Package 2 are same device type and speed grade 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 12 of 19 June 2005 rev 0.2 ENABLE DISABLE ASM2P3807AH 3V CONTROL INPUT t PLZ SWITCH CLOSED t PLZ OUTPUT NORMALLY HIGH t PLZ 3.5V 1.5V 0.3V t PLZ VOL 3.5V 1.5V 0V OUTPUT NORMALLY LOW SWITCH OPEN 1.5V 0V 0.3V VOH 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: f ≤1.0MHz; tF ≤2.5ns; tR ≤2.5ns 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 13 of 19 June 2005 rev 0.2 Package Information 20-lead SSOP ( 150 mil ) Package ASM2P3807AH Dimensions Symbol A A1 A2 D c E E1 L L1 b R1 a e Inches Min Max 0.053 0.004 …. 0.337 0.007 0.228 0.150 0.016 0.203 0.003 0° 0.069 0.010 0.059 0.344 0.012 0.244 0.157 0.035 0.325 …. 8° Millimeters Min Max 1.346 0.102 …. 8.560 0.178 5.791 3.810 0.406 0.008 0.08 0° 1.753 0.254 1.499 8.738 0.274 6.198 3.988 0.890 0.014 ….. 8° 0.010 BASIC 0.254 BASIC 0.025 BASIC 0.635 BASIC 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 14 of 19 June 2005 rev 0.2 ASM2P3807AH 20L SOIC Package (300 mil) Dimensions Symbol A A1 A2 D L E1 R1 b c E e a Inches Min Max 0.093 0.004 0.088 0.496 0.016 0.291 0.003 0.013 0.009 0.394 0° 0.104 0.012 0.094 0.512 0.050 0.299 …. 0.022 0.015 0.419 8° Millimeters Min Max 2.35 0.10 2.25 12.60 0.40 7.40 0.08 0.33 0.23 10.00 0° 2.65 0.30 2.40 13.00 1.27 7.60 ….. 0.56 0.38 10.65 8° 0.050 BSC 1.27 BSC 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 15 of 19 June 2005 rev 0.2 ASM2P3807AH 20-lead QSOP Package Dimensions Symbol A A1 b c D E e H h L S a Inches Min Max 0.060 0.004 0.009 0.007 0.337 0.150 0.230 0.010 0.016 0.056 0° 0.068 0.008 0.012 0.010 0.344 0.157 0.244 0.016 0.035 0.060 8° Millimeters Min Max 1.52 0.10 0.23 0.18 8.56 3.81 5.84 0.25 0.41 1.42 0° 1.73 0.20 0.30 0.25 8.74 3.99 6.20 0.41 0.89 1.52 8° 0.025 BSC 0.64 BSC 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 16 of 19 June 2005 rev 0.2 Ordering Information Part Number ASM2P3807AHG-20-AR ASM2P3807AHG-20-AT ASM2P3807AHG-20-DR ASM2P3807AHG-20-DT ASM2P3807AHG-20-SR ASM2P3807AHG-20-ST ASM2I3807AHG-20-AR ASM2I3807AHG-20-AT ASM2I3807AHG-20-DR ASM2I3807AHG-20-DT ASM2I3807AHG-20-SR ASM2I3807AHG-20-ST ASM2P3807AG-20-AR ASM2P3807AG-20-AT ASM2P3807AG-20-DR ASM2P3807AG-20-DT ASM2P3807AG-20-SR ASM2P3807AG-20-ST ASM2I3807AG-20-AR ASM2I3807AG-20-AT ASM2I3807AG-20-DR ASM2I3807AG-20-DT ASM2I3807AG-20-SR ASM2I3807AG-20-ST ASM2P3807AH Marking 2P3807AHG 2P3807AHG 2P3807AHG 2P3807AHG 2P3807AHG 2P3807AHG 2I3807AHG 2I3807AHG 2I3807AHG 2I3807AHG 2I3807AHG 2I3807AHG 2P3807AG 2P3807AG 2P3807AG 2P3807AG 2P3807AG 2P3807AG 2I3807AG 2I3807AG 2I3807AG 2I3807AG 2I3807AG 2I3807AG Package Type 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Pb Free 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green Temperature Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 17 of 19 June 2005 rev 0.2 Device Ordering Information ASM2P3807AH ASM2P3807AHG-20-AT R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent Nos 5,488,627 and 5,631,920. 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 18 of 19 June 2005 rev 0.2 ASM2P3807AH Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Advance Information Part Number: ASM2P3807AH Document Version: v0.1 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3V CMOS 1-TO-10 CLOCK DRIVER Notice: The information in this document is subject to change without notice. 19 of 19