ASM5I2304AF-1-08-SR

September 2005 rev 1.4 3.3V Zero Delay Buffer Features Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304A Configurations Table”. Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. Less than 200pS Cycle-to-Cycle jitter (-1, -1H, -2, -2H). Available in space saving, 8 pin 150-mil SOIC packages. 3.3V operation. Advanced 0.35< CMOS technology. Industrial temperature available. ASM5P2304A the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250pS, and the output-to-output skew is guaranteed to be less than 200pS. The ASM5P2304A has two banks of two outputs each. Multiple ASM5P2304A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500pS. The ASM5P2304A is available in two different configurations (Refer “ASM5P2304A Configurations Table). The ASM5P2304A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P2304A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. The ASM5P2304A-2 allows the user to obtain REF and 1/2X or 2X frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. Functional Description ASM5P2304A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in 8 pin package. The part has an on-chip PLL which locks to an input clock presented on Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 Alliance Semiconductor 2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. September 2005 rev 1.4 ASM5P2304A Configurations Device ASM5P2304A-1 ASM5P2304A-1H ASM5P2304A-2 ASM5P2304A-2 ASM5P2304A-2H ASM5P2304A-2H ASM5P2304A Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A Frequency Reference Reference Reference 2 X Reference Reference 2 X Reference Bank B Frequency Reference Reference Reference /2 Reference Reference/2 Reference Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded. 1500 1000 REF-Input to CLKA / CLKB Delay (pS) 500 0 -30 -500 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins To close the feedback loop of the ASM5P2304A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 15 September 2005 rev 1.4 Pin Configuration REF 1 CLKA1 2 CLKA2 3 GND 4 ASM5P2304A 8 FBK 7 VDD 6 CLKB2 5 CLKB1 ASM5P2304A Pin Description for ASM5P2304A Pin # 1 2 3 4 5 6 7 8 Pin Name REF 1 Description Input reference frequency, 5V tolerant input CLKA1 CLKA2 GND CLKB1 CLKB2 VDD FBK 2 Buffered clock output, bank A Buffered clock output, bank A Ground 2 2 Buffered clock output, bank B Buffered clock output, bank B 3.3V supply PLL feedback input 2 Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 15 September 2005 rev 1.4 Absolute Maximum Ratings ASM5P2304A Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 Unit V V V °C °C °C 2000 V Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P2304A Commercial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Description Min 3.0 0 Max 3.6 70 30 15 7 Unit V °C pF pF pF Operating Temperature (Ambient Temperature) Load Capacitance, from 15MHz to 100MHz Load Capacitance, from 100MHz to 133MHz Input Capacitance 3 Note: 3. Applies to both Ref Clock and FBK. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 15 September 2005 rev 1.4 Electrical Characteristics for ASM5P2304A Commercial Temperature Devices ASM5P2304A Parameter VIL VIH IIL IIH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Test Conditions Min Max 0.8 Unit V V 2.0 VIN = 0V VIN = VDD IOL = 8mA (-1, -2) IOH = 12mA (-1H, -2H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -2H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 50.0 100.0