ASM5I23S04A-2-08-SR

August 2004 rev 2.0 3.3 V ‘SpreadTrak’ Zero Delay Buffer Features  Zero input - output propagation delay, adjustable by capacitive load on FBK input.  Multiple configurations - Refer “ASM5P23S04A Configurations Table”.  Input frequency range: 10MHz to 133MHz  Multiple low-skew outputs.  Output-output skew less than 200 ps.  Device-device skew less than 500 ps.  Two banks of four outputs.  Less than 200 ps cycle-to-cycle jitter  Available in space saving, 8-pin 150-mil SOIC packages.  3.3V operation.  Advanced 0.35µ CMOS technology.  Industrial temperature available.  ‘SpreadTrak’ Functional Description ASM5P23S04A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in a 8-pin package. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to ASMP5P23S04A FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250ps, and the output-to-output skew is guaranteed to be less than 200ps. The ASM5P23S04A has two banks of two outputs each. Multiple ASM5P23S04A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500ps. The ASM5P23S04A (Refer is available in two different configurations “ASM5P23S04A Configurations Table). The ASM5P23S04A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P23S04A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. The ASM5P23S04A-2 allows the user to obtain Ref, 1/2 X and 2X frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. The ASM5P23S04A-5H is a high-drive version with REF/2 on both banks Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra D ivider ( - 2) CLKB1 CLKB2 Alliance Semiconductor 2575, Augustine Drive  Santa Clara, CA  Tel: 408.855.4900  Fax: 408.855.4999  www.alsc.com Notice: The information in this document is subject to change without notice. `` August 2004 rev 2.0 ASM5P23S04A Configurations Device ASM5P23S04A-1 ASM5P23S04A-1H ASM5P23S04A-2 ASM5P23S04A-2 ASM5P23S04A-5H ‘SpreadTrak’ Many systems being designed now utilize a technology called Spread Frequency Timing Generation. ASM3P23S04A is designed so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded. 1500 ASM5P23S04A Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference Reference /2 Bank B Frequency Reference Reference Reference /2 Reference Reference /2 delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew which may cause problems in the systems requiring synchronization. 1000 REF-Input to C LKA /CLK B Delay ( ps) 500 0 -30 -500 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins 3.3 ‘SpreadTrak’ Zero Delay Buffer Notice: 2 of 13 The information in this document is subject to change without notice. `` August 2004 rev 2.0 To close the feedback loop of the ASM5P23S04A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph. Pin Configuration REF CLKA1 CLKA2 GND 1 2 3 4 8 FBK VDD CLKB2 ASM5P23S04A For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. ASM5P23S04A 7 6 5 CLKB1 Pin Description for ASM5P23S04A Pin # 1 2 3 4 5 6 7 8 Pin Name REF1 CLKA12 CLKA22 GND CLKB12 CLKB2 2 VDD FBK Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A Ground Buffered clock output, bank B Buffered clock output, bank B 3.3V supply PLL feedback input Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3.3 ‘SpreadTrak’ Zero Delay Buffer Notice: 3 of 13 The information in this document is subject to change without notice. `` August 2004 rev 2.0 Absolute Maximum Ratings Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 >2000 ASM5P23S04A Unit V V V °C °C °C V Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P23S04A Commercial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Description Min 3.0 0 Max 3.6 70 30 15 7 Unit V °C Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance3 pF pF pF Note: 3. Applies to both Ref Clock and FBK. 3.3 ‘SpreadTrak’ Zero Delay Buffer Notice: 4 of 13 The information in this document is subject to change without notice. `` August 2004 rev 2.0 Electrical Characteristics for ASM5P23S04A Commercial Temperature Devices ASM5P23S04A Parameter VIL VIH IIL IIH VOL Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage 4 Test Conditions Min Max 0.8 Unit V V 2.0 VIN = 0V VIN = VDD IOL = 8mA (-1, -2) IOH = 12mA (-1H, -5H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -5H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 2.4 50.0 100.0 µA µA 0.4 V VOH Output HIGH Voltage 4 V TBD TBD mA IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) TBD TBD Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 5. REF Input Vth = ~ VDD/2 3.3 ‘SpreadTrak’ Zero Delay Buffer Notice: 5 of 13 The information in this document is subject to change without notice. `` August 2004 rev 2.0 Switching Characteristics for ASM5P23S04A Commercial Temperature Devices Parameter t1 t1 t1 Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) Duty Cycle = (t2 / t1) * 100 (-1, -2,-1H, -5H) t3 Output Rise Time (-1, -2) Output Rise Time (-1, -2) Output Rise Time (-1H, -5H) Output Fall Time (-1, -2) Output Fall Time (-1, -2) Output Fall Time (-1H, -5H) 4 4 4 4 ASM5P23S04A Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices 15-pF load, -1, -2 devices Measured at 1.4V, FOUT = 66.66 MHz 30-pF load Measured at 1.4V, FOUT =