ASM5I9351

July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Features Output frequency range: 25 MHz to 200 MHz Input frequency range: 25 MHz to 200 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs ± 2.5% max Output duty cycle variation Nine Clock outputs: Drive up to 18 clock lines Two reference clock inputs: LVPECL or LVCMOS 150-ps max output-output skew Phase-locked loop (PLL) bypass mode ‘SpreadTrak’ Output enable/disable Pin-compatible with MPC9351 and CY29351. Industrial temperature range: –40°C to +85°C 32-pin 1.0mm TQFP & LQFP Package. ASM5I9351 The ASM5I9351 features LVPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table.2. These dividers allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see the Table 1. When PLL_EN is LOW, PLL is bypassed and the reference Functional Description The ASM5I9351 is a low voltage high performance clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. 200MHz PLL-based zero delay buffer designed for high speed clock distribution applications. Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. July 2005 rev 0.2 Block Diagram SELA PLL_EN REF_SEL TCLK PECL_CLK ASM5I9351 Phase Detector VCO 200-500MHz LPF +2/ +4 QA FB_IN +4/ +8 QB QC0 QC1 QD0 QD1 QD2 QD3 QD4 SELB +4/ +8 SELC +4/ +8 OE# SELD REF_SEL VDDQB TCLK Pin Configuration PLL_EN VSS QA 32 31 30 29 28 27 26 25 AVDD FB_IN SELA SELB SELC SELD AVSS PECL_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 QC0 VDDQC QC1 VSS QD0 VDDQD QD1 VSS ASM5I9351 VSS 21 20 19 18 17 QD2 VDD PECL_CLK# 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. VDDQD VSS OE# QD4 QD3 QB 2 of 13 July 2005 rev 0.2 Pin Configuration1 Pin # Pin Name 8 9 30 28 26 22, 24 12, 14, 16, 18, 20 2 10 31 32 3, 4, 5, 6 27 23 15, 19 1 11 7 13, 17, 21, 25, 29 PECL_CLK PECL_CLK# TCLK QA QB QC(1:0) QD(4:0) FB_IN OE# PLL_EN REF_SEL SEL(A:D) VDDQB VDDQC VDDQD AVDD VDD AVSS VSS ASM5I9351 I/O I, PU I, PU/PD I, PD O O O O I, PD I, PD I, PU I, PD I, PD Supply Supply Supply Supply Supply Supply Supply Type Analog Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD Ground Ground Description LVPECL reference clock input. LVPECL reference clock input. Weak pull-up to VDD/2. LVCMOS/LVTTL reference clock input Clock output bank A Clock output bank B Clock output bank C Clock output bank D Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Output enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Reference select input. See Table 2. Frequency select input, Bank (A:D). See Table 2. 2.5V or 3.3V Power supply for bank B output clock2,3 2.5V or 3.3V Power supply for bank C output clocks2,3 2.5V or 3.3V Power supply for bank D output clocks2,3 2.5V or 3.3V Power supply for PLL2,3 2.5V or 3.3V Power supply for core, inputs, and bank A output clock2,3 Analog ground Common ground Note: 1 PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin ( 100 MHz 0.6V to 1.8V TCLK to FB_IN PCLK to FB_IN % mV V nS MHz DC tr, tf t(φ) tsk(O) tPLZ, HZ tPZL, ZH BW Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (–3dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time % nS pS pS nS nS MHz ÷2 Feedback ÷4 Feedback ÷8 Feedback Same frequency Multiple frequencies Same frequency Multiple frequencies - tJIT(CC) tJIT(PER) tJIT(φ) tLOCK pS pS pS mS Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ). 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 13 July 2005 rev 0.2 AC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)1 Parameter fVCO ASM5I9351 Description VCO Frequency Condition ÷2 Feedback ÷4 Feedback Min 200 100 50 25 0 25 Typ 2.2 0.85 0.6 175 - Max 500 200 125 62.5 200 75 1000 VDD– 0.9 1.0 200 125 62.5 52.5 55 1.0 100 100 150 350 10 10 150 250 100 150 1 Unit MHz fin Input Frequency ÷8 Feedback Bypass mode (PLL_EN = 0) LVPECL LVPECL 0.8V to 2.0V ÷2 Output ÷4 Output ÷8 Output fMAX < 100 MHz fMAX > 100 MHz 0.8V to 2.4V TCLK to FB_IN, same VDD PCLK to FB_IN, same VDD Banks at same voltage Banks at different voltages MHz frefDC VPP VCMR tr, tf fMAX Input Duty Cycle Peak-Peak Input Voltage Common Mode Range2 TCLK Input Rise/FallTime Maximum Output Frequency % mV V nS MHz 500 1.2 100 50 25 47.5 45 0.1 –100 –100 - DC tr, tf t(φ) tsk(O) tsk(B) tPLZ, HZ tPZL, ZH BW Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (–3dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time % nS pS pS pS nS nS MHz ÷2 Feedback ÷4 Feedback ÷8 Feedback Same frequency Multiple frequencies Same frequency Multiple frequencies I/O same VDD - tJIT(CC) tJIT(PER) tJIT(φ) tLOCK pS pS pS mS Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ). 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 13 July 2005 rev 0.2 ASM5I9351 Zo = 50 ohm Pulse Generator Z = 50 ohm RT = 50 ohm Zo = 50 ohm RT = 50 ohm VTT VTT Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V / 2.5V Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 2. PECL_CLK AC Test Reference for VDD = 3.3V / 2.5V 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 13 July 2005 rev 0.2 ASM5I9351 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 13 July 2005 rev 0.2 Package Diagram 32-lead TQFP Package ASM5I9351 SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e Inches Min Max …. 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7° 0.03937 REF 1.00 REF 0.031 BASE 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 13 July 2005 rev 0.2 32-lead LQFP Package ASM5I9351 SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a Inches Min Max …. 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7° 0.03937 REF 1.00 REF 0.031 BASE 0.8 BASE 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 13 July 2005 rev 0.2 Ordering Information Part Number ASM5I9351-32-ET ASM5I9351-32-LT ASM5I9351G-32-ET ASM5I9351G-32-LT ASM5I9351 Marking ASM5I9351 ASM5I9351 ASM5I9351G ASM5I9351G Package Type 32-pin TQFP 32-pin LQFP –Tape and Reel 32-pin TQFP, Green 32-pin LQFP –Tape and Reel, Green Temperature Industrial Industrial Industrial Industrial Device Ordering Information ASM 5I9351 F-32-LT R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 13 July 2005 rev 0.2 ASM5I9351 Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM5I9351 Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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