ASM5I9658-32-LR

July 2005 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator Features 1:10 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply Generates clock signals up to 250MHz Maximum output skew of 120pS Differential LVPECL reference clock input External PLL feedback Drives up to 20 clock lines 32 lead LQFP packaging Pin and function compatible to the MPC958 and MPC9658 ASM5I9658 and the reference clock frequency determines the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the ASM5I9658 is running at either 2x or 4x of the reference clock frequency. The ASM5I9658 has a differential LVPECL reference input along with an external feedback input. The ASM5I9658 is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The ASM5I9658 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50Ω transmission lines. For series terminated transmission lines, each of the ASM5I9658 outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP & TQFP Packages. Functional Description The ASM5I9658 is a 3.3V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 250MHz and output skews less than 120pS the device meets the needs of the most demanding clock applications. The ASM5I9658 is specified for the temperature range of 0°C to +70°C. The ASM5I9658 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the ASM5I9658 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125MHz or 100 to 250MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) Alliance Semiconductor 2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. July 2005 rev 0.2 Block Diagram ASM5I9658 Q0 VCC 2-25k PCLK PCLK VCC 25k FB_IN VCC 3-25k 0 & ÷1 ÷2 0 1 ÷2 Q1 0 1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 QFB Ref VCO PLL 1 200-500 MHz FB PLL_EN VCO_SEL BYPASS MR/OE 25k Figure 1. ASM5I9658 Logic Diagram GND GND 16 15 14 VCC Q2 Q3 VCC Q4 Q5 Pin Configuration 24 23 22 21 20 19 18 17 GND Q1 VCC Q0 GND QFB VCC VCO_SEL 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 Q6 VCC Q7 GND Q8 VCC Q9 GND ASM5I9658 13 12 11 10 9 BYPASS VCC_PLL PLL_EN PCLK FB_IN PCLK Figure 2. ASM5I9658 32-Lead Package Pinout (Top View) 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. MR/OE GND 2 of 14 July 2005 rev 0.2 Table 1: Pin Configuration Pin # 6 7 2 32 3 4 5 28,26,24, 22,20,18, 16,14,12, 10 30 8,9,13,17 21,25,29 1 11,15,19, 23,27,31 ASM5I9658 Pin Name PCLK, PCLK FB_IN VCO_SEL BYPASS PLL_EN MR/OE Q0-9 QFB GND VCC_PLL VCC I/O Input Input Input Input Input Input Output Output Supply Supply Supply Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC Function LVPECL reference clock signal PLL feedback signal input, connect to QFB Operating frequency range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Clock output for PLL feedback, connect to FB_IN Negative power supply (GND) PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 2: FUNCTION TABLE Control PLL_EN Default 1 0 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. ASM59658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. ASM59658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO ÷ 1 (High frequency range). fREF = fQ0-9 =2. fVCO 1 Selects the VCO output1 BYPASS 1 Selects the output dividers. VCO_SEL 1 VCO ÷ 2 (Low frequency range). fREF =fQ0-9 =4.fVCO Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK). MR/OE 0 Outputs enabled (active) Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 3 of 14 July 2005 rev 0.2 Table 3: ABSOLUTE MAXIMUM RATINGS1 Symbol VCC VIN VOUT IIN IOUT TS ASM5I9658 Characteristics Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 ±20 ±50 Unit V V V mA mA °C Condition -65 125 Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Table 4: GENERAL SPECIFICATIONS Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance LQFP 32 Thermal resistance junction to ambient JESD 51-3, single layer test board Min 200 2000 200 Typ VCC÷2 Max Unit V V V mA Condition 10 4.0 83.1 73.3 68.9 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 pF pF °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Per output Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 θJA JESD 51-6, 2S2P multilayer test board 63.8 57.4 59.0 54.4 52.5 50.4 47.8 θJC LQFP 32 Thermal resistance junction to case 23.0 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 4 of 14 July 2005 rev 0.2 Table 5: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICC_PLL ICCQ ASM5I9658 Characteristics Input high voltage Input low voltage Peak-to-peak input voltage (PCLK) Common Mode Range (PCLK) Output High Voltage Output Low Voltage3 Output impedance Input Current 4 Min 2.0 250 1.0 2.4 Typ Max VCC +0.3 0.8 Unit V V mV Condition LVCMOS LVCMOS LVPECL LVPECL IOH=-24 mA2 IOL=24mA IOL=12mA VIN=VCC or GND VCC_PLL Pin All VCC Pins VCC-0.6 0.55 0.30 14 -17 ±200 12 13 15 15 V V V V Ω µA mA mA Maximum PLL Supply Current Maximum Quiescent Supply Current Note: 1. VCMR (DC) is the cross point of the differential input signal. Functional operation is obtained ,when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2.The ASM3P9658 is capable of driving 50Ωtransmission lines on the incident edge. Each output drives one 50Ωparallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ωseries terminated transmission lines. 3.The ASM5I9658 output levels are compatible to the MPC958 output levels. 4.Inputs have pull-down or pull-up resistors affecting the input current. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 5 of 14 July 2005 rev 0.2 Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)1 Symbol Characteristics fREF fVCO fMAX VPP VCMR6 tPW,MIN t(Ø) tPD tsk(O) DC tR , tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT(Ø) BW tLOCK Input reference frequency PLL mode, external feedback ÷2 feedback2 ÷4 feedback3 ASM5I9658 Min 100 50 0 200 100 50 500 1.2 2 -70 -125 1.0 (T÷2)400 0.1 Typ Max 250 125 250 500 250 125 1000 VCC-0.9 Unit MHz MHz MHz MHz MHz MHz mV V nS Condition PLL locked PLL locked Input reference frequency in PLL bypass mode4 VCO operating frequency range5 Output Frequency ÷2 feedback ÷4 feedback4 3 PLL locked PLL locked LVPECL LEPVCL Peak-to-peak input voltage PCLK Common Mode Range PCLK Input Reference Pulse Width7 Propagation Delay (static phase offset) 8 PCLK to FB_IN fREF=100MHz any frequency Propagation Delay PLL and divider bypass, PCLK to Q0-9 Output-to-output Skew9 Output duty cycle10 Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter fVCO=500 MHz and ÷ 2 feedback, RMS (1σ)11 fVCO=500 MHz and ÷ 4 feedback, RMS (1σ) 12 ÷2 feedback8 PLL closed loop bandwidth  PLL mode, external feedback ÷4 feedback9 Maximum PLL Lock Time +80 +125 4.0 120 (T÷2)+4 00 1.0 7.0 6.0 80 80 5.5 6.5 6-20 2-8 10 pS pS nS pS pS nS nS nS pS pS pS pS MHz MHz mS PLL locked T÷2 0.55 to 2.4V Note:1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. ÷2 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0. 3.÷4 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0. 4.In bypass mode, the ASM3P9658 divides the input reference clock. 5.The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB. 6.VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(Ø). 7.Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF. 100% and DCREF,MAX = 100% - DCREF,MIN. 8.Valid for fREF=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t(Ø) [pS] = 50 pS ± (1÷(120 . fREF)). 9.See application section for part-to-part skew calculation in PLL zero-delay mode. 10.Output duty cycle is DC = (0.5 ± 400 pS. fOUT) V 100%. E.g. the DC range at fOUT=100MHz is 46%