ASM5I9772A-52-ET

June 2005 rev 0.3 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Features Output frequency range: 8.33 MHz to 200 MHz Input frequency range: 6.25 MHz to 125 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs ±2% max Output duty cycle variation 12 clock outputs: drive up to 24 clock lines One feedback output Three reference clock inputs: crystal or LVCMOS 300pS max output-output skew Phase-locked loop (PLL) bypass mode ‘SpreadTrak’ Output enable/disable Pin-compatible with CY29772, MPC9772 and MPC972 Industrial temperature range: –40°C to +85°C 52 pin 1.0 mm TQFP package ASM5I9772A The ASM5I9772A features one on-chip crystal oscillator and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL(A:C) settings, see Functional Table. These dividers allow output to input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible output can drive 50Ω series or parallel-terminated transmission lines. For seriesterminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of 1:24. The PLL is ensured stable given that the VCO is configured to run between 200 MHz and 500 MHz. This allows a wide range of output frequencies from 8 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. RoHS Compliance Functional Description The ASM5I9772A is a low-voltage high-performance 200 MHz PLL-based zero delay buffer, designed for highspeed clock-distribution applications. Block Diagram XIN XOUT VCO_SEL PLL_EN REF_SEL 0 TCLK0 TCLK1 TCLK_SEL FB_IN 0 1 LPF D Q Sync Frz QB0 QB1 QB2 QB3 MR#/OE Power-On Reset /4,/6,/8,/12 /4,/6,/8,/10 SELA(0,1) SELB(0,1) SELC(0,1) 2 2 2 /2/4,/6,/8 0 /4,/6,/8,/10 /2 Sync Pulse FB_SEL(0,1) SCLK SDATA Output Disable Circuitry 2 Data Generator D 12 Q Sync Frz SYNC 1 D Q D Q Sync Frz QC2 QC3 FB_OUT D Q Sync Frz QC0 QC1 Phase Detector VCO 1 D Q Sync Frz QA0 QA1 QA2 QA3 FB_SEL2 Sync Frz INV_CLK Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. June 2005 rev 0.3 Pin Configuration ASM5I9772A VCO_SEL VDDQA VDDQA SELB0 SELA0 AVSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 XIN XOUT AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 SELA1 QA1 QA2 QA3 SELB1 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QA0 VSS VSS QB0 VDDQB QB1 VSS QB2 VDDQB QB3 FB_IN VSS FB_OUT VDD FB_SEL0 ASM5I9772A 14 15 16 17 18 19 20 21 22 23 24 25 26 VDDQC VDDQC SYNC 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. FB_SEL1 QC3 QC2 QC1 SELC1 SELC0 QC0 VSS INV_CLK VSS 2 of 15 June 2005 rev 0.3 Pin Description1 Pin 11 12 9 10 44, 46, 48, 50 32, 34, 36, 38 16, 18, 21, 23 29 31 25 6 2 8 7 52 14 5, 26, 27 42, 43 40, 41 19, 20 3 4 45, 49 33, 37 22, 17 13 28 1 15, 24, 30, 35, 39, 47, 51 ASM5I9772A Name XIN XOUT TCLK0 TCLK1 QA(3:0) QB(3:0) QC(3:0) FB_OUT FB_IN SYNC PLL_EN MR#/OE TCLK_SEL REF_SEL VCO_SEL INV_CLK FB_SEL(2:0) SELA(1,0) SELB(1,0) SELC(1,0) SCLK SDATA VDDQA VDDQB VDDQC AVDD VDD AVSS VSS I/O I O I, PU I, PU O O O O I, PU O I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU Supply Supply Supply Supply Supply Supply Supply Type Analog Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD Ground Ground Crystal oscillator input. Description Crystal oscillator output. LVCMOS/LVTTL reference clock input. LVCMOS/LVTTL reference clock input. Clock output bank A. Clock output bank B. Clock output bank C. Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Synchronous pulse output. This output is used for system synchronization. PLL enable/bypass input. When Low, PLL is disabled/bypassed and the input clock connects to the output dividers. Master reset and Output enable/disable input. See Table 2 LVCMOS Clock reference select input. See Table 2. LVCMOS/LVPECL Reference select input. See Table 2. VCO Operating frequency select input. See Table 2. QC(2,3) Phase selection input. See Table 2. Feedback divider select input. See Table 6. Frequency select input, Bank A. See Table 3. Frequency select input, Bank B. See Table 4. Frequency select input, Bank C. See Table 5. Serial Clock input. Serial Data input. 2.5V or 3.3V Power supply for bank A output clocks2,3. 2.5V or 3.3V Power supply for bank B output clocks.2,3 2.5V or 3.3V Power supply for bank C output clocks. 2,3 2.5V or 3.3V Power supply for PLL. 2,3 2.5V or 3.3V Power supply for core and inputs.2,3 Analog Ground. Common Ground. Note: 1.PU = Internal pull up, PD = Internal pull down. 2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin ( 100 MHz 0.6V to 1.8V TCLK to FB_IN Skew within Bank A Skew within Bank B Skew within Bank C Min 200 10 50 33.3 25 20 16.6 12.5 10 8.3 6.25 5 0 25 100 50 33.3 25 20 16.6 12.5 10 8.3 47.5 45 0.1 -125 - Typ 1.3–2.0 0.7–1.3 0.9–1.3 0.6–1.1 0.6–0.9 0.4–0.6 0.6–0.9 Max 380 25 95 63.3 47.5 38 31.6 23.75 19 15.8 11.8 9.5 200 75 1.0 190 95 63.3 47.5 38 31.6 23.75 19 15.8 20 52.5 55 1.0 125 75 100 150 400 10 10 - Unit MHz MHz fin Input Frequency MHz frefDC tr, tf Input Duty Cycle TCLK Input Rise/FallTime % nS fMAX Maximum Output Frequency MHz fSCLK DC tr, tf t(φ) tsk(O) tsk(B) tPLZ, HZ tPZL, ZH Serial Clock Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time ÷4 Feedback ÷6 Feedback ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback MHz % nS pS pS pS nS nS BW PLL Closed Loop Bandwidth (–3 dB) MHz Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 15 June 2005 rev 0.3 AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) (Continued)6 Parameter tJIT(CC) ASM5I9772A Description Cycle-to-Cycle Jitter Condition Same frequency (125 MHz) RMS (1σ) Same frequency Multiple frequencies Same frequency (125 MHz) RMS (1σ) Same frequency Multiple frequencies Min - Typ 7 6 45 - Max 30 150 435 30 75 235 150 1 Unit pS tJIT(PER) Period Jitter pS tJIT(φ) tLOCK I/O Phase Jitter Maximum PLL Lock Time pS mS AC Parameters (VDD= 3.3V ± 5%, TA= –40°C to +85°C)6 Parameter fVCO fXTAL Description VCO Frequency Crystal Frequency Range Condition see Table 7 ÷4 Feedback ÷6 Feedback ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback ÷24 Feedback ÷32 Feedback ÷40 Feedback Bypass mode (PLL_EN = 0) 0.8V to 2.0V ÷2 Output ÷4 Output ÷6 Output ÷8 Output ÷10 Output ÷12 Output ÷16 Output ÷20 Output ÷24 Output fMAX< 100 MHz fMAX > 100 MHz 0.55V to 2.4V TCLK to FB_IN, same VDD Skew within Bank A Skew within Bank B Min 200 10 50 33.3 25 20 16.6 12.5 10 8.3 6.25 5 0 25 100 50 33.3 25 20 16.6 12.5 10 8.3 48 45 0.1 -125 - Typ - Max 500 25 125 83.3 62.5 50 41.6 31.25 25 20.8 15.625 12.5 200 75 1.0 200 125 83.3 62.5 50 41.6 31.25 25 20.8 20 52 55 1.0 125 75 100 Unit MHz MHz fin Input Frequency MHz frefDC tr, tf Input Duty Cycle TCLK Input Rise/FallTime % nS fMAX Maximum Output Frequency MHz fMAX fSCLK DC tr, tf t(φ) tsk(O) Maximum Output Frequency (continued) Serial Clock Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew MHz MHz % nS pS pS 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 15 June 2005 rev 0.3 AC Parameters (VDD= 3.3V ± 5%, TA= –40°C to +85°C) (Continued)6 Parameter tsk(B) tPLZ, HZ tPZL, ZH ASM5I9772A Description Bank-to-Bank Skew Output Disable Time Output Enable Time Condition Skew within Bank C Min - Typ 1.3 - 2.0 0.7 - 1.3 0.9 - 1.3 0.6 - 1.1 0.6 - 0.9 0.4 - 0.6 0.6 - 0.9 7 6 45 - Max 150 325 8 8 30 100 375 30 75 225 150 1 Unit pS nS nS ÷4 Feedback ÷6 Feedback BW PLL Closed-Loop Bandwidth (–3 dB) ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback Same frequency (125 MHz) RMS (1σ ) Same frequency Multiple frequencies Same frequency (125 MHz) RMS (1σ ) Same frequency Multiple frequencies tJIT(φ) tLOCK I/O Phase Jitter Maximum PLL Lock Time I/O same VDD - MHz tJIT(CC) Cycle-to-Cycle Jitter pS tJIT(PER) Period Jitter pS pS mS Sync Output In situations where output frequency relationships are not integer multiples of each other, the SYNC output provides a signal for system synchronization. The ASM5I9772A monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 15 June 2005 rev 0.3 VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QA QC SYNC 3:2 Mode QA QC SYNC 4:1 Mode QA QC SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC Figure 1 ASM5I9772A Power Management The individual output enable / freeze control of the ASM5I9772A allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs cannot be frozen with the serial port. This avoids any potential lock up situation should an error occur in the loading of the serial data. An output is frozen when a logic ‘0’ is programmed and enabled when a logic ‘1’ is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 15 June 2005 rev 0.3 Start Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 ASM5I9772A Figure 2. D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC Table 7. Suggested Oscillator Crystal Parameters Parameter TC TS TA CL RESR Description Frequency Tolerance Frequency Temperature Stability Aging Load Capacitance Effective Series Resistance (ESR) Conditions (TA–10° to +60°C) (First three years @ 25°C) The crystal’s rated load Min – – – – – Typ – – – 20 40 Max ±1100 ± 100 5 – 80 Unit PPM PPM PPM/Yr pF Ohm Zo = 50 ohm Pulse Generator Z = 50 ohm RT = 50 ohm VTT VTT Figure 3. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V VDD LVCMOS_CLK VDD/2 GND VDD FB_IN VDD/2 t(φ) GND Figure 4. LVCMOS Propagation Delay t(φ), Static Phase Offset 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 15 June 2005 rev 0.3 ASM5I9772A VDD VDD/2 tP T0 GND DC = tP / T0 x 100% Figure 5. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(0) GND Figure 6. Output-to-Output Skew, tsk(O) 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 15 June 2005 rev 0.3 Package Information 52-lead TQFP Package ASM5I9772A SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e Inches Min Max …. 0.0020 0.0374 0.4646 0.3898 0.4646 0.3898 0.0177 0.0035 0.0038 0.0102 0.0106 0.0031 0° 0.0472 0.0059 0.0413 0.4803 0.3976 0.4803 0.3976 0.0295 0.0079 0.0062 0.0150 0.0130 0.0079 7° Millimeters Min Max … 0.05 0.95 11.8 9.9 11.8 9.9 0.45 0.09 0.097 0.26 0.27 0.08 0° 1.2 0.15 1.05 12.2 10.1 12.2 10.1 0.75 0.2 0.157 0.38 0.33 0.2 7° 0.03937 REF 1.00 REF 0.0256 BASE 0.65 BASE 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 15 June 2005 rev 0.3 Ordering Information Part Number ASM5I9772A-52-ET ASM5I9772A-52-ER ASM5I9772AG-52-ET ASM5I9772AG-52-ER ASM5I9772A Marking ASM5I9772A ASM5I9772A ASM5I9772AG ASM5I9772AG Package Type 52-pin TQFP, Tray 52-pin TQFP – Tape and Reel 52-pin TQFP, Tray, Green 52-pin TQFP – Tape and Reel, Green Operating Range Industrial Industrial Industrial Industrial Device Ordering Information ASM5I9772AG-52-ET R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 15 June 2005 rev 0.3 ASM5I9772A Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM5I9772A Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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