ASM5P23S05A-1H-08-SR

August 2004 rev 2.0 3.3V ‘SpreadTrak’ Zero Delay Buffer General Features    10 MHz to 133- MHz operating range, compatible with CPU and PCI bus frequencies. Zero input - output propagation delay. Multiple low-skew outputs.        Output-output skew less than 250 ps. Device-device skew less than 700 ps. One input drives 9 outputs, grouped as 4 + 4 + 1 (ASM5P23S09A). One input drives 5 outputs (ASM5P23S05A). Less than 200 ps cycle-to-cycle jitter is compatible with Pentium ® based systems. Test Mode to bypass PLL (ASM5P23S09A only, refer Select Input Decoding Table). Available in 16-pin, 150-mil SOIC, 4.4 mm TSSOP, and 150-mil SSOP packages (ASM5P23S09A) or in 8-pin, 150-mil SOIC package (ASM5P23S05A).   3.3V operation, advanced 0.35µ CMOS technology. ‘SpreadTrak’. ASMP5P23S09A ASMP5P23S05A 133- MHz frequencies, and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The ASM5P23S09A has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. If all the output clocks are not required, Bank B can be three-stated. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P23S09A and ASM5P23S05A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700ps. All outputs have less than 200 ps of cycle-to-cycle jitter. The input and output propagation delay is guaranteed to be less than 250 ps, and the output to output skew is guaranteed to be less than 250ps. The ASM5P23S09A and the ASM5P23S05A are available in two different configurations, as shown in the ordering information table. The ASM5P23SXXA-1 is the base part. The ASM5P23SXXA-1H is the high drive version of the -1 and its rise and fall times are much faster than -1 part. Functional Description ASM5P23S09A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks with Spread Spectrum capability. It is available in a 16-pin package. The ASM5P23S05A is the eight-pin version of the ASM5P23S09A. It accepts one reference input and drives out five low-skew clocks. The -1H version of the ASM5P23SXXA operates at up to Block Diagram REF PLL CLKOUT REF PLL MUX CLKOUT CLKA1 CLKA2 CLKA3 CLK1 CLK2 CLKA4 CLK3 S2 CLKB1 Select Input Decoding S1 CLKB2 CLKB3 CLKB4 CLK4 ASM5P23S09A ASM5P23S05A Alliance Semiconductor 2575, Augustine Drive  Santa Clara, CA  Tel: 408.855.4900  Fax: 408.855.4999  www.alsc.com Notice: The information in this document is subject to change without notice. August 2004 rev 2.0 Select Input Decoding for ASM5P23S09A S2 0 0 1 1 S1 0 1 0 1 Clock A1 - A4 Three-state Driven Driven Driven Clock B1 - B4 Three-state Three-state Driven Driven CLKOUT 1 Driven Driven Driven Driven ASMP5P23S09A ASMP5P23S05A Output Source PLL PLL Reference PLL PLL Shut-Down N N Y N Notes: 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the output. Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero-input-output delay. SpreadTrak Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. ASM5P23S09A and ASM5P23S05A are designed so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew which may cause problems in the systems requiring synchronization. 3.3V ‘SpreadTrak” Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 16 August 2003 rev 2.0 Pin Configuration ASM5P23S09A ASM5P23S05A REF CLKA1 CLKA2 V DD 1 2 3 4 5 6 7 8 16 15 14 13 CLKOUT CLKA4 CLKA3 V DD GND CLKB1 CLKB2 S2 ASM5P23S09A 12 11 10 9 GND CLKB4 CLKB3 S1 REF CLK2 CLK1 GND 1 2 3 4 8 CLKOUT CLK4 V DD ASM5P23S05A 7 6 5 CLK3 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 16 August 2003 rev 2.0 Pin Description for ASM5P23S09A Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name REF 2 3 3 ASM5P23S09A ASM5P23S05A Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A 3.3V supply Ground CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 S1 4 4 3 3 Buffered clock output, bank B Buffered clock output, bank B Select input, bit 2 Select input, bit 1 CLKB3 CLKB4 GND VDD CLKA3 CLKA4 3 3 Buffered clock output, bank B Buffered clock output, bank B Ground 3.3V supply 3 3 3 Buffered clock output, bank A Buffered clock output, bank A Buffered output, internal feedback on this pin CLKOUT Pin Description for ASM5P23S05A Pin # 1 2 3 4 5 6 7 8 Pin Name REF 2 Description Input reference frequency, 5V-tolerant input Buffered clock output Buffered clock output Ground CLK2 3 CLK1 3 GND CLK3 VDD CLK4 3 3 3 Buffered clock output 3.3V supply Buffered clock output Buffered clock output, internal feedback on this pin CLKOUT Notes: 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-up on these inputs. 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 16 August 2003 rev 2.0 Absolute Maximum Ratings Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Tem perature Static Discharge Voltage (per MIL-STD-883, Method 3015) Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 2000 ASM5P23S09A ASM5P23S05A Unit V V V °C °C °C V Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P23S05A and ASM5P23S09A - Commercial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Description Min 3.0 0 Max 3.6 70 30 10 7 Unit V °C pF pF pF 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 16 August 2003 rev 2.0 ASM5P23S09A ASM5P23S05A Electrical Characteristics for ASM5P23S05A and ASM5P23S09A - Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD Notes: 5. REF input has a threshold voltage of VDD/2 6. Parameter is guaranteed by design and characterization. Not 100% tested in production 7. S1 / S2 inputs are CMOS, TTL compatible inputs – The input must toggle somewhere between 0.8 and 2.0. We guarantee the limits of 0.8 and 2.0, but can't guarantee anything tighter than that. As Vdd moves higher the toggle point will move higher, but will always stay below 2.0V. As Vdd moves lower, the toggle point will move lower, but always stay higher than 0.8V. What the 2.0V MIN Vih specification means is that you put 2.0V or a higher voltage into the device, and you will have a logic HIGH. If you put 0.8V or a lower voltage into the device, you will have a logic LOW ( Vil spec = 0.8V max) . It will toggle someplace in between 0.8V and 2.0V, but we don't guarantee exactly where, and the exact point will change depending upon conditions. Characterization shows we toggle at 1.1V and 1.5V (showing a little hysteresis), everything is perfect. We meet spec, plus have ~ 300mV noise immunity on the low end and ~500mV noise immunity on the high side. Under nominal conditions, with no hysteresis, most devices will toggle at about 1.5V for both high and low. Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Supply Current 6 5 5 Test Conditions Min Max 0.8 Unit V V 2.0 VIN = 0V VIN = VDD IOL = 8mA (-1) IOH = 12mA (-1H) 6 50.0 100.0 0.4 2.4 TBD µA µA V V mA IOL = -8mA (-1) IOH = -12mA (-1H) Unloaded outputs at 66.67 MHz, SEL inputs at VDD Switching Characteristics for ASM5P23S05A-1 and ASM5P23S09A-1 - Commercial Temperature Devices7 Parameter 1/t1 Description Output Frequency Duty Cycle = (t2 / t1) * 100 t3 t4 t5 t6 t7 tJ tLOCK Output Rise Time 6 Output Fall Time 6 6 6 Test Conditions 30- pF load 10- pF load Min 10 10 Typ Max 100 133.3 3 Unit MHz Measured at 1.4V, FOUT = 66.67 MHz Measured between 0.8V and 2.0V Measured between 2.0V and 0.8V All outputs equally loaded Measured at VDD /2 40.0 50.0 60.0 2.50 2.50 250 % ns ns ps ps ps ps ms Output-to-output skew CLKOUT Rising Edge Delay, REF Rising Edge to 6 0 0 ±350 700 200 1.0 Device-to-Device Skew 6 Cycle-to-cycle jitter 6 PLL Lock Time 6 Measured at VDD/2 on the CLKOUT pins of the device Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Notes: 7. All parameters specified with loaded outputs. 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 16 August 2003 rev 2.0 ASM5P23S09A ASM5P23S05A 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 16 August 2003 rev 2.0 ASM5P23S09A ASM5P23S05A Switching Characteristics for ASM5I23S05A-1H and ASM5I23S09A-1H - Industrial Temperature Devices Parameter 1/t1 Description Output Frequency Duty Cycle = (t2 / t1) * 100 Duty Cycle = (t2 / t1) * 100 t3 t4 t5 t6 t7 t8 tJ tLOCK Output Rise Time 6 Output Fall Time 6 Output-to-output skew 6 Delay, REF Rising Edge to CLKOUT Rising Edge 6 Device-to-Device Skew 6 Output Slew Rate 6 Cycle-to-cycle jitter 6 PLL Lock Time 6 Measured at VDD/2 on the CLKOUT pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock pre sented on REF pin 200 1.0 1 0 700 6 6 7 Test Conditions 30-pF load 10-pF load Measured at 1.4 V, FOUT = 66.67 MHz Measured at 1.4 V, FOUT < 50.0 MHz Measured between 0.8V and 2.0V Measured between 2.0V and 0.8V All outputs equally loaded Measured at VDD /2 Min 10 10 40.0 45.0 Typ Max 100 133.33 Unit MHz % 50.0 50.0 60.0 55.0 1.50 1.50 250 ns ns ps ps ps V/ns ps ms 0 ± 350 Switching Waveforms Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time OUTPUT 2.0 V 0.8 V t3 t4 2.0 V 0.8 V 3.3 V 0V 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 16 August 2003 rev 2.0 Output - Output Skew ASM5P23S09A ASM5P23S05A 1.4 V OUTPUT 1.4 V OUTPUT t5 Input - Output Propagation Delay V INPUT DD /2 VDD /2 OUTPUT t6 Device - Device Skew V DD /2 CLKOUT, Device 1 V DD /2 CLKOUT, Device 2 t7 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 16 August 2003 rev 2.0 Test Circuits Test Circuit #1 Test Circuit #2 ASM5P23S09A ASM5P23S05A V 0.1 ÿF DD V OUTPUTS CLK OUT 0.1 ÿF C DD 1k  OUTPUTS 1k LOAD 10 pF V 0.1 ÿF DD V GND 0.1 ÿF DD GND GND GND For parameter t (output slew rate) on -1H devices 8 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 16 August 2003 rev 2.0 Package Information: 8-lead (150-mil) SOIC ASM5P23S09A ASM5P23S05A E H D A2 A e B A1 D  L C Symbol Dimensions in inches Min A A1 A2 B C D E e H L  0.057 0.004 0.053 0.012 0.004 0.186 0.148 0.224 0.012 0° Max 0.071 0.010 0.069 0.020 0.01 0.202 0.164 0.248 0.028 8° Dimensions in millimeters Min 1.45 0.10 1.35 0.31 0.10 4.72 3.75 5.70 0.30 0° Max 1.80 0.25 1.75 0.51 0.25 5.12 4.15 6.30 0.70 8° 0.050 BSC 1.27 BSC 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 16 August 2003 rev 2.0 Package Information: 16-lead (150 Mil) Molded SOIC ASM5P23S09A ASM5P23S05A 8 1 PIN 1 ID E H 9 D 16 h Seating P lane A2 A D  0.004 C L e B A1 DIMENSIONS INCHES MIN A A1 A2 B C D E e H h L  0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 0° MAX 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 8° MILLIMETERS MIN 1.55 0.102 1.40 0.33 0.191 9.80 3.81 1.27 BSC 5.84 0.25 0.41 0° 6.20 0.41 0.89 8° MAX 1.73 0.249 1.55 0.49 0.249 9.98 3.99 0.050 BSC 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 16 August 2003 rev 2.0 ASM5P23S09A ASM5P23S05A Package Information: 16-lead Thin Shrunk Small Outline Package (4.40-MM Body) 8 1 PIN 1 ID E H 9 16 A Seating P lane A2 e D A1 B D  L C DIMENSIONS (inches) MIN A A1 A2 B C D E e H L  0.002 0.003 0.007 0.004 0.193 0.169 0.026 BSC 0.246 0.020 0° 0.256 0.028 8° MAX 0.043 0.006 0.37 0.012 0.008 2.008 0.177 DIMENSIONS (mm) MIN 0.05 0.85 0.19 0.09 4.90 4.30 0.65 BSC 6.25 0.50 0° 6.50 0.70 8° MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 16 August 2003 rev 2.0 Package Information: 16-lead (150-mil) SSOP 8 1 ASM5P23S09A ASM5P23S05A P I N 1 ID E H 9 16 D A Seati ng P lane  0.004 A1 e B D C L DIMENSIONS (inches) MIN A A1 B C D E e H L  0.049 0.004 0.008 0.007 0.189 0.150 0.228 0.016 0° MAX 0.065 0.010 0.012 0.010 0.197 0.157 0.244 0.050 8° DIMENSIONS (millimeters) MIN 1.245 0.102 0.203 0.178 4.801 3.81 5.791 0.406 0° MAX 1.651 0.254 0.305 0.254 5.004 3.988 0.635 BSC 6.198 1.27 8° 0.025 BSC 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 16 August 2003 rev 2.0 Ordering Codes Ordering Code ASM5P23S09A-1-16-ST ASM5I23S09A-1-16-ST ASM5P23S09A-1-16-SR ASM5I23S09A-1-16-SR ASM5P23S09A-1-16-TT ASM5I23S09A-1-16-TT ASM5P23S09A-1-16-TR ASM5I23S09A-1-16-TR ASM5P23S09A-1H-16-ST ASM5I23S09A-1H-16-ST ASM5P23S09A-1H-16-SR ASM5I23S09A-1H-16-SR ASM5P23S09A-1H-16-TT ASM5I23S09A-1H-16-TT ASM5P23S09A-1H-16-TR ASM5I23S09A-1H-16-TR ASM5P23S05A-1-08-ST ASM5I23S05A-1-08-ST ASM5P23S05A-1-08-SR ASM5I23S05A-1-08-SR ASM5P23S05A-1-08-TT ASM5I23S05A-1-08-TT ASM5P23S05A-1-08-TR ASM5I23S05A-1-08-TR ASM5P23S05A-1H-08-ST ASM5I23S05A-1H-08-ST ASM5P23S05A-1H-08-SR ASM5I23S05A-1H-08-SR ASM5P23S05A-1H-08-TT ASM5I23S05A-1H-08-TT ASM5P23S05A-1H-08-TR ASM5I23S05A-1H-08-TR Package Type 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC-TAPE & REEL 16-pin 150-mil SOIC-TAPE & REEL 16-pin 4.4-mm TSSOP-TUBE 16-pin 4.4-mm TSSOP-TUBE 16-pin 4.4-mm TSSOP-TAPE & REEL 16-pin 4.4-mm TSSOP-TAPE & REEL 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC-TAPE & REEL 16-pin 150-mil SOIC-TAPE & REEL 16-pin 4.4-mm TSSOP-TUBE 16-pin 4.4-mm TSSOP-TUBE 16-pin 4.4-mm TSSOP-TAPE & REEL 16-pin 4.4-mm TSSOP-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TAPE & REEL 8-pin 4.4-mm TSSOP-TUBE 8-pin 4.4-mm TSSOP-TUBE 8-pin 4.4-mm TSSOP-TAPE & REEL 8-pin 4.4-mm TSSOP-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TAPE & REEL 8-pin 4.4-mm TSSOP-TUBE 8-pin 4.4-mm TSSOP-TUBE 8-pin 4.4-mm TSSOP-TAPE & REEL 8-pin 4.4-mm TSSOP-TAPE & REEL ASM5P23S09A ASM5P23S05A Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Licensed under US patent Nos 5,488,627 and 5,631,920. Preliminary datasheet. Specification subject to change without notice. 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 15 of 16 August 2003 rev 2.0 ASM5P23S09A ASM5P23S05A Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM5P23S09A ASM5P23S05A Document Version: 2.0 8_30_2004 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 16 of 16