ASM706RCSA

ASM706 P/ R/ S/ T/ J ASM708 R/ S/ T/ J October 2003 rev 1.0 3/3.3/4.0 V µP Supervisor Circuits Features • Precision power supply minotor •2.63V threshold (ASM706P/R, ASM708R) •2.93V threshold (ASM706S, ASM708S) •3.08V threshold (ASM706T, ASM708T) •New 4.00V threshold (ASM706J , ASM708J) • • Debounced manual reset input Auxiliary voltage monitor comparator •1.25V threshold •Battery monitor / auxiliary supply monitor • • • Watchdog timer (ASM706P/R/S/T/J) •Watchdog can be disabled by floating WDI 200ms reset time delay Three reset signal options •Active HIGH: ASM706P •Active LOW: ASM706R/S/T/J •Active HIGH and LOW outputs: ASM708R/S/T/J • • DIP, SO and MicroSO packages Guaranteed RESET assertion to VCC = 1.1V General Description The ASM706P/R/S/T/J and ASM708R/S/T/J are cost effective CMOS supervisor circuits that monitor power-supply and battery voltage level, and µP/µC operation. The family offers several functional options. Each device generates a reset signal during power-up, power-down and during brownout conditions. A reset is generated when the supply drops below 2.63V (ASM706P/R, ASM708R), 2.93V (ASM706S, ASM708S), 3.08V (ASM706T, ASM708T) or 4.00 (ASM706J, ASM708J). In addition, the ASM706P/R/S/T/J feature a 1.6 second watchdog timer. The watchdog timer output will trigger a reset if connected to MR. Floating the WDI input pin disables the watchdog timer. The ASM708R/S/T/J have both active-HIGH and active-LOW reset outputs but no watchdog function. The ASM706P has the same pin-out and functions as the ASM706R but has an activeHIGH reset output. A versatile power-fail circuit, useful in checking battery levels and non-5V supplies, has a 1.25V threshold. All devices have a manual reset input. All devices are available in 8-pin DIP, SO and the compact MicroSO packages. The MicroSO package requires 50% less PC board area than the conventional SO package. Applications • • • • • • • • Computers and embedded controllers CTI applications Automotive systems Portable/Battery-operated systems Intelligent instruments Wireless communication systems PDAs and hand-held equipment Safety systems Typical Operating Circuit Unregulated DC +3.3V Regulator VCC VCC PFI ASM706 R/S/T ASM708 R/S/T (ASM706 P) µP R1 RESET (RESET) WDI WDO PFO RESET (RESET) I/O LINE NMI INTERRUPT R2 MR Alliance Semiconductor 2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com Notice: The information in this document is subject to change without notice October 2003 rev 1.0 ASM706 P/ R/ S/ T/ J ASM708 R/ S/ T/ J Block Diagrams Transition Detector VCC Timebase 20kΩ 20kΩ RESET Generator WDI Watchdog Timer WDO VCC RESET MR RESET (RESET) ASM706P MR RESET Generator RESET VCC + + 2.63V (ASM706P/R) 2.93V (ASM706S) 3.08V (ASM706T) 4.00V (ASM706J) VCC + + 2.63V (ASM708R) 2.93V (ASM708S) 3.08V (ASM708T) 4.00V (ASM708J) PFI + - PFI PFO + - PFO 1.25V 1.25V ASM706P/R/S/T/J GND ASM708R/S/T/J GND Pin Configuration MicroSO ASM706R/S/T/J 2 7 RESET 6 5 WDI PFO 2 7 6 5 PFO PFI GND RESET 2 ASM708R/S/T/J DIP/SO ASM708R/S/T/J VCC 2 7 RESET 6 5 NC PFO VCC ASM706P ASM706P MR 1 MR 2 WDO MR 7 RESET VCC 6 WDI PFO WDO ASM706R/S/T/J 8 RESET 1 8 1 8 (RESET) RESET (ASM706P) WDO 1 8 WDI RESET 1 8 7 6 5 NC PFO PFI GND GND 3 PFI 4 GND 3 PFI 4 GND 3 PFI 4 MR 3 VCC 4 MR 3 VCC 4 5 3/3.3/4.0 V µP Supervisor Circuits Notice: The information in this document is subject to change without notice 2 of 16 October 2003 rev 1.0 ASM706 P/ R/ S/ T/ J ASM708 R/ S/ T/ J Pin Description Pin Number ASM706P DIP/ SO MicroSO ASM706R/S/T/J DIP/ SO MicroSO ASM708R/S/T/J DIP/ SO MicroSO Manual reset input. The active LOW input triggers a reset pulse. It is pulled HIGH by a 20kΩ pull-up resistor. It is compatible with TTL/CMOS signals when VCC = 5V. It can be shorted to ground through a mechanical switch. Leave folating or connect to VCC if the function is not used. 2 3 4 4 5 6 2 3 4 4 5 6 2 3 4 4 5 6 VCC GND PFI Monitored power supply input. Ground. Power-fail input voltage monitor. With PFI less than 1.25V, PFO goes LOW. Connect PFI to Ground when not in use. Power-fail output. The output is active LOW and sinks current when PFI is less than 1.25V. If not used, leave the pin unconnected. Watchdog input. WDI controls the internal watchdog timer. A HIGH or LOW signal for 1.6sec at WDI allows the internal timer to run-out, setting WDO low. A rising or falling edge must occur at WDI within 1.6 seconds or WDO goes LOW. The watchdog function is disabled by floating WDI. The internal watchdog timer clears when: RESET is asserted; WDI is three-stated ; or WDI sees a rising or falling edge. Not Connected Active LOW reset output. Pulses LOW for 200ms when triggered, and stays LOW whenever VCC is 7 1 7 1 RESET below the reset threshold. RESET remains LOW for 200ms after VCC rises above the reset threshold or MR goes from HIGH to LOW. A watchdog timeout will not trigger RESET unless WDO is connected to MR. Name Function 1 3 1 3 1 3 MR 5 7 5 7 5 7 PFO 6 8 6 8 - - WDI - - - - 6 8 NC 3/3.3/4.0 V µP Supervisor Circuits Notice: The information in this document is subject to change without notice 3 of 16 October 2003 rev 1.0 Pin Number ASM706P DIP/ SO MicroSO ASM706R/S/T/J DIP/ SO MicroSO ASM708R/S/T/J DIP/ SO MicroSO Name ASM706 P/ R/ S/ T/ J ASM708 R/ S/ T/ J Function 8 2 8 2 - - WDO Watchdog output. WDO goes LOW when the 1.6 second interval watchdog timer times-out and does not go HIGH until a transition occurs at WDI. In addition, when VCC falls below the reset threshold, WDO goes LOW. Unlike RESET, WDO does not have a minimum pulse width and as soon as VCC exceeds the reset threshold, WDO becomes HIGH with no delay. Active HIGH reset output. The inverse of RESET. 7 1 - - 8 2 RESET 3/3.3/4.0 V µP Supervisor Circuits Notice: The information in this document is subject to change without notice 4 of 16 ASM706 P/ R/ S/ T/ J ASM708 R/ S/ T/ J October 2003 rev 1.0 Detailed Descriptions A proper reset input enables a microprocessor/ microcontroller to start in a known state. ASM706 P/ R/ S/ T/ J and ASM708 R/ S/ T/ J assert reset to prevent code execution errors during power-up, power-down and brownout conditions. RESET/RESET Operation The RESET/RESET signals are designed to start or return a µP/µC to a known state. With VCC above 1.2V, RESET and RESET are guaranteed to be asserted. During a power-up sequence, the reset outputs remain asserted until the supply rises above the threshold level. The resets are deasserted approximately 200ms after crossing the threshold. In a brownout situation where VCC falls below the threshold level, the reset outputs are asserted. If a brownout occurs during an already initiated reset period, the reset period will extend for an additional reset period of 200ms. The ASM708 devices have dual reset outputs, one active LOW and one active HIGH. The ASM706P has a single active HIGH reset and the ASM706/R/S/T/J devices have an active LOW reset output. Alliance Part # ASM706P ASM706R ASM706S ASM706T ASM706J ASM708R ASM708S ASM708T ASM708J RESET Polarity HIGH LOW LOW LOW LOW HIGH & LOW HIGH & LOW HIGH & LOW HIGH & LOW Watchdog Timer YES YES YES YES YES NO NO NO NO Manual Reset (MR) The active-LOW manual reset input is pulled high by an internal 20kΩ pull-up resistor and can be driven low by CMOS/TTL logic or a mechanical switch to ground. An external debounce circuit is unnecessary since the 140ms minimum reset time will debounce mechanical pushbutton switches. The minimum MR input pulse width is 0.5µs with a 3V VCC input and 0.15µs with a 5V VCC input. If not used, tie MR to VCC or leave floating. Figure 1: WDI Three-state operation By connecting the watchdog output (WDO) and MR, a watchdog timeout forces a RESET to be generated. Watchdog Timer A watchdog timer available on the ASM706P/R/S/T/J monitors µP/µC activity. An output line on the processor is used to toggle the WDI line. If the line is not toggled within 1.6 seconds on the Watchdog Input (WDI), the internal timer puts the Watchdog Output (WDO) into a LOW state. WDO will remain LOW until a toggle is detected at WDI. The watchdog function is disabled, meaning it is cleared and not counting, if WDI is floated or connected to a three-stated circuit. The watchdog timer is also disabled if RESET is asserted. When RESET becomes inactive and the WDI input sees a high or low transition as short as 100ns (VCC = 2.7V)/ Threshold 2.63V 2.63V 2.93V 3.08V 4.00V 2.63V 2.93V 3.08V 4.00V 3/3.3/4.0 V µP Supervisor Circuits Notice: The information in this document is subject to change without notice 5 of 16 ASM706 P/ R/ S/ T/ J ASM708 R/ S/ T/ J October 2003 rev 1.0 50ns (VCC = 4.5V), the watchdog timer will begin a 1.6 second countdown. Additional transitions at WDI will reset the watchdog timer and initiate a new countdown sequence. WDO will also become LOW and remain so, whenever the supply voltage, VCC, falls below the device threshold level. WDO goes HIGH as soon as VCC transitions above the threshold. There is no minimum pulse width for WDO as there is for the RESET outputs. If WDI is floated, WDO essentially acts as a low supply voltage output indicator. Power-failure Detection With Auxiliary Comparator All devices have an auxiliary comparator with 1.25V trip point. The output, PFO, is active LOW and the noninverting input is PFI. This comparator can be used as a supply voltage monitor with an external resistor voltage divider. As the monitored voltage level falls, PFI is reduced causing the PFO output to go LOW. Normally PFO interrupts the processor so the system can be shut down in a controlled manner. Bi-directional I/O Pin Supply Voltage VCC BUF Buffered RESET Application Information Bi-directional Reset Pin Interfacing The ASM706/8 can interface with µP/µC bi-directional reset pins by connecting a 4.7kΩ resistor in series with the RESET output and the µP/µC bi-directional reset pin. ASM70x 4.7kΩ RESET GND µC or µP RESET Input GND Figure 3: Bi-directional reset pin interfacing 0V Ensuring the RESET is Valid Down to VCC = 0V When VCC falls below 1.2V, the ASM706R/S/T/J and 708R/S/ T/J RESET reset outputs no longer pull down; it becomes indeterminate. To avoid the possibility that stray charges could build up and force RESET to the wrong state, a pulldown resistor should be connected to the RESET pin, thus draining such charges to ground. The resistor value is not critical. A100kΩ resistor will pull RESET to ground without loading it. Figure 2: Watchdog timing 3/3.3/4.0 V µP Supervisor Circuits Notice: The information in this document is subject to change without notice 6 of 16 October 2003 rev 1.0 Monitoring Voltages Other Than VCC The ASM706/708 can monitor voltages other than VCC using the Power Fail circuitry. If a resistive divider is connected from the voltage to be monitored to the PFI input, the PFO will go LOW if the voltage at PFI goes below 1.25V reference. Should hysteresis be desired, connect a resistor (equal to approximately 10 times the sum of the two resistors in the divider) between the PFI and PFO pins. A capacitor between PFI and GND will reduce circuit sensitivity to input high frequency noise. If it is desired to assert a reset in addition to the PFO flag, this may be achieved by connecting the PFO output to MR. R2 R1 VIN ASM706 P/ R/ S/ T/ J ASM708 R/ S/ T/ J +5V VCC MR PFI ASM70X PFO GND RESET To µP Absolute Maximum Ratings Parameter Pin Terminal Voltage with Respect to Ground VCC All other inputs Input Current at VCC and GND Output Current: All outputs Rate of Rise at VCC Plastic DIP Power Dissipation (Derate 9mW/°C above 70°C) SO Power Dissipation (Derate 5.9mW/°C above 70°C) MicroSO POwer Disspation (Derate 4.1mW/°C above 70°C) Operating Temperature Range ASM706xE, ASM708xE ASM706xC, ASM708xC Storage Temperature Range Lead Temperature Soldering (10sec) Figure 4: Monitoring +5V and an additional supply VIN Min Max Unit -0.3 -0.3 6.0 VCC + 0.3 20 20 100 700 470 330 V V mA mA V/µs mV mW‘ mW -40 0 -65 +85 70 160 300 °C °C °C °C Note: These are stress ratings only and functional operation is noy implied. Exposure to absolute maximum ratings for prolonged time periods may affect device reliability. 3/3.3/4.0 V µP Supervisor Circuits Notice: The information in this document is subject to change without notice 7 of 16 October 2003 rev 1.0 ASM706 P/ R/ S/ T/ J ASM708 R/ S/ T/ J Electrical Characteristics Unless otherwise noted, specifications are over the operating temperature range and VCC supply voltages are 2.7V to 5.5V (ASM706P, ASM708R), 3.0 V to 5.5V (ASM706/708S), 3.15V to 5.5V (ASM706/708T) and 4.1V to 5.5.V (ASM706/708J) Parameter Operating Voltage Range Symbol VCC Conditions ASM706xC, ASM708xC ASM706xE, ASM708xE ASM706xC, ASM706xE, MR = VCC, WDI Float- Min 1.1 1.2 Typ Max 5.5 5.5 Unit V Supply Current VCC < 3.6V ICC ing ASM708xC, ASM708xE, MR = VCC, WDI Floating ASM706xC, ASM706xE, MR = VCC, WDI Float- 75 140 µA 50 140 Supply Current VCC < 5.5V ICC ing ASM708xC, ASM708xE, MR = VCC, WDI Floating P and R devices 2.55 2.85 3.00 3.89 75 140 µA 50 2.63 2.93 3.08 4.00 40 140 2.70 3.00 3.15 4.10 mV V RESET Threshold VRT S devices T devices J devices RESET Threshold Hysteresis VCC = 3V (ASM706/8, P/R devices). RESET Pulse Width tRS VCC = 3.3V (ASM706/8, S/T devices). VCC = 4.4V (ASM706/8, J devices). VCC = 5V 4.5V < VCC < 5.5V MR Pulse Width tMR 3.6V < VCC < 4.5V (ASM706/8J devices) VRST (MAX) < VCC < 3.6V (ASM706/8/P/R/S/T devices) 3.6V < VCC < 4.5V (AS706/8J devices) VRST (MAX) < VCC < 3.6V (ASM706/8/P/R/S/T devices) 4.5V < VCC < 5.5V 150 140 200 280 ms 200 ns 500 MR to RESET Out Delay tMD 750 ns 250 3/3.3/4.0 V µP Supervisor Circuits Notice: The information in this document is subject to change without notice 8 of 16 October 2003 rev 1.0 Parameter Symbol VIH MR Input Threshold VIL VIH VIL MR Pullup resistor RP VOH VOL RESET Output Voltage (All R/S/T/J devices) VOH VOL VOL ISOURCE = 800µA, 4.5V < VCC < 5.5V ISINK = 3.2mA, 4.5V < VCC < 5.5V ISOURCE=500µA, VRST(MAX) < VCC < 4.5V ISINK =1.2mA, VRST(MAX) < VCC < 4.5V ISINK = 50µA, VCC = 1.1V (ASM706xC, ASM708xC devices) ISINK =100µA, VCC = 1.2V (ASM706xE, ASM708xE devices) VOH RESET Output Voltage ASM706P VOL VOH VOL VOH RESET Output Voltage ASM708R/S/T/J VOL VOH VOL ISOURCE = 800µA, 4.5V < VCC < 5.5V ISINK = 3.2mA, 4.5V < VCC < 5.5V ISOURCE=500µA, VRST(MAX) < VCC