Numonyx® Axcell™ P30-65nm Flash Memory
128-Mbit, 64-Mbit Single Bit per Cell (SBC)
Datasheet
Product Features
High Performance:
— 65ns initial access time for Easy BGA and
QUAD+
— 75ns initial access time for TSOP
— 25ns 8-word asynchronous-page read mode
— 52MHz with zero WAIT states, 17ns clock-todata output synchronous-burst read mode
— 4-, 8-, 16- and continuous-word options for
burst mode
— 1.8V Low Power buffered programming at
1.8MByte/s (Typ) using 256-word buffer
— Buffered Enhanced Factory Programming at
3.2MByte/s (typ) using 256-word buffer
VCC (core) voltage: 1.7V – 2.0V
VCCQ (I/O) voltage: 1.7V – 3.6V
Standby current: 30µA(Typ)/55µA(Max)
Continuous synchronous read current: 23mA
(Typ)/28mA (Max) at 52MHz
Datasheet
1
Absolute write protection: VPP = Vss
Power-transition erase/program lockout
Individual zero-latency block locking
Individual block lock-down capability
Password Access feature
One-Time Programmable Register:
— 64 OTP bits, programmed with unique
information by Numonyx
— 2112 OTP bits, available for customer
programming
Software:
— 20µs (Typ) program suspend
— 20µs (Typ) erase suspend
— Basic Command Set and Extended Function
Interface (EFI) Command Set compatible
— Common Flash Interface capable
Density and Packaging:
—
—
—
—
Voltage and Power:
—
—
—
—
Enhanced Security:
—
—
—
—
—
—
Architecture:
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte array blocks
— Blank Check to verify an erased block
56-Lead TSOP (128-Mbit, 64-Mbit)
64-Ball Easy BGA (128-Mbit, 64-Mbit)
88-Ball QUAD+ Package (128-Mbit)
16-bit wide data bus
Quality and Reliability:
—
—
—
—
JESD47E Compliant
Operating temperature: –40°C to +85°C
Minimum 100,000 erase cycles
65nm process technology
Apr 2010
Order Number: 208033-02
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and Axcell are trademarks or registered trademarks of Numonyx , B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2010, Numonyx, B.V., All Rights Reserved.
Datasheet
2
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Contents
1.0
Functional Description ............................................................................................... 5
1.1
Introduction ....................................................................................................... 5
1.2
Overview ........................................................................................................... 5
1.3
Memory Map....................................................................................................... 6
2.0
Package Information ................................................................................................. 7
2.1
56-Lead TSOP..................................................................................................... 7
2.2
64-Ball Easy BGA Package .................................................................................... 8
2.3
QUAD+ SCSP Packages ...................................................................................... 10
3.0
Pinouts/Ballouts ..................................................................................................... 11
4.0
Signals .................................................................................................................... 14
5.0
Bus Operations ........................................................................................................ 16
5.1
Read - Asynchronous Mode................................................................................. 16
5.2
Read - Synchronous Mode .................................................................................. 16
5.3
Write ............................................................................................................... 17
5.4
Output Disable .................................................................................................. 17
5.5
Standby ........................................................................................................... 17
5.6
Reset............................................................................................................... 18
6.0
Command Set .......................................................................................................... 19
6.1
Device Command Codes ..................................................................................... 19
6.2
Device Command Bus Cycles .............................................................................. 20
7.0
Read
7.1
7.2
7.3
7.4
7.5
8.0
Program Operation .................................................................................................. 24
8.1
Word Programming ........................................................................................... 24
8.2
Buffered Programming ....................................................................................... 24
8.3
Buffered Enhanced Factory Programming.............................................................. 25
8.4
Program Suspend .............................................................................................. 27
8.5
Program Resume............................................................................................... 28
8.6
Program Protection............................................................................................ 28
9.0
Erase Operation....................................................................................................... 29
9.1
Block Erase ...................................................................................................... 29
9.2
Blank Check ..................................................................................................... 29
9.3
Erase Suspend .................................................................................................. 30
9.4
Erase Resume................................................................................................... 30
9.5
Erase Protection ................................................................................................ 30
Operation........................................................................................................ 22
Read Array ....................................................................................................... 22
Read Device Identifier........................................................................................ 22
Read CFI .......................................................................................................... 23
Read Status Register ......................................................................................... 23
Clear Status Register ......................................................................................... 23
10.0 Security ................................................................................................................... 31
10.1 Block Locking.................................................................................................... 31
10.2 Selectable OTP Blocks ........................................................................................ 33
10.3 Password Access ............................................................................................... 33
11.0 Register................................................................................................................... 34
11.1 Status Register (SR) .......................................................................................... 34
11.2 Read Configuration Register (RCR) ...................................................................... 34
Datasheet
3
Apr 2010
Order Number: 208033-02
P30-65nm SBC
11.3
One-Time Programmable (OTP) Registers .............................................................40
12.0 Power and Reset Specifications ...............................................................................43
12.1 Power-Up and Power-Down .................................................................................43
12.2 Reset Specifications ...........................................................................................43
12.3 Power Supply Decoupling....................................................................................44
13.0 Maximum Ratings and Operating Conditions ............................................................45
13.1 Absolute Maximum Ratings .................................................................................45
13.2 Operating Conditions..........................................................................................45
14.0 Electrical Specifications ...........................................................................................46
14.1 DC Current Characteristics ..................................................................................46
14.2 DC Voltage Characteristics ..................................................................................47
15.0 AC Characteristics ....................................................................................................48
15.1 AC Test Conditions.............................................................................................48
15.2 Capacitance ......................................................................................................49
15.3 AC Read Specifications ......................................................................................50
15.4 AC Write Specifications .......................................................................................54
15.5 Program and Erase Characteristics .......................................................................58
16.0 Ordering Information...............................................................................................59
A
Supplemental Reference Information.......................................................................61
A.1
Common Flash Interface .....................................................................................61
A.2
Flowcharts ........................................................................................................73
A.3
Write State Machine ...........................................................................................83
B
Conventions - Additional Documentation .................................................................87
B.1
Acronyms .........................................................................................................87
B.2
Definitions and Terms ........................................................................................87
C
Revision History.......................................................................................................89
Datasheet
4
Apr 2010
Order Number: 208033-02
P30-65nm SBC
1.0
Functional Description
1.1
Introduction
This document provides information about the Numonyx® AxcellTM P30-65nm Single Bit
per Cell (SBC) Flash memory and describes its features, operations, and specifications.
P30-65nm SBC device is offered in 64-Mbit and 128-Mbit. Benefits include high-speed
interface NOR device, and support for code and data storage. Features include highperformance synchronous-burst read mode, a dramatical improvement in buffer
program time through larger buffer size, fast asynchronous access times, low power,
flexible security options, and three industry-standard package choices.
P30-65nm SBC device is manufactured using 65nm process technology.
1.2
Overview
P30-65nm SBC device provides high performance on a 16-bit data bus. Individually
erasable memory blocks are sized for optimum code and data storage. Upon initial
power-up or return from reset, the device defaults to asynchronous page-mode read.
Configuring the Read Configuration Register (RCR) enables synchronous burst-mode
reads. In synchronous burst mode, output data is synchronized with a user-supplied
clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast buffer program and erase operations. The device features
a 256-word buffer to enable optimum programming performance, which can improve
system programming throughput time significantly to 1.8MByte/s.
Designed for low-voltage systems, the P30-65nm SBC device supports read operations
with VCC at 1.8V, and erase and program operations with VPP at 1.8V or 9.0V. Buffered
Enhanced Factory Programming provides the fastest flash array programming
performance with VPP at 9.0V, which increases factory throughput with 3.2Mbyte/s.
With VPP at 1.8V, VCC and VPP can be tied together for a simple, ultra low power
design. In addition to voltage flexibility, a dedicated VPP connection provides complete
data protection when VPP ≤ VPPLK.
The Command User Interface is the interface between the system processor and all
internal operations of the device. An internal Write State Machine automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
A device command sequence invokes program and erase automation. Each erase
operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations.
The OTP Register allows unique flash device identification that can be used to increase
system security. The individual Block Lock feature provides zero-latency block locking
and unlocking. The P30-65nm SBC device adds enhanced protection via Password
Access; this new feature allows write and/or read access protection of user-defined
blocks. In addition, the P30-65nm SBC device also has backward-compatible One-Time
Programmable (OTP) permanent block locking security feature.
Datasheet
5
Apr 2010
Order Number:208033-02
P30-65nm SBC
1.3
Figure 1:
Memory Map
P30-65nm SBC Memory Map (64-Mbit and 128-Mbit Densities)
64- Kword Block
130
3F0000 – 3FFFFF
64- Kword Block
66
020000 – 02FFFF
64- Kword Block
5
010000 – 01FFFF
64- Kword Block
4
00C000– 00FFFF
008000 – 00BFFF
004000 – 007FFF
000000 – 003FFF
16161616-
Kword Block
Kword Block
Kword Block
Kword Block
128-Mbit
7F0000 – 7FFFFF
64-Mbit
A 128- Mbit
A 64-Mbit
3
2
1
0
Bottom Boot
Word Wide (x16) Mode
A 128- Mbit
7FC000– 7FFFFF
7F8000–7FBFFF
7F4000–7F7000
7F 0000–7F3FFF
16161616-
Kword Block
Kword Block
Kword Block
Kword Block
130
7E0000–7EFFFF
64- Kword Block
126
129
128
A 64-Mbit
127
16161616-
Kword Block
Kword Block
Kword Block
Kword Block
66
3E0000–3EFFFF
64- Kword Block
62
1
010000–01FFFF
64- Kword Block
1
0
000000–00FFFF
64- Kword Block
0
65
64
63
64-Mbit
128-Mbit
3FC000– 3FFFFF
3F8000–3FBFFF
3F4000–3F7FFF
3F0000–3F3FFF
010000–01FFFF
64- Kword Block
000000–00FFFF
64- Kword Block
Top Boot
Word Wide (x16) Mode
Note:
Datasheet
6
Top Boot
Word Wide (x16) Mode
A1 is the least significant address bit for TSOP and Easy BGA while A0 for the QUAD+
package. Unless otherwise indicated, for the purpose of brevity, this document will
consolidate all discussions to A1 as the least significant Address bit.
Apr 2010
Order Number: 208033-02
P30-65nm SBC
2.0
Package Information
2.1
56-Lead TSOP
Figure 2:
TSOP Mechanical Specifications
Z
A2
See Note 2
See Notes 1 and 3
Pin 1
e
See Detail B
E
Y
D1
A1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
0
b
L
Table 1:
TSOP Package Dimensions (Sheet 1 of 2)
Millimeters
Product Information
Inches
Symbol
Min
Nom
Max
Min
Nom
Max
-
1.200
-
-
0.047
Package Height
A
-
Standoff
A1
0.050
-
-
0.002
-
-
Package Body Thickness
A2
0.965
0.995
1.025
0.038
0.039
0.040
Lead Width
b
0.100
0.150
0.200
0.004
0.006
0.008
Lead Thickness
C
0.100
0.150
0.200
0.004
0.006
0.008
Package Body Length
D1
18.200
18.400
18.600
0.717
0.724
0.732
Package Body Width
E
13.800
14.000
14.200
0.543
0.551
0.559
Lead Pitch
e
-
0.500
-
-
0.0197
-
Terminal Dimension
D
19.800
20.00
20.200
0.780
0.787
0.795
Lead Tip Length
L
0.500
0.600
0.700
0.020
0.024
0.028
Datasheet
7
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 1:
TSOP Package Dimensions (Sheet 2 of 2)
Millimeters
Product Information
Inches
Symbol
Min
Nom
Max
Min
Nom
Max
N
-
56
-
-
56
-
Lead Tip Angle
θ
0°
3°
5°
0°
3°
5°
Seating Plane Coplanarity
Y
-
-
0.100
-
-
0.004
Lead to Package Offset
Z
0.150
0.250
0.350
0.006
0.010
0.014
Lead Count
Notes:
1.
One dimple on package denotes Pin 1.
2.
If two dimples, then the larger dimple denotes Pin 1.
3.
Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
2.2
Figure 3:
64-Ball Easy BGA Package
Easy BGA Mechanical Specifications (10x13x1.2 mm)
S1
Ball A1
Corner
1
E
Ball A1
Corner
D
2
3
4
5
6
7
8
8
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
7
5
6
4
3
2
1
S2
b
e
Top View - Ball side down
Bottom View - Ball Side Up
A1
A2
A
Seating
Y
Plane
Note: Drawing not to scale
Table 2:
Easy BGA Package Dimensions for 10x13x1.2 mm (Sheet 1 of 2)
Millimeters
Product Information
Inches
Symbol
Min
Nom
Max
Min
Nom
Max
A
-
-
1.200
-
-
0.0472
Ball Height
A1
0.250
-
-
0.0098
-
-
Package Body Thickness
A2
-
0.780
-
-
0.0307
-
Ball (Lead) Width
b
0.310
0.410
0.510
0.0120
0.0160
0.0200
Package Body Width
D
9.900
10.000
10.100
0.3898
0.3937
0.3976
Package Height
Datasheet
8
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 2:
Easy BGA Package Dimensions for 10x13x1.2 mm (Sheet 2 of 2)
Millimeters
Product Information
Package Body Length
Inches
Symbol
E
Min
Nom
Max
Min
Nom
Max
12.900
13.000
13.100
0.5079
0.5118
0.5157
Pitch
e
-
1.000
-
-
0.0394
-
Ball (Lead) Count
N
-
64
-
-
64
-
Seating Plane Coplanarity
Y
-
-
0.100
-
-
0.0039
Corner to Ball A1 Distance Along D
S1
1.400
1.500
1.600
0.0551
0.0591
0.0630
Corner to Ball A1 Distance Along E
S2
2.900
3.000
3.100
0.1142
0.1181
0.1220
Note:
Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology http://
developer.Numonyx.com/design/flash/packtech.
Datasheet
9
Apr 2010
Order Number:208033-02
P30-65nm SBC
2.3
Figure 4:
QUAD+ SCSP Packages
128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm)
A1 Index
Mark
S1
1
2
3
4
5
6
7
8
8
A
A
B
B
C
C
D
D
7
6
5
4
3
2
1
S2
E
E
F
D
F
G
G
H
H
J
K
J
e
K
L
L
M
M
b
E
Top View - Ball
Down
A2
Bottom View - Ball Up
A1
A
Y
D raw ing not to scale.
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Width
Package Body Length
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Datasheet
10
Symbol
A
A1
A2
b
D
E
e
N
Y
S1
S2
Min
0.200
0.325
9.900
7.900
1.100
0.500
Millimeters
Nom
Max
1.200
0.860
0.375
0.425
10.000
10.100
8.000
8.100
0.800
88
0.100
1.200
1.300
0.600
0.700
Min
0.0079
0.0128
0.3898
0.3110
0.0433
0.0197
Inches
Nom
0.0339
0.0148
0.3937
0.3150
0.0315
88
0.0472
0.0236
Max
0.0472
0.0167
0.3976
0.3189
0.0039
0.0512
0.0276
Apr 2010
Order Number: 208033-02
P30-65nm SBC
3.0
Pinouts/Ballouts
Figure 5:
A16
A15
A14
A13
A12
A11
A10
A9
A23
A22
A21
VSS
NC
WE#
WP#
A20
A19
A18
A8
A7
A6
A5
A4
A3
A2
RFU
RFU
VSS
Notes:
1.
2.
3.
4.
5.
56-Lead TSOP Pinout (64-Mbit and 128-Mbit Densities)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Lead TSOP Pinout
14 mm x 20 mm
Top View
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WAIT
A17
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
ADV#
CLK
RST#
VPP
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE#
VSS
CE#
A1
A1 is the least significant address bit.
A23 is valid for 128-Mbit densities; otherwise, it is a no connect (NC).
A22 is valid for 64-Mbit densities and above; otherwise, it is a no connect (NC).
No Internal Connection on Pin 13; it may be driven or floated. For legacy 130nm designs, this pin can be tied to Vcc.
One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the
product mark.
Datasheet
11
Apr 2010
Order Number:208033-02
P30-65nm SBC
Figure 6:
64-Ball Easy BGA Ballout (64-Mbit and 128-Mbit Densities)
7
8
8
7
A13 VCC
A18
A22
A22
A18
CE#
A14
RFU
A19 RFU
RFU
A12
A15
WP#
A20
A21
A11 RST# VCCQ VCCQ A16
A17
1
2
3
4
A1
A6
A8
VPP
A2
VSS
A9
A3
A7
A10
A4
A5
5
6
6
5
4
3
2
1
VCC A13
VPP
A8
A6
A1
A19
RFU
A14
CE#
A9
VSS
A2
A21
A20
WP#
A15
A12
A10
A7
A3
A17
A16 VCCQ VCCQ RST# A11
A5
A4
A
A
B
B
C
C
D
D
E
E
DQ8
DQ1 DQ9
DQ3 DQ4
CLK DQ15 RFU
RFU DQ15 CLK DQ4 DQ3 DQ9 DQ1
DQ8
RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE#
OE# WAIT ADV# DQ12 DQ11 DQ10 DQ0
RFU
A23
RFU
WE# DQ14 DQ6
RFU
VSS VCC VSS DQ13 VSS DQ7
F
F
G
G
DQ2 VCCQ DQ5 DQ6
DQ14 WE#
DQ5 VCCQ DQ2
RFU
A23
VSS DQ13 VSS VCC
VSS
RFU
H
H
Easy BGA
Top View- Ball side down
Notes:
1.
2.
3.
4.
RFU
RFU DQ7
Easy BGA
Bottom View- Ball side up
A1 is the least significant address bit.
A23 is valid for 128-Mbit densities; otherwise, it is a no connect.
A22 is valid for 64-Mbit densities and above; otherwise, it is a no connect (NC).
One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the
product mark.
Datasheet
12
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Figure 7:
QUAD+ SCSP Ballout and Signals (128-Mbit)
Pin 1
1
2
3
4
5
6
7
8
A
DU
DU
Depop
Depop
Depop
Depop
DU
DU
A
B
A4
A18
A19
VSS
VCC
VCC
A21
A11
B
C
A5
RFU
RFU
VSS
RFU
CLK
A22
A12
C
D
A3
A17
RFU
VPP
RFU
RFU
A9
A13
D
E
A2
A7
RFU
WP#
ADV#
A20
A10
A15
E
F
A1
A6
RFU
RST#
WE#
A8
A14
A16
F
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
F2-CE#
G
H
RFU
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F2-OE#
H
J
RFU
F1-OE#
DQ9
DQ11
DQ4
DQ6
DQ15
VCCQ
J
K
F1-CE#
RFU
RFU
RFU
RFU
VCC
VCCQ
RFU
K
L
VSS
VSS
VCCQ
VCC
VSS
VSS
VSS
VSS
L
M
DU
DU
Depop
Depop
Depop
Depop
DU
DU
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Legends:
Notes:
1.
2.
3.
4.
De-Populated Ball
Reserved for Future Use
Do Not Use
Control Signals
Address
Data
Power/Ground
A22 is valid for 128-Mbit densities; otherwise, it is a no connect (NC).
A21 is valid for 64-Mbit densities and above; otherwise, it is a no connect (NC).
F2-CE# and F2-OE# are no connect (NC) for all densities.
Unlike TSOP and Easy BGA, A0 is the least significant address bit for the QUAD+ package. Unless otherwise indicated, for
the purpose of brevity, this document will consolidate all later discussions to A1 as the least significant Address bit.
Datasheet
13
Apr 2010
Order Number:208033-02
P30-65nm SBC
4.0
Table 3:
Symbol
Signals
TSOP and Easy BGA Signal Descriptions
Type
A[MAX:1]
Input
DQ[15:0]
Input/
Output
Name and Function
ADDRESS INPUTS: Device address inputs. 128-Mbit: A[23:1], 64-Mbit: A[22:1].
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
reads of memory, Status Register, OTP Register, and Read Configuration Register. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
Input
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
CE#
Input
CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted,
flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: Chip Enable must be high when device is not in use.
CLK
Input
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OE#
Input
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
RST#
Input
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
ADV#
WAIT
Output
WAIT: Indicates data valid in synchronous array or non-array burst reads. RCR.10, (WT) determines
its polarity when asserted. WAIT’s active output is VOL or VOH when CE# and OE# are VIL. WAIT is
high-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates in valid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
WE#
Input
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WP#
Input
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lockdown cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
VPP
Power/
Input
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP
voltages should not be attempted.
Set VPP = VPPL for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPPH can be applied to array blocks for 1000 cycles maximum and to parameter blocks for 2500. VPP
can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at
9 V may reduce block cycling capability.
VCC
Power
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ
Power
OUTPUT POWER SUPPLY: Output-driver source voltage.
VSS
Power
GROUND: Connect to system ground. Do not float any VSS connection.
—
RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and
enhancement. These should be treated in the same way as a Don’t Use (DU) signal.
DU
—
DON’T USE: Do not connect to any other signal, or power supply; must be left floating.
NC
—
NO CONNECT: No internal connection; can be driven or floated.
RFU
Datasheet
14
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 4:
Symbol
QUAD+ SCSP Signal Descriptions
Type
Name and Function
A[MAX:0]
Input
ADDRESS INPUTS: Device address inputs. 128-Mbit: A[22:0].
Note: Unlike TSOP and Easy BGA, A0 is the least significant address bit for the QUAD+ package.
Unless otherwise indicated, for the purpose of brevity, this document will consolidate all discussions
to A1 as the least significant Address bit.
DQ[15:0]
Input/
Output
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
Input
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
F1-CE#
Input
Flash CHIP ENABLE: Active low input. F1-CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: Chip enable must be driven high when device is not in use.
CLK
Input
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
F1-OE#
Input
OUTPUT ENABLE: Active low input. F1-OE# low enables the device’s output data buffers during
read cycles. F1-OE# high places the data outputs and WAIT in High-Z.
RST#
Input
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
ADV#
WAIT
Output
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR.10, WT) determines its polarity when asserted. WAIT’s active output is VOL or
VOH when F1-CE# and F1-OE# are VIL. WAIT is high-Z if F1-CE# or F1-OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
WE#
Input
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WP#
Input
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lockdown cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
VPP
Power/
lnput
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP
voltages should not be attempted.
Set VPP = VPPL for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
VCC
Power
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ
Power
OUTPUT POWER SUPPLY: Output-driver source voltage.
VSS
Power
GROUND: Connect to system ground. Do not float any VSS connection.
RFU
—
RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and
enhancement. These should be treated in the same way as a Do Not Use (DU) signal.
DU
—
DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
NC
—
NO CONNECT: No internal connection; can be driven or floated.
Datasheet
15
Apr 2010
Order Number:208033-02
P30-65nm SBC
5.0
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
Bus cycles to/from the P30-65nm SBC device conform to standard microprocessor bus
operations. Table 5, “Bus Operations Summary” summarizes the bus operations and
the logic levels that must be applied to the device control signal inputs.
Table 5:
Bus Operations Summary
Bus Operation
Read
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
Notes
Asynchronous
VIH
X
L
L
L
H
Deasserted
Output
2
Synchronous
VIH
Running
L
L
L
H
Driven
Output
-
Write
VIH
X
L
L
H
L
High-Z
Input
1,2
Output Disable
VIH
X
X
L
H
H
High-Z
High-Z
2
Standby
VIH
X
X
H
X
X
High-Z
High-Z
2
Reset
VIL
X
X
X
X
X
High-Z
High-Z
2,3
Notes:
1.
Refer to the Table 7, “Command Bus Cycles” on page 21 for valid DQ[15:0] during a write
operation.
2.
X = Don’t Care (H or L).
3.
RST# must be at VSS ± 0.2V to meet the maximum specified power-down current.
5.1
Read - Asynchronous Mode
To perform an asynchronous page or single word read, an address is driven onto the
address bus, and CE# is asserted. ADV# can be driven high to latch the address, or it
must be held low throughout the read cycle. WE# and RST# must already have been
deasserted. WAIT is set to a deasserted state during asynchronous page mode and
single word mode as determined by RCR.10. CLK is not used for asynchronous pagemode reads, and is ignored. After OE# is asserted, the data is driven onto DQ[15:0]
after an initial access time tAVQV or tGLQV delay. (See Table 25, “AC Read Specifications”
on page 50).
Note:
If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level,
WAIT signal can be floated and ADV# must be tied to ground.
In asynchronous page mode, eight data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address on the Address bus is driven onto DQ[15:0] after
the initial access delay. The lowest three address bits determine which word of the
8-word page is output from the data buffer at any given time.
Refer to the following waveforms for more detailed information:Figure 19,
“Asynchronous Single-Word Read (ADV# Low)” on page 51, and Figure 20,
“Asynchronous Single-Word Read (ADV# Latch)” on page 52, and Figure 21,
“Asynchronous Page-Mode Read Timing” on page 52.
5.2
Read - Synchronous Mode
To perform a synchronous burst read on array or non-array, an initial address is driven
onto the address bus, and CE# is asserted. WE# and RST# must already have been
deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately,
Datasheet
16
Apr 2010
Order Number: 208033-02
P30-65nm SBC
ADV# can remain asserted throughout the burst access, in which case the address is
latched on the next valid CLK edge while ADV# is asserted. Once OE# is asserted, the
the first word is driven onto DQ[15:0] on the next valid CLK edge after initial access
latency delay (see Section 11.2.2, “Latency Count (RCR[13:11])” on page 36).
Subsequent data is output on valid CLK edges following a minimum delay TCHQV (see
Table 25, “AC Read Specifications” on page 50).
However, for a synchronous non-array read, the same word of data will be output on
successive clock edges until the burst length requirements are satisfied.
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15=0). The WAIT signal is only “deasserted” when data is valid on the bus. When
the device is operating in synchronous non-array read mode, such as read status, read
ID, or read query, the WAIT signal is also “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
Refer to the following waveforms for more detailed information: Figure 22,
“Synchronous Single-Word Array or Non-array Read Timing” on page 53, and
Figure 23, “Continuous Burst Read, showing an Output Delay Timing” on page 53, and
Figure 24, “Synchronous Burst-Mode Four-Word Read Timing” on page 54.
5.3
Write
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 7, “Command Bus Cycles” on page 21
shows the bus cycle sequence for each of the supported device commands, while
Table 6, “Command Codes and Definitions” on page 19 describes each command. See
Table 26, “AC Write Specifications” on page 54 for signal-timing details.
When the device is operating in write operations, WAIT is set to a deasserted state as
determined by RCR.10.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
5.4
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a highimpedance (High-Z) state, WAIT is also placed in High-Z.
5.5
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5ms time interval, 5μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
Datasheet
17
Apr 2010
Order Number:208033-02
P30-65nm SBC
5.6
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
NumonyxTM allow proper CPU initialization following a system reset through the use of
the RST# input.
After initial power-up or reset, the device defaults to asynchronous Read Array mode,
and the Status Register is set to 0x80.
When RST# is driven low (RST# asserted), the flash device enters reset mode. Then all
internal circuits are de-energized, and the output drivers are placed in High-Z. If RST#
is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no
longer valid. A device reset also clears the Status Register. See Table 18, “Power and
Reset” on page 43 for RST# timing detail.
When RST# is driven high (RST# deasserted), a minimum wait is required before the
flash device is able to perform normal operations. Please consider TPHQV (R5) and
TPHWL (W1) during system design. see Table 25, “AC Read Specifications” on page 50.
and Section 26, “AC Write Specifications” on page 54. After this wake-up interval
passes, normal operation is ready for execution.
Datasheet
18
Apr 2010
Order Number: 208033-02
P30-65nm SBC
6.0
Command Set
6.1
Device Command Codes
The flash Command User Interface (CUI) provides access to device read, write, and
erase operations. The CUI does not occupy an addressable memory location; it is part
of the internal logic which allows the flash device to be controlled. The Write State
Machine provides the management for its internal erase and program algorithms.
Commands are written to the CUI to control flash device operations. Table 6,
“Command Codes and Definitions” describes all valid command codes.
For operations that involve multiple command cycles, the possibility exists that the
subsequent command does not get issued in the proper sequence. When this happens,
the CUI sets Status Register bits SR[5,4] to indicate a command sequence error.
Table 6:
Mode
Read
Write
Command Codes and Definitions (Sheet 1 of 2)
Code
Device Mode
0xFF
Read Array
Places the device in Read Array mode. Array data is output on DQ[15:0].
0x70
Read Status
Register
Places the device in Read Status Register mode. The device enters this mode
after a program or erase command is issued. SR data is output on DQ[7:0].
0x90
Read Device ID
or Read
Configuration
Register (RCR)
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status,
or OTP Register data on DQ[15:0].
0x98
Read CFI
Places the device in Read Query mode. Subsequent reads output Common
Flash Interface (CFI) information on DQ[7:0].
0x50
Clear Status
Register
The WSM can only set SR error bits. The Clear Status Register command is
used to clear the SR error bits.
0x40
Word Program
Setup
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. CE# or ADV# must be toggled to
update the SR Data for synchronous Non-array reads. The Read Array
command must be issued to read array data after programming has finished.
0xE8
Buffered Program
This command loads a variable number of words up to the buffer size of 256
words onto the program buffer.
0xD0
Buffered Program
Confirm
The confirm command is issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, writing the data from the buffer to the flash memory array.
0x80
BEFP Setup
First cycle of a 2-cycle command; initiates the BEFP mode. The CUI then
waits for the BEFP Confirm command, 0xD0, that initiates the BEFP
algorithm. All other commands are ignored when BEFP mode begins.
0xD0
BEFP Confirm
If the previous command was BEFP Setup (0x80), the CUI latches the
address and data, and prepares the device for BEFP mode.
0x20
Block Erase Setup
First cycle of a 2-cycle command; prepares the CUI for a block-erase
operation. The WSM performs the erase algorithm on the block addressed by
the Erase Confirm command.
Block Erase Confirm
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During blockerase operations, the device responds only to Read Status Register and Erase
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
SR Data for synchronous Non-array reads.
Erase
0xD0
Datasheet
19
Description
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 6:
Command Codes and Definitions (Sheet 2 of 2)
Mode
Code
0xB0
Program or Erase
Suspend
0xD0
Suspend Resume
This command issued to any device address resumes the suspended program
or block-erase operation.
0x60
Block Lock Setup
First cycle of a 2-cycle command; prepares the CUI for block lock
configuration changes.
0x01
Block Lock
If the previous command was Block Lock Setup (0x60), the addressed block
is locked.
0xD0
Block Unlock
If the previous command was Block Lock Setup (0x60), the addressed block
is unlocked. If the addressed block is in a lock-down state, the operation has
no effect.
0x2F
Block Lock-Down
If the previous command was Block Lock Setup (0x60), the addressed block
is locked down.
0xC0
OTP Register or
Lock Register
program setup
First cycle of a 2-cycle command; prepares the device for a OTP Register or
Lock Register program operation. The second cycle latches the register
address and data, and starts the programming algorithm to program data
into the OTP array.
0x60
Read Configuration
Register Setup
First cycle of a 2-cycle command; prepares the CUI for device read
configuration.
0x03
Read Configuration
Register
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[16:1] to the Read Configuration
Register. Following a Configure RCR command, subsequent read operations
access array data.
0xBC
Block Blank Check
First cycle of a 2-cycle command; initiates the Blank Check operation on a
array block.
0xD0
Block Blank Check
Confirm
Second cycle of blank check command sequence; it latches the block address
and executes blank check on the array block.
0xEB
Extended Function
Interface
This command is used in extended function interface. first cycle of a multiplecycle command second cycle is a Sub-Op-Code, the data written on third
cycle is one less than the word count; the allowable value on this cycle are 0
through 511. The subsequent cycles load data words into the program buffer
at a specified address until word count is achieved.
Configuration
Blank Check
EFI
6.2
Description
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR.2 (program
suspended) or SR.6 (erase suspended), along with SR.7 (ready). The WSM
remains in the suspend mode regardless of control signal states (except for
RST# asserted).
Suspend
Protection
Device Mode
Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the CUI. See
Table 7, “Command Bus Cycles” on page 21. Several commands are used to modify
array data including Word Program and Block Erase commands. Writing either
command to the CUI initiates a sequence of internally-timed functions that culminate in
the completion of the requested task. However, the operation can be aborted by either
asserting RST# or by issuing an appropriate suspend command.
Datasheet
20
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 7:
Command Bus Cycles
Mode
Command
Read Array
Read
Bus
Cycles
1
First Bus Cycle
Second Bus Cycle
Oper
Addr(1)
Data(2)
Oper
Addr(1)
Data(2)
Write
DnA
0xFF
-
-
-
Read Device Identifier
≥2
Write
DnA
0x90
Read
DBA + IA
ID
Read CFI
≥2
Write
DnA
0x98
Read
DBA + CFI-A
CFI-D
Read Status Register
2
Write
DnA
0x70
Read
DnA
SRD
Clear Status Register
1
Write
DnA
0x50
-
-
-
Word Program
2
Write
WA
0x40
Write
WA
WD
Buffered Program(3)
>2
Write
WA
0xE8
Write
WA
N-1
Buffered Enhanced
Factory Program
(BEFP)(4)
>2
Write
WA
0x80
Write
WA
0xD0
Block Erase
2
Write
BA
0x20
Write
BA
0xD0
Program/Erase
Suspend
1
Write
DnA
0xB0
-
-
-
Program/Erase
Resume
1
Write
DnA
0xD0
-
-
-
Block Lock
2
Write
BA
0x60
Write
BA
0x01
Block Unlock
2
Write
BA
0x60
Write
BA
0xD0
Block Lock-down
2
Write
BA
0x60
Write
BA
0x2F
Program OTP Register
2
Write
OTP-RA
0xC0
Write
OTP-RA
OTP-D
Program Lock Register
2
Write
LRA
0xC0
Write
LRA
LRD
Configure Read
Configuration Register
2
Write
RCD
0x60
Write
RCD
0x03
Blank Check
Block Blank Check
2
Write
BA
0xBC
Write
BA
D0
EFI
Extended Function
Interface(5)
>2
Write
WA
0xEB
Write
WA
Sub-Op
code
Program
Erase
Suspend
Protection
Configuration
Notes:
1.
First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address.
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Read CFI address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
OTP-RA = OTP Register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[16:1] for TSOP and BGA package; on A[15:0] for QUAD+ package.
2.
ID = Identifier data.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
OTP-D = OTP Register data.
LRD = Lock Register data.
3.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
is followed by up to 256 words of data. Then the confirm command (0xD0) is issued, triggering the array programming
operation.
4.
The confirm command (0xD0) is followed by the buffer data.
5.
The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1 ≤ N ≤ 256. The subsequent cycles load data
words into the program buffer at a specified address until word count is achieved. After the data words are loaded, the
final cycle is the confirm cycle 0xD0).
Datasheet
21
Apr 2010
Order Number:208033-02
P30-65nm SBC
7.0
Read Operation
The device can be in any of four read states: Read Array, Read Identifier, Read Status
or Read Query. Upon power-up or after a reset, the device defaults to Read Array
mode. To change the read state, the appropriate read command must be written to the
device (see Section 6.2, “Device Command Bus Cycles” on page 20). The following
sections describe read-mode operations in detail.
In order to enable synchronous burst reads, the RCR must be configured. Please see
Section 11.2, “Read Configuration Register (RCR)” on page 34 for RCR detail. Please
refer to Section 5.1, “Read - Asynchronous Mode” on page 16 and Section 5.2, “Read Synchronous Mode” on page 16 for bus operation detail. See Section 25, “AC Read
Specifications” on page 50 for timing specification.
7.1
Read Array
Following a device power-up or reset, the device is set to Read Array mode. However,
to perform array reads after any other device operation (e.g. write operation), the Read
Array command must be issued in order to read from the flash memory array. Please
refer to Section 5.1, “Read - Asynchronous Mode” on page 16 and Section 5.2, “Read Synchronous Mode” on page 16 for bus operation detail. See Section 25, “AC Read
Specifications” on page 50 for timing specification.
7.2
Read Device Identifier
The Read Device Identifier command instructs the device to output manufacturer code,
device identifier code, block-lock status, OTP Register data, or Read Configuration
Register data (see Section 6.2, “Device Command Bus Cycles” on page 20 for details on
issuing the Read Device Identifier command). Table 8, “Device Identifier Information”
on page 22 and Table 9, “Device ID codes” on page 23 show the address offsets and
data values for this device.
Table 8:
Device Identifier Information (Sheet 1 of 2)
Address(1,2)
Data(x16)
Manufacturer Code
0x00
0x89h
Device ID Code
0x01
Item
• Block Is Unlocked
• Block Is Locked
ID (See
Table 9)
Lock Bit:
Block Lock Configuration:
DQ0 = 0b0
BBA(1) + 0x02
DQ0 = 0b1
• Block Is not Locked-Down
DQ1 = 0b0
• Block Is Locked-Down
DQ1 = 0b1
Read Configuration Register
0x05
RCR Contents
General Purpose Register(3)
DBA(2) + 0x07
GPR data
Lock Register 0
0x80
PR-LK0
64-bit Factory-Programmed OTP Register
0x81–0x84
Numonyx Factory OTP Register data
64-bit User-Programmable OTP Register
0x85–0x88
User OTP Register data
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Table 8:
Device Identifier Information (Sheet 2 of 2)
Item
Address(1,2)
Data(x16)
0x89
PR-LK1 OTP Register lock data
0x8A–0x109
User OTP Register data
Lock Register 1
128-bit User-Programmable OTP Registers
Notes:
1.
BBA = Block Base Address.
2.
DBA = Device base Address, Numonyx reserves other configuration address locations.
3.
The GPR is used as read out register for Extended Function interface command.
Table 9:
Device ID codes
ID Code Type
Top Boot
Bottom Boot
7.3
Device Density
Device Identifier Codes
64-Mbit
8817
128-Mbit
8818
64-Mbit
881A
128-Mbit
881B
Read CFI
The Read CFI command instructs the device to output Common Flash Interface data
when read. See Figure 6.1, “Device Command Codes” on page 19. Section A.1,
“Common Flash Interface” on page 61 shows CFI information and address offsets
within the CFI database.
7.4
Read Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. SRD is automatically made available
following a Word Program, Block Erase, or Block Lock command sequence. Reads from
the device after any of these command sequences outputs the device’s status until
another valid command is written (e.g. the Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. SRD is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, when reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update SRD.
The Device Ready Status bit (SR.7) provides overall status of the device. SR[6:1]
present status and error information about the program, erase, suspend, VPP, and
block-locked operations.
See Table 12, “Status Register Description” on page 34 for the description of the Status
Register.
7.5
Clear Status Register
The Clear Status Register command clears the Status Register. It functions independent
of VPP. The WSM sets and clears SR.7, but it sets bits SR[5:3,1] without clearing them.
The Status Register should be cleared before starting a command sequence to avoid
any ambiguity. A device reset also clears the Status Register.
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8.0
Program Operation
The device supports three programming methods: Word Programming (40h/10h),
Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h,
D0h). The following sections describe device programming in detail.
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be deasserted and the block must be unlocked before
attempting to program the block. Attempting to program a locked block causes a
program error (SR[4,1] set) and termination of the operation. See Section 10.0,
“Security” on page 31 for details on locking and unlocking blocks.
8.1
Word Programming
Word programming operations are initiated by writing the Word Program Setup
command to the device. This is followed by a second write to the device with the
address and data to be programmed. The device outputs Status Register data when
read. See Figure 32, “Word Program Flowchart” on page 73. VPP must be above VPPLK,
and within the specified VPPL min/max values.
During programming, the WSM executes a sequence of internally-timed events that
program the desired data bits at the addressed location, and verifies that the bits are
sufficiently programmed. Programming the flash memory array changes “ones” to
“zeros”. Memory array bits that are zeros can be changed to ones only by erasing the
block.
The Status Register can be examined for programming progress and errors by reading
at any address. The device remains in the Read Status Register state until another
command is written to the device.
Status Register bit SR.7 indicates the programming status while the sequence
executes. Commands that can be issued to the device during programming are Read
Status Register, Read Device Identifier, Read CFI, and Read Array (this returns
unknown data).
When programming has finished, Status Register bit SR.4 (when set) indicates a
programming failure. If SR.3 is set, the WSM could not perform the word programming
operation because VPP was outside of its acceptable limits. If SR.1 is set, the word
programming operation attempted to program a locked block, causing the operation to
abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow,
when word programming has completed.
8.2
Buffered Programming
The device features a 256-word buffer to enable optimum programming performance.
For Buffered Programming, data is first written to an on-chip write buffer. Then the
buffer data is programmed into the flash memory array in buffer-size increments. This
can improve system programming performance significantly over non-buffered
programming. (see Figure 35, “Buffer Program Flowchart” on page 76).
When the Buffered Programming Setup command is issued, Status Register information
is updated and reflects the availability of the buffer. SR.7 indicates buffer availability: if
set, the buffer is available; if cleared, the buffer is not available.
Note:
Datasheet
24
The device defaults to output SR data after the Buffered Programming Setup Command
(E8h) is issued. CE# or OE# must be toggled to update Status Register. Don’t issue the
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Read SR command (70h), which would be interpreted by the internal state machines as
Buffer Word Count.
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. Subsequent writes provide additional device addresses and
data. All data addresses must lie within the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the starting address at the beginning of a 256-word boundary (A[8:1] = 0x00).
Note:
If a misaligned address range is issued during buffered programming, the program
region must also be within an 256-word aligned boundary.
After the last data is written to the buffer, the Buffered Programming Confirm command
must be issued to the original block address. The WSM begins to program buffer
contents to the flash memory array. If an error occurs while writing to the array, the
device stops programming, and SR[7,4] are set, indicating a programming failure.
When Buffered Programming has completed, additional buffer writes can be initiated by
issuing another Buffered Programming Setup command and repeating the buffered
program sequence. Buffered programming may be performed with VPP = VPPL or VPPH
(see Section 13.2, “Operating Conditions” on page 45 for limitations when operating
the device with VPP = VPPH).
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and SR[5,4] are set.
If Buffered programming is attempted while VPP is at or below VPPLK, SR[4,3] are set.
If any errors are detected that have set Status Register bits, the Status Register should
be cleared using the Clear Status Register command.
8.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up the flash programming
perforamnce. The enhanced programming algorithm used in BEFP eliminates traditional
programming elements that drive up overhead in device programmer systems.
BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 37, “BEFP
Flowchart” on page 78). It uses a write buffer to spread up the program performance
across 256 data words. Verification occurs in the same phase as programming to
accurately program the flash memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This
enhancement eliminates three write cycles per buffer: two commands and the word
count for each set of 256 data words. Host programmer bus cycles fill the device’s write
buffer followed by a status check. SR.0 indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 256-word array
boundary. This aspect of BEFP saves host programming equipment the address-bus
setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
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Apr 2010
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8.3.1
BEFP Requirements and Considerations
Table 10: BEFP Requirements
Parameter/Issue
Requirement
Notes
Case Temperature
TC = 30°C ± 10°C
-
VCC
Nominal Vcc
-
VPP
Driven to VPPH
-
Setup and Confirm
Target block must be unlocked before issuing the BEFP Setup and Confirm commands.
-
Programming
The first-word address (WA0) of the block to be programmed must be held constant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired.
-
Buffer Alignment
WA0 must align with the start of an array buffer boundary.
1
Note:
Word buffer boundaries in the array are determined by A[8:1] (0x00 through 0xFF). The alignment start point is A[8:1] =
0x000.
Table 11: BEFP Considerations
Parameter/Issue
Requirement
Notes
Cycling
For optimum performance, cycling must be limited below 50 erase cycles per block.
1
Programming blocks
BEFP programs one block at a time; all buffer data must fall within a single block.
2
Suspend
BEFP cannot be suspended.
-
Programming the flash
memory array
Programming to the flash memory array can occur only when the buffer is full.
3
Notes:
1.
Some degradation in performance may occur is this limit is exceeded, but the internal algorithm continues to work
properly.
2.
If the internal address counter increments beyond the block’s maximum address, addressing wraps around to the
beginning of the block.
3.
If the number of words is less than 256, remaining locations must be filled with 0xFFFF.
8.3.2
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR.7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A
delay before checking SR.7 is required to allow the WSM enough time to perform all of
its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR.4
is set and BEFP operation terminates. If the block was found to be locked, SR.1 is also
set. SR.3 is set if the error occurred due to an incorrect VPP level.
Note:
Reading from the device after the BEFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be
interpreted as data to be loaded into the buffer.
8.3.3
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR.7
cleared indicates the device is busy and the BEFP program/verify phase is activated.
SR.0 indicates the write buffer is available.
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Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For BEFP, the count value for buffer loading is always
the maximum buffer size of 256 words. During the buffer-loading sequence, data is
stored to sequential buffer locations starting at address 0x00. Programming of the
buffer contents to the flash memory array starts as soon as the buffer is full. If the
number of words is less than 256, the remaining buffer locations must be filled with
0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an
address outside of the current block's range during a buffer-fill sequence
causes the algorithm to exit immediately. Any data previously loaded into the
buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the BEFP
algorithm will be aborted and the program fails and (SR.4) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the
flash memory array; programming continues from where the previous buffer sequence
ended. The host programming system must poll SR.0 to determine when the buffer
program sequence completes. SR.0 cleared indicates that all buffer data has been
transferred to the flash array; SR.0 set indicates that the buffer is not available yet for
the next fill cycle. The host system may check full status for errors at any time, but it is
only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write
cycles should be issued to the device until SR.0 = 0 and the device is ready for the next
buffer fill.
Note:
Any spurious writes are ignored after a buffer fill operation and when internal program
is proceeding.
The host programming system continues the BEFP algorithm by providing the next
group of data words to be written to the buffer. Alternatively, it can terminate this
phase by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the BEFP Exit phase.
8.3.4
BEFP Exit Phase
When SR.7 is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed
successfully. When exiting the BEFP algorithm with a block address change, the read
mode will not change. After BEFP exit, any valid command can be issued to the device.
8.4
Program Suspend
Issuing the Program Suspend command while programming suspends the
programming operation. This allows data to be accessed from the device other than the
one being programmed. The Program Suspend command can be issued to any device
address. A program operation can be suspended to perform reads only. Additionally, a
program operation that is running during an erase suspend can be suspended to
perform a read operation (see Figure 36, “Program Suspend/Resume Flowchart” on
page 77).
When a programming operation is executing, issuing the Program Suspend command
requests the WSM to suspend the programming algorithm at predetermined points. The
device continues to output Status Register data after the Program Suspend command is
issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend
latency is specified in Section 15.5, “Program and Erase Characteristics” on page 58.
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To read data from the device, the Read Array command must be issued. Read Array,
Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid
commands during a program suspend.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at its programming level, and WP# must remain
unchanged while in program suspend. If RST# is asserted, the device is reset.
8.5
Program Resume
The Resume command instructs the device to continue programming, and
automatically clears Status Register bits SR[7,2]. This command can be written to any
address. If error bits are set, the Status Register should be cleared before issuing the
next instruction. RST# must remain deasserted (see Figure 33, “Program Suspend/
Resume Flowchart” on page 74).
8.6
Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If
VPP is at or below VPPLK, programming operations halt and SR.3 is set indicating a VPPlevel error. Block Lock Registers are not affected by the voltage level on VPP; they may
still be programmed and read, even if VPP is less than VPPLK.
Figure 8:
Example VPP Supply Connections
VCC
VPP
VCC
VPP
VPP=VPPH
VCC
VPP
• Low Voltage and Factory Programming
Datasheet
28
PROT #
VCC
VPP
≤ 10K Ω
• Factory Programming with VPP = VPPH
• Complete write/Erase Protection when VPP ≤ VPPLK
VCC
VCC
• Low-voltage Programming only
• Logic Control of Device Protection
VCC
VCC
VPP
• Low Voltage Programming Only
• Full Device Protection Unavailable
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9.0
Erase Operation
Flash erasing is performed on a block basis. An entire block is erased each time an
erase command sequence is issued, and only one block is erased at a time. When a
block is erased, all bits within that block read as logical ones. The following sections
describe block erase operations in detail.
9.1
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the
address of the block to be erased (see Section 6.2, “Device Command Bus Cycles” on
page 20). Next, the Block Erase Confirm command is written to the address of the
block to be erased. If the device is placed in standby (CE# deasserted) during an erase
operation, the device completes the erase operation before entering standby. VPP must
be above VPPLK and the block must be unlocked (see Figure 38, “Block Erase Flowchart”
on page 79).
During a block erase, the WSM executes a sequence of internally-timed events that
conditions, erases, and verifies all bits within the block. Erasing the flash memory array
changes “zeros” to “ones”. Memory block array data that are ones can be changed to
zeros by programming block.
The Status Register can be examined for block erase progress and errors by reading
any address. The device remains in the Read Status Register state until another
command is written. SR.0 indicates whether the addressed block is erasing. Status
Register bit SR.7 is set upon erase completion.
Status Register bit SR.7 indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR.5 indicates an erase
failure if set. SR.3 set would indicate that the WSM could not perform the erase
operation because VPP was outside of its acceptable limits. SR.1 set indicates that the
erase operation attempted to erase a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase operation has completed.
9.2
Blank Check
The Blank Check operation determines whether a specified array block is blank (i.e.
completely erased). Without Blank Check, Block Erase would be the only other way to
ensure a block is completely erased. Blank Check is especially useful in the case of
erase operation interrupted by a power loss event.
Blank check can apply to only one block at a time, and no operations other than Status
Register Reads are allowed during Blank Check (e.g. reading array data, program,
erase etc). Suspend and resume operations are not supported during Blank Check, nor
is Blank Check supported during any suspended operations.
Blank Check operations are initiated by writing the Block Blank Check command to the
block address. Next, the Blank Check Confirm command is issued along with the same
block address. When a successful command sequence is entered, the device
automatically enters the Read Status State. The WSM then reads the entire specified
block, and determines whether any bit in the block is programmed or over-erased.
The Status Register can be examined for Blank Check progress and errors by reading
any address within the block being accessed. During a blank check operation, the
Status Register indicates a busy status (SR.7 = 0). Upon completion, the Status
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Register indicates a ready status (SR.7 = 1). The Status Register should be checked for
any errors, and then cleared. If the Blank Check operation fails, which means the block
is not completely erased, the Status Register bit SR.5 will be set (“1”). CE# or OE#
toggle (during polling) updates the Status Register.
After examining the Status Register, it should be cleared by the Clear Status Register
command before issuing a new command. The device remains in Status Register Mode
until another command is written to the device. Any command can follow once the
Blank Check command is complete.
9.3
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend command can be issued to any device address. A block
erase operation can be suspended to perform a word or buffer program operation, or a
read operation within any block except the block that is erase suspended (see
Figure 34, “Erase Suspend/Resume Flowchart” on page 75).
When a block erase operation is executing, issuing the Erase Suspend command
requests the WSM to suspend the erase algorithm at predetermined points. The device
continues to output Status Register data after the Erase Suspend command is issued.
Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in Section 15.5, “Program and Erase Characteristics” on page 58.
To read data from the device (other than an erase-suspended block), the Read Array
command must be issued. During Erase Suspend, a Program command can be issued
to any block other than the erase-suspended block. Block erase cannot resume until
program operations initiated during erase suspend complete. Read Array, Read Status
Register, Read Device Identifier, Read CFI, and Erase Resume are valid commands
during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend,
Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase
Suspend.
During an erase suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at a valid level, and WP# must remain unchanged
while in erase suspend. If RST# is asserted, the device is reset.
9.4
Erase Resume
The Erase Resume command instructs the device to continue erasing, and
automatically clears SR[7,6]. This command can be written to any address. If Status
Register error bits are set, the Status Register should be cleared before issuing the next
instruction. RST# must remain deasserted.
9.5
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If
VPP ≤ VPPLK, erase operations halt and SR.3 is set indicating a VPP-level error.
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10.0
Security
The device features security modes used to protect the information stored in the flash
memory array. The following sections describe each security mode in detail.
10.1
Block Locking
Individual instant block locking is used to protect user code and/or data within the flash
memory array. All blocks power up in a locked state to protect array data from being
altered during power transitions. Any block can be locked or unlocked with no latency.
Locked blocks cannot be programmed or erased; they can only be read.
Software-controlled security is implemented using the Block Lock and Block Unlock
commands. Hardware-controlled security can be implemented using the Block LockDown command along with asserting WP#. Also, VPP data security can be used to
inhibit program and erase operations (see Section 8.6, “Program Protection” on
page 28 and Section 9.5, “Erase Protection” on page 30).
10.1.1
Lock Block
To lock a block, issue the Block Lock Setup command. The next command must be the
Block Lock command issued to the desired block’s address (see Section 6.2, “Device
Command Bus Cycles” on page 20 and Figure 39, “Block Lock Operations Flowchart” on
page 80). If the Configure Read Configuration Register command is issued after the
Block Lock Setup command, the device configures the RCR instead.
Block lock and unlock operations are not affected by the voltage level on VPP. The block
lock bits may be modified and/or read even if VPP is at or below VPPLK.
10.1.2
Unlock Block
The Block Unlock command is used to unlock blocks (see Section 6.2, “Device
Command Bus Cycles” on page 20). Unlocked blocks can be read, programmed, and
erased. Unlocked blocks return to a locked state when the device is reset or powered
down. If a block is in a lock-down state, WP# must be deasserted before it can be
unlocked (see Figure 9, “Block Locking State Diagram” on page 32).
10.1.3
Lock-Down Block
A locked or unlocked block can be locked-down by writing the Block Lock-Down
command sequence (see Section 6.2, “Device Command Bus Cycles” on page 20).
Blocks in a lock-down state cannot be programmed or erased; they can only be read.
However, unlike locked blocks, their locked state cannot be changed by software
commands alone. A locked-down block can only be unlocked by issuing the Block
Unlock command with WP# deasserted. To return an unlocked block to locked-down
state, a Block Lock-Down command must be issued prior to changing WP# to VIL.
Locked-down blocks revert to the locked state upon reset or power up the device (see
Figure 9, “Block Locking State Diagram” on page 32).
10.1.4
Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see
Section 7.2, “Read Device Identifier” on page 22). Data bits DQ[1:0] display the
addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the
addressed block’s lock-down bit.
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Figure 9:
Block Locking State Diagram
P G M /E R A S E
ALLO W ED
P G M /E R A S E
PREVENTED
LK/
D0h
[0 0 0 ]
LK/
LK/
01h
2Fh
[0 0 1 ]
P o w e r -U p /
R e s e t D e fa u lt
LK/
2Fh
W P # = V IL = 0
V ir tu a l lo c k dow n
W
[1 1 0 ]
P#
to
gg
LK/
D 0h
W P # = V IH = 1
[0 1 1 ]
A ny Lock
com m ands
le
LK/
01h or 2Fh
LK/
D0h
LK/
01h
L o c k e d -d o w n
W P # to g g le
L o c k e d -d o w n
is d is a b le d b y
W P # = V IH
[1 1 1 ]
LK/
2Fh
[1 0 0 ]
Note:
[0 1 0 ]
LK/
2Fh
P o w e r-U p /
R e s e t D e fa u lt
[1 0 1 ]
LK: Lock Setup Command, 60h; LK/D0h: Unlock Command; LK/01h: Lock Command; LK/2Fh: Lock-Down Command.
10.1.5
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change
block locking during an erase operation, first issue the Erase Suspend command.
Monitor the Status Register until SR.7 and SR.6 are set, indicating the device is
suspended and ready to accept another command.
Next, write the desired lock command sequence to a block, which changes the lock
state of that block. After completing block lock or unlock operations, resume the erase
operation using the Erase Resume command.
Note:
A Lock Block Setup command followed by any command other than Lock Block, Unlock
Block, or Lock-Down Block produces a command sequence error and set Status
Register bits SR.4 and SR.5. If a command sequence error occurs during an erase
suspend, SR.4 and SR.5 remains set, even after the erase operation is resumed. Unless
the Status Register is cleared using the Clear Status Register command before
resuming the erase operation, possible erase errors may be masked by the command
sequence error.
If a block is locked or locked-down during an erase suspend of the same block, the lock
status bits change immediately. However, the erase operation completes when it is
resumed. Block lock operations cannot occur during a program suspend. See Appendix
A, “Write State Machine” on page 83, which shows valid commands during an erase
suspend.
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10.2
Selectable OTP Blocks
P30-65nm SBC device is backward-compatible with the OTP permanent block lock
security feature of the legacy P30-130nm device. Blocks from the main array can be
optionally configured as OTP. Ask your local Numonyx Sales representative for details
about these selectable OTP implementations.
10.3
Password Access
The Password Access is a security enhancement offered on the P30-65nm SBC device.
This feature protects information stored in array blocks by preventing content
alteration or reads until a valid 64-bit password is received. The Password Access may
be combined with Flexible block blocking to create a multi-tiered solution.
Please contact representative Numonyx Sales for further details concerning the
Password Access.
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P30-65nm SBC
11.0
Register
When non-array reads are performed in asynchronous page mode only the first data is
valid and all subsequent data are undefined. When a non-array read operation occurs
as synchronous burst mode, the same word of data requested will be output on
successive clock edges until the burst length requirements are satisfied.
11.1
Status Register (SR)
The Status Register provides the ready/busy information of the device, as well as the
error information about the program, erase, VPP and block-locked operations. please
refer to Section 7.4, “Read Status Register” on page 23 and Section 7.5, “Clear Status
Register” on page 23 for detail operations.
Table 12: Status Register Description
Status Register (SR)
Default Value = 0x80
Device
Ready
Status
Erase Suspend
Status 1
Erase Status
Program Status
VPP Status
Program
Suspend Status
Block-Locked
Status
BEFP Write
Status
DRS
ESS
ES
PS
VPPS
PSS
BLS
BWS
7
6
5
4
3
2
1
0
Bit
Name
Description
7
Device Ready Status
0 = Device is busy; program or erase cycle in progress; SR.0 valid.
1 = Device is ready; SR[6:1] are valid.
6
Erase Suspend Status
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
5
Erase Status
SR.5
SR.4
0
0
1
1
0
1
0
1
Command
Sequence
Error
Description
Program or Erase operation successful.
Program error - operation aborted.
Erase error - operation aborted.
Command sequence error - command aborted.
4
Program Status
3
VPP Status
0 = VPP within acceptable limits during program or erase operation.
1 = VPP < VPPLK during program or erase operation.
2
Program Suspend Status
0 = Program suspend not in effect.
1 = Program suspend in effect.
1
Block-Locked Status
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
0
2
BEFP Write Status
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
1 = BEFP in-progress.
1. Always clear the Status Register before resuming erase operations afer an Erase Suspend command; this prevents ambiguity in
Status Register information. For example, if a command sequence error occurs during an erase suspend state, the Status
Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible
errors during the erase operation cannot be deteted via the Stauts Register because it contains the previous error status.
2. BEFP mode is only valid in array.
11.2
Read Configuration Register (RCR)
The RCR is a 16-bit read/write register used to select bus-read mode (synchronous or
asynchronous), and to configure synchronous burst read characteristics of the device.
To modify RCR settings, use the Configure Read Configuration Register command (see
Section 6.2, “Device Command Bus Cycles” on page 20).
Datasheet
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Order Number: 208033-02
P30-65nm SBC
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see Section 7.2, “Read Device Identifier” on page 22).
Upon power-up or exit from reset, the RCR defaults to asynchronous mode.
The RCR is shown in Table 13. The following sections describe each RCR bit function.
Table 13: Read Configuration Register Description
Read Configuration Register (RCR)
Read
Mode
RES
RM
R
15
14
Bit
Latency Count
WAIT
Polarity
Data
Output
Config
WAIT
Delay
Burst
Seq
CLK
Edge
RES
RES
Burst
Wrap
LC[3:0]
WP
DOC
WD
BS
CE
R
R
BW
10
9
8
7
6
5
4
3
13
12
11
Name
15
Read Mode (RM)
14
Reserved (R)
Set to 0. This bit cannot be altered by customer.
13:11
Latency Count (LC[2:0])
000
001
010
011
100
101
110
111
10
WAIT Polarity (WP)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
9
Data Output Configuration
(DOC)
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
8
WAIT Delay (WD)
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
6
5:4
3
2:0
BL[2:0]
2
=Code
=Code
=Code
=Code
=Code
=Code
=Code
=Code
0 =Reserved
1 =Linear (default)
Clock Edge (CE)
0 = Falling edge
1 = Rising edge (default)
Reserved (R)
Set to 0. This bit cannot be altered by customer.
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
11.2.1
0
0 reserved
1 reserved
2
3
4
5
6
7(default)
Burst Sequence (BS)
Burst Length (BL[2:0])
1
Description
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
7
Burst Length
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Read Mode (RCR.15)
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
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Apr 2010
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P30-65nm SBC
11.2.2
Latency Count (RCR[13:11])
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and Figure 10 shows the data output latency for the different
settings of LC. The maximum Latency Count for P30-65nm SBC device would be Code 4
based on the Max clock frequency specification of 52MHz, and there will be zero WAIT
States when bursting within the word line. Please also refer to Section 11.2.3, “End of
Word Line (EOWL) Considerations” on page 37 for more information on EOWL.
Refer to Table 14, “LC and Frequency Support” on page 36 for Latency Code Settings.
Figure 10: First-Access Latency Count
CLK [C]
Address [A]
Valid
Address
ADV# [V]
Code 0 (Reserved)
Valid
Output
DQ15-0 [D/Q]
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 1
(Reserved
DQ15-0 [D/Q]
Code 2
DQ15-0 [D/Q]
Code 3
DQ15-0 [D/Q]
Code 4
DQ15-0 [D/Q]
Code 5
DQ15-0 [D/Q]
Code 6
DQ15-0 [D/Q]
Code 7
DQ15-0 [D/Q]
Valid
Output
Table 14: LC and Frequency Support
Datasheet
36
Latency Count Settings
Frequency Support (MHz)
3
≤ 40
4
≤ 52
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Figure 11: Example Latency Count Setting Using Code 3
0
1
2
3
tData
4
CLK
CE#
ADV#
A[MAX:0]
A[MAX:1]
Address
Code 3
High-Z
D[15:0]
Data
R103
11.2.3
End of Word Line (EOWL) Considerations
The delay may occur when a burst sequence access crosses a 8-word boundary. That
is, A[3:1] of start address does not equal 0x0. Figure 12, “End of Wordline Timing
Diagram” on page 37 illustrates the end of wordline WAIT state(s), which occur after
the first 8-word boundary is reached. The number of data words and the number of
WAIT states is summarized in Table 15, “End of Wordline Data and WAIT state
Comparison” on page 38 for both P30-130nm and P30-65nm SBC devices.
Figure 12: End of Wordline Timing Diagram
Latency C ount
C LK
A [Max :1 ]
D Q[15 :0 ]
D ata
D ata
D ata
A D V#
OE#
W A IT
Datasheet
37
EOW L
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 15: End of Wordline Data and WAIT state Comparison
Latency Count
1
2
3
4
5
6
7
11.2.4
P30-130nm
P30-65nm SBC
Data States
WAIT States
Data States
WAIT States
Not Supported
4
4
4
4
4
4
Not Supported
0 to 1
0 to 2
0 to 3
0 to 4
0 to 5
0 to 6
Not Supported
Not Supported
8
8
8
8
8
Not Supported
Not Supported
0 to 2
0 to 3
0 to 4
0 to 5
0 to 6
WAIT Polarity (RCR.10)
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low
(default). WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
Table 16: WAIT Functionality Table
Condition
WAIT
Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
High-Z
1
CE# =’0’, OE# = ‘0’
Active
1
Synchronous Array Reads
Active
1
Synchronous Non-Array Reads
Active
1
All Asynchronous Reads
Deasserted
All Writes
High-Z
1
1,2
Notes:
1.
Active: WAIT is asserted until data becomes valid, then deasserts.
2.
When OE# = VIH during writes, WAIT = High-Z.
11.2.5
Data Output Configuration (RCR.9)
The Data Output Configuration (DOC) bit, RCR.9 determines whether a data word
remains valid on the data bus for one or two clock cycles. This period of time is called
the “data cycle”. When DOC is set, output data is held for two clocks (default). When
DOC is cleared, output data is held for one clock (see Figure 13, “Data Hold Timing” on
page 39). The processor’s data setup time and the flash memory’s clock-to-data output
delay should be considered when determining whether to hold output data for one or
two clocks. A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above:
20 ns + 4 ns ≤ 25 ns
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of
2 clock periods must be used.
Datasheet
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Apr 2010
Order Number: 208033-02
P30-65nm SBC
Figure 13: Data Hold Timing
CLK [C]
1 CLK
Data Hold
D[15:0] [Q]
2 CLK
Data Hold
D[15:0] [Q]
11.2.6
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
WAIT Delay (RCR.8)
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
11.2.7
Burst Sequence (RCR.7)
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Table 17 shows the synchronous burst sequence for all burst
lengths, as well as the effect of the Burst Wrap (BW) setting.
Table 17: Burst Sequence Word Ordering (Sheet 1 of 2)
Start
Addr.
(DEC)
Burst
Wrap
(RCR.3)
0
Burst Addressing Sequence (DEC)
4-Word Burst
(BL[2:0] = 0b001)
8-Word Burst
(BL[2:0] = 0b010)
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4…14-15
0-1-2-3-4-5-6-…
1
0
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5…15-0
1-2-3-4-5-6-7-…
2
0
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6…15-0-1
2-3-4-5-6-7-8-…
3
0
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7…15-0-1-2
3-4-5-6-7-8-9-…
4
0
4-5-6-7-0-1-2-3
4-5-6-7-8…15-0-1-2-3
4-5-6-7-8-9-10…
5
0
5-6-7-0-1-2-3-4
5-6-7-8-9…15-0-1-2-34
5-6-7-8-9-10-11…
6
0
6-7-0-1-2-3-4-5
6-7-8-9-10…15-0-1-23-4-5
6-7-8-9-10-11-12-…
7
0
7-0-1-2-3-4-5-6
7-8-9-10…15-0-1-2-34-5-6
7-8-9-10-11-12-13…
…
…
14-15-0-1-2…12-13
14-15-16-17-18-19-20…
15
0
15-0-1-2-3…13-14
15-16-17-18-19-20-21…
…
…
…
…
…
…
…
…
0
0
1
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4…14-15
0-1-2-3-4-5-6-…
Datasheet
39
…
…
14
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 17: Burst Sequence Word Ordering (Sheet 2 of 2)
1
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5…15-16
1-2-3-4-5-6-7-…
2
1
3
1
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6…16-17
2-3-4-5-6-7-8-…
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7…17-18
3-4-5-6-7-8-9-…
4
5
1
4-5-6-7-8-9-10-11
4-5-6-7-8…18-19
4-5-6-7-8-9-10…
1
5-6-7-8-9-10-11-12
5-6-7-8-9…19-20
5-6-7-8-9-10-11…
6
1
6-7-8-9-10-11-12-13
6-7-8-9-10…20-21
6-7-8-9-10-11-12-…
7
1
7-8-9-10-11-12-13-14
7-8-9-10-11…21-22
7-8-9-10-11-12-13…
…
…
…
…
1
14-15-16-17-18…28-29
14-15-16-17-18-19-20…
15
1
15-16-17-18-19…29-30
15-16-17-18-19-20-21…
11.2.8
…
…
14
Clock Edge (RCR.6)
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
11.2.9
Burst Wrap (RCR.3)
The Burst Wrap (BW) bit determines whether 4, 8, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries.
When BW is set, burst wrapping does not occur (default). When BW is cleared, burst
wrapping occurs.
11.2.10
Burst Length (RCR[2:0])
The Burst Length bits (BL[2:0]) select the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word or
continuous word.
Continuous burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 17, “Burst Sequence Word Ordering” on page 39). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
11.3
One-Time Programmable (OTP) Registers
The device contains 17 OTP Registers that can be used to implement system security
measures and/or device identification. Each OTP Register can be individually locked.
The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit
number. The upper 64-bit segment, as well as the other sixteen 128-bit OTP Registers,
are blank. Users can program these registers as needed. Once programmed, users can
then lock the OTP Register(s) to prevent additional bit programming (see Figure 14,
“OTP Register Map” on page 41).
Each OTP Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated OTP Register can only be read; it can no longer be
programmed. Each OTP Register can be accessed multiple times to program individual
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Apr 2010
Order Number: 208033-02
P30-65nm SBC
bits, as long as the register remains unlocked. Additionally, because the Lock Register
bits themselves are OTP, when programmed, Lock Register bits cannot be erased.
Therefore, when a OTP Register is locked, it cannot be unlocked.
Figure 14: OTP Register Map
0x109
128-bit OTP Register 16
(User-Programmable)
0x102
0x91
128-bit OTP Register 1
(User-Programmable)
0x8A
Lock Register 1
0x89
0x88
0x85
0x84
0x81
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
1
0
64-bit Segment
(User-Programmable)
128-Bit OTP Register 0
64-bit Segment
(Factory-Programmed)
Lock Register 0
0x80
11.3.1
15 14 13 12 11 10 9
8
7
6
5
4
3
2
Reading the OTP Registers
The OTP Registers can be read from OTP-RA address. To read the OTP Register, first
issue the Read Device Identifier command at OTP-RA address to place the device in the
Read Device Identifier state (see Section 6.2, “Device Command Bus Cycles” on
page 20). Next, perform a read operation using the address offset corresponding to the
register to be read. Table 8, “Device Identifier Information” on page 22 shows the
address offsets of the OTP Registers and Lock Registers. OTP Registers and Lock
Registers data is read 16 bits at a time.
Datasheet
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P30-65nm SBC
11.3.2
Programming the OTP Registers
To program an OTP Register, first issue the OTP Register Program Setup command at
the device base address plus the offset address of the desired OTP Register location
(OTP-RA: see Figure 14, “OTP Register Map” on page 41). Next, write the desired OTP
Register data to the same OTP Register address. See Section 6.2, “Device Command
Bus Cycles” on page 20.
The device programs the 64-bit and Sixteen 128-bit user-programmable OTP Register
data 16 bits at a time (see Figure 40, “OTP Register Programming Flowchart” on
page 81). Issuing the OTP Register Program Setup command outside of the OTP
Register’s address space causes a program error (SR.4 set). Attempting to program a
locked OTP Register causes a program error (SR.4 set) and a lock error (SR.1 set).
11.3.3
Locking the OTP Registers
Each OTP Register can be locked by programming its respective lock bit in the Lock
Register. To lock an OTP Register, program the corresponding bit in the Lock Register by
issuing the Lock Register Program Setup command, followed by the desired Lock
Register data (see Section 6.2, “Device Command Bus Cycles” on page 20). The
physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1.
These addresses are used when programming the lock registers (see Table 8, “Device
Identifier Information” on page 22).
Bit 0 of Lock Register 0 is already programmed during the manufacturing process at
Numonyx factory, locking the lower half segment of the first 128-bit OTP Register. Bit 1
of Lock Register 0 can be programmed by user to the upper half segment of the first
128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to
be left as ‘1’ such that the data programmed is 0xFFFD.
Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each
bit of Lock Register 1 corresponds to a specific 128-bit OTP Register; e.g.,
programming LR1.0 locks the corresponding OTP Register 1.
Caution:
Datasheet
42
After being locked, the OTP Registers cannot be unlocked.
Apr 2010
Order Number: 208033-02
P30-65nm SBC
12.0
Power and Reset Specifications
12.1
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
12.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 18: Power and Reset
Num
Symbol
P1
tPLPH
P2
tPLRH
P3
tVCCPH
Notes:
1.
2.
3.
4.
5.
6.
7.
Parameter
Min
Max
Unit
Notes
100
-
ns
1,2,3,4
RST# low to device reset during erase
-
25
RST# low to device reset during program
-
25
µs
1,3,4,7
60
-
RST# pulse width low
VCC Power valid to RST# de-assertion (high)
1,3,4,7
1,4,5,6
These specifications are valid for all device versions (packages and speeds).
The device may reset if tPLPH is < tPLPH Min, but this is not guaranteed.
Not applicable if RST# is tied to VCC.
Sampled, but not 100% tested.
When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.
When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.
Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
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P30-65nm SBC
Figure 15: Reset Operation Waveforms
P1
(A) Reset during
read mode
RST# [P]
VIH
VIL
P2
(B) Reset during
program or block erase
P1 ≤ P2
RST# [P]
RST# [P]
Abort
Complete
R5
VIH
VIL
P2
(C) Reset during
program or block erase
P1 ≥ P2
R5
Abort
Complete
R5
VIH
VIL
P3
(D) VCC Power-up to
RST# high
12.3
VCC
VCC
0V
Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power
supply current considerations are: 1) standby current levels; 2) active current levels;
and 3) transient peaks produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of
these internal activities produce transient signals. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct
de-coupling capacitor selection suppress transient voltage peaks.
Because flash memory devices draw their power from VCC, VPP, and VCCQ, each power
connection should have a 0.1 µF ceramic capacitor to ground. High-frequency,
inherently low-inductance capacitors should be placed as close as possible to package
leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
Datasheet
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Order Number: 208033-02
P30-65nm SBC
13.0
Maximum Ratings and Operating Conditions
13.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the Absolute Maximum Ratings may cause permanent
damage. These are stress ratings only.
Table 19: Absolute Maximum Ratings
Parameter
Temperature under bias
Storage temperature
Maximum Rating
Notes
–40°C to +85°C
-
–65°C to +125°C
-
Voltage on any signal (except VCC, VPP and VCCQ)
–0.5V to +4.1V
1
VPP voltage
–0.2V to +10.0V
1,2,3
VCC voltage
–0.2V to +2.5V
1
VCCQ voltage
–0.2V to +4.1V
1
100mA
4
Output short circuit current
Notes:
1.
Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5V on input/output signals and –0.2V on
VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0V for periods less than 20ns. Maximum DC
voltage on VCC is VCC + 0.5V, which, during transitions, may overshoot to VCC + 2.0V for periods less than 20ns.
Maximum DC voltage on input/output signals and VCCQ is VCCQ + 0.5V, which, during transitions, may overshoot to
VCCQ + 2.0V for periods less than 20ns.
2.
Maximum DC voltage on VPP may overshoot to +11.5V for periods less than 20ns.
3.
Program/erase voltage is typically 1.7V – 2.0V. 9.0V can be applied for 80 hours maximum total, to any blocks for 1000
cycles maximum. 9.0V program/erase voltage may reduce block cycling capability.
4.
Output shorted for no more than one second. No more than one output shorted at a time.
13.2
Operating Conditions
Note:
Operation beyond the Operating Conditions is not recommended and extended
exposure beyond the Operating Conditions may affect device reliability.
Table 20: Operating Conditions
Symbol
TC
VCC
VCCQ
Parameter
Operating Temperature
VCC Supply Voltage
I/O Supply Voltage
CMOS inputs
TTL inputs
Max
Unit
Notes
–40
+85
°C
1
1.7
2.0
1.7
3.6
2.4
3.6
0.9
3.6
8.5
9.5
-
80
VPP = VPPL
100,000
-
Main Blocks
VPP = VPPH
-
1000
Parameter Blocks
VPP = VPPH
-
2500
VPPL
VPP Voltage Supply (Logic Level)
VPPH
Buffered Enhanced Factory Programming VPP
tPPH
Maximum VPP Hours
VPP = VPPH
Main and Parameter Blocks
Block
Erase
Cycles
Min
V
Hours
2
Cycles
Notes:
1.
TC = Case Temperature.
2.
In typical operation VPP program voltage is VPPL.
Datasheet
45
Apr 2010
Order Number:208033-02
P30-65nm SBC
14.0
Electrical Specifications
14.1
DC Current Characteristics
Table 21: DC Current Characteristics (Sheet 1 of 2)
Sym
Parameter
ILI
Input Load Current
ILO
Output
Leakage
Current
ICCS,
ICCD
ICCR
ICCW,
ICCE
CMOS
Inputs
(VCCQ =
1.7V - 3.6V)
DQ[15:0], WAIT
Max
Typ
Max
-
±1
-
±2
Test Conditions
µA
VCC = VCC Max
VCCQ = VCCQ Max
VIN = VCCQ or VSS
µA
VCC = VCC Max
VCCQ = VCCQ Max
VIN = VCCQ or VSS
µA
VCC = VCC Max
VCCQ = VCC Max
CE# =VCCQ
RST# = VCCQ (for ICCS)
RST# = VSS (for ICCD)
WP# = VIH
±1
-
±10
128-Mbit
30
55
710
2000
64-Mbit
30
55
710
2000
Asynchronous SingleWord f = 5MHz (1 CLK)
20
25
-
-
mA
8-Word Read
Page-Mode Read
f = 13MHz (17 CLK)
12
16
-
-
mA
8-Word Read
16
19
-
-
mA
4-Word Read
19
22
-
-
mA
8-Word Read
22
26
-
-
mA
16-Word
Read
23
28
-
-
mA
Continuous
Read
Synchronous Burst
f = 52MHz, LC=4
µA
CE# = VCCQ; suspend in
progress
1,3,4
5
µA
VPP = VPPL, suspend in progress
1,3,7
2
15
µA
VPP = VPPL
0.10
0.05
0.10
10
5
10
0.05
0.10
0.05
0.10
5
10
5
10
33
128-Mbit
30
55
710
2000
64-Mbit
30
55
710
2000
0.2
5
0.2
2
15
0.05
5
IPPES
IPPR
VPP Read
IPPW
VPP Program Current
IPPE
VPP Erase Current
1
1,3,5
50
26
VPP Standby Current,
VPP Program Suspend Current,
VPP Erase Suspend Current
1,2
1,3,5
35
33
IPPS,
IPPWS,
1,6
VPP = VPPH, Pgm/Ers in progress
50
26
VCC Program
Suspend Current,
VCC Erase
Suspend Current
VCC = VCCMax
CE# = VIL
OE# = VIH
Inputs: VIL or
VIH
Notes
VPP = VPPL, Pgm/Ers in progress
35
VCC Program Current,
VCC Erase Current
ICCWS,
ICCES
Datasheet
46
Typ
Unit
-
VCC Standby,
Power-Down
Average
VCC
Read
Current
TTL Inputs
(VCCQ =
2.4V - 3.6V)
mA
mA
mA
1,3
VPP = VPPL, program in progress
VPP = VPPH, program in progress
VPP = VPPL, erase in progress
VPP = VPPH, erase in progress
3
3
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 21: DC Current Characteristics (Sheet 2 of 2)
Sym
Parameter
IPPBC
Notes:
1.
2.
3.
4.
5.
6.
7.
CMOS
Inputs
(VCCQ =
1.7V - 3.6V)
VPP Blank Check
TTL Inputs
(VCCQ =
2.4V - 3.6V)
Typ
Max
Typ
Max
0.05
0.10
0.05
0.10
5
10
5
10
Unit
mA
Test Conditions
VPP = VPPL, erase in progress
VPP = VPPH, erase in progress
Notes
3
All currents are RMS unless noted. Typical values at typical VCC, TC = +25°C.
ICCS is the average current measured over any 5ms time interval 5µs after CE# is deasserted.
Sampled, not 100% tested.
ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR.
ICCW, ICCE measured over typical or max times specified in Section 15.5, “Program and Erase
Characteristics” on page 58.
if VIN > VCC the input load current increases to 10µA max.
the IPPS,IPPWS,IPPES Will increase to 200µA when VPP/WP# is at VPPH.
14.2
DC Voltage Characteristics
Table 22: DC Voltage Characteristics
Sym
Parameter
CMOS Inputs
(VCCQ = 1.7V – 3.6V)
TTL Inputs (1)
(VCCQ = 2.4V – 3.6V)
Min
Max
Min
Max
Unit
Test Conditions
Notes
VIL
Input Low Voltage
-0.5
0.4
-0.5
0.6
V
-
VIH
Input High Voltage
VCCQ – 0.4
VCCQ + 0.5
2.0
VCCQ + 0.5
V
-
VOL
Output Low Voltage
-
0.2
-
0.2
V
VCC = VCC Min
VCCQ = VCCQ Min
IOL = 100µA
-
VOH
Output High Voltage
VCCQ – 0.2
-
VCCQ – 0.2
-
V
VCC = VCC Min
VCCQ = VCCQ Min
IOH = –100µA
-
VPPLK
VPP Lock-Out Voltage
-
0.4
-
0.4
V
-
3
VLKO
VCC Lock Voltage
1.0
-
1.0
-
V
-
-
VLKOQ
VCCQ Lock Voltage
0.9
-
0.9
-
V
-
-
2
Notes:
1.
Synchronous read mode is not supported with TTL inputs.
2.
VIL can undershoot to –0.4V and VIH can overshoot to VCCQ + 0.4V for durations of 20ns or less.
3.
VPP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
Datasheet
47
Apr 2010
Order Number:208033-02
P30-65nm SBC
15.0
AC Characteristics
15.1
AC Test Conditions
Figure 16: AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
Note:
IO_REF.WMF
AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input
rise and fall times (10% to 90%) < 5ns. Worst case speed occurs at VCC = VCCMin.
Figure 17: Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Notes:
1.
See the following table for component values.
2.
Test configuration component value for worst case speed conditions.
3.
CL includes jig capacitance
.
Table 23: Test Configuration Component Value for Worst Case Speed Conditions
Test Configuration
VCCQ Min Standard Test
Datasheet
48
CL (pF)
30
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Figure 18: Clock Input AC Waveform
R201
CLK [C]
VIH
VIL
R202
R203
CLKINPUT.WMF
15.2
Capacitance
Table 24: Capacitance
Symbol
Parameter
Signals
Min
Typ
Max
Unit
CIN
Input Capacitance
Address, CE#,
WE#, OE#,
RST#, CLK,
ADV#, WP#
3
7
8
pF
COUT
Output Capacitance
Data, WAIT
3
5
6
pF
Condition
Notes
Typ temp = 25°C,
Max temp = 85°C,
VCC = (0V - 2.0V),
VCCQ = (0V - 3.6V)
1
Notes:
1.
Sampled, not 100% tested.
Datasheet
49
Apr 2010
Order Number:208033-02
P30-65nm SBC
15.3
AC Read Specifications
Table 25: AC Read Specifications (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Easy BGA/QUAD+
65
-
ns
-
TSOP
75
-
ns
-
Easy BGA/QUAD+
-
65
ns
-
TSOP
-
75
ns
-
Easy BGA/QUAD+
-
65
ns
-
TSOP
-
75
ns
-
Asynchronous Specifications
R1
tAVAV
Read cycle time
R2
tAVQV
Address to output valid
R3
tELQV
CE# low to output valid
R4
tGLQV
OE# low to output valid
-
25
ns
1,2
R5
tPHQV
RST# high to output valid
-
150
ns
1
R6
tELQX
CE# low to output in low-Z
0
-
ns
1,3
R7
tGLQX
OE# low to output in low-Z
0
-
ns
1,2,3
R8
tEHQZ
CE# high to output in high-Z
-
20
ns
R9
tGHQZ
OE# high to output in high-Z
-
15
ns
Output hold from first occurring address, CE#, or OE#
change
0
-
ns
1,3
R10
tOH
R11
tEHEL
CE# pulse width high
17
-
ns
R12
tELTV
CE# low to WAIT valid
-
17
ns
R13
tEHTZ
CE# high to WAIT high-Z
-
20
ns
1,3
R15
tGLTV
OE# low to WAIT valid
-
17
ns
1
R16
tGLTX
OE# low to WAIT in low-Z
0
-
ns
R17
tGHTZ
OE# high to WAIT in high-Z
-
20
ns
1
1,3
Latching Specifications
R101
tAVVH
Address setup to ADV# high
10
-
ns
R102
tELVH
CE# low to ADV# high
10
-
ns
R103
tVLQV
ADV# low to output valid
Easy BGA/QUAD+
-
65
ns
TSOP
-
75
ns
R104
tVLVH
ADV# pulse width low
10
-
ns
R105
tVHVL
ADV# pulse width high
10
-
ns
R106
tVHAX
Address hold from ADV# high
9
-
ns
R108
tAPA
Page address access
-
25
ns
R111
tPHVH
30
-
ns
RST# high to ADV# high
1
1,4
1
Clock Specifications
R200
fCLK
CLK frequency
R201
tCLK
CLK period
R202
tCH/CL
CLK high/low time
R203
tFCLK/RCLK
CLK fall/rise time
Datasheet
50
Easy BGA/QUAD+
-
52
MHz
TSOP
-
40
MHz
Easy BGA/QUAD+
19.2
-
ns
TSOP
25
-
ns
Easy BGA/QUAD+
5
-
ns
TSOP
9
-
ns
0.3
3
ns
1,3,5,6
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 25: AC Read Specifications (Sheet 2 of 2)
Num
Symbol
Synchronous
Parameter
Min
Max
Unit
Notes
Specifications(5)
R301
tAVCH/L
Address setup to CLK
9
-
ns
R302
tVLCH/L
ADV# low setup to CLK
9
-
ns
R303
tELCH/L
CE# low setup to CLK
9
-
ns
R304
tCHQV / tCLQV
Easy BGA/QUAD+
-
17
ns
TSOP
-
20
ns
R305
tCHQX
Output hold from CLK
Easy BGA/QUAD+
3
-
ns
1,6
TSOP
5
-
ns
1,6
R306
tCHAX
Address hold from CLK
CLK to output valid
Easy BGA/QUAD+
R307
tCHTV
CLK to WAIT valid
R311
tCHVL
CLK Valid to ADV# Setup
R312
tCHTX
WAIT Hold from CLK
TSOP
1,6
10
-
ns
1,4,6
-
17
ns
1,6
-
20
ns
1,6
3
-
ns
1
Easy BGA/QUAD+
3
-
ns
1,6
TSOP
5
-
ns
1,6
Notes:
1.
See Figure 16, “AC Input/Output Reference Waveform” on page 48 for timing measurements and
max allowable input slew rate.
2.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3.
Sampled, not 100% tested.
4.
Address hold in synchronous burst read mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5.
Synchronous burst read mode is not supported with TTL level inputs.
6.
Applies only to subsequent synchronous reads.
Figure 19: Asynchronous Single-Word Read (ADV# Low)
R1
R2
Address [A]
ADV#[V]
R3
R8
CE# [E]
R4
R9
OE# [G]
R15
R17
WAIT [T]
R7
R6
Data [D/Q]
R5
RST# [P]
Note:
WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Datasheet
51
Apr 2010
Order Number:208033-02
P30-65nm SBC
Figure 20: Asynchronous Single-Word Read (ADV# Latch)
Address[A]
A[3:1][A]
ADV#[V]
R1
R2
R101
R105
R104
R106
R3
CE#[E]
R8
R4
OE#[G]
R9
R15
WAIT[T]
R17
R6
R7
R10
Data [D/Q]
Note:
WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Figure 21: Asynchronous Page-Mode Read Timing
R2
A[Max:4] [A]
Valid Address
R10
A[3:1]
0
R10
1
R10
2
R101
R 105
R10
F
R106
ADV# [V]
R3
R8
CE# [E]
R4
R9
OE# [G]
WAIT [T]
R6
DATA [D/Q]
Note:
Q1
R 108
R 108
R 108
Q2
Q3
Q8
R13
WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Datasheet
52
Apr 2010
Order Number: 208033-02
P30-65nm SBC
.
Figure 22: Synchronous Single-Word Array or Non-array Read Timing
Latency Count
R301
R306
CLK [C]
R2
Address [A]
R101
R106
R105
R104
ADV# [V]
R303
R102
R3
R8
CE# [E]
R7
R9
OE# [G]
R15
R307
R312 R17
WAIT [T]
R4
R304
R305
Data [D/Q]
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
Figure 23: Continuous Burst Read, showing an Output Delay Timing
R301
R302
R306
R304
R304
R304
CLK [C]
R2
R101
Address [A]
R106
R105
ADV# [V]
R303
R102
R3
CE# [E]
OE# [G]
R15
R307
R312
WAIT [T]
R304
R4
R7
R305
R305
R305
R305
Data [D/Q]
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned. See Section 11.2.3, “End of Word Line (EOWL) Considerations” on
page 37 for more information.
Datasheet
53
Apr 2010
Order Number:208033-02
P30-65nm SBC
Figure 24: Synchronous Burst-Mode Four-Word Read Timing
y
R302
R301
R306
CLK [C]
R2
R101
A
Address [A]
R105
R102
R106
ADV# [V]
R303
R3
R8
CE# [E]
R9
OE# [G]
R15
R17
R307
WAIT [T]
R4
R7
R304
Data [D/Q]
Note:
R304
R305
Q0
R10
Q1
Q2
Q3
WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR.10=0, WAIT asserted low).
15.4
AC Write Specifications
Table 26: AC Write Specifications (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
W1
tPHWL
RST# high recovery to WE# low
W2
tELWL
CE# setup to WE# low
W3
tWLWH
WE# write pulse width low
50
-
ns
1,2,4
W4
tDVWH
Data setup to WE# high
50
-
ns
1,2,12
W5
tAVWH
Address setup to WE# high
50
-
ns
W6
tWHEH
CE# hold from WE# high
0
-
ns
W7
tWHDX
Data hold from WE# high
0
-
ns
W8
tWHAX
Address hold from WE# high
0
-
ns
W9
tWHWL
WE# pulse width high
W10
tVPWH
VPP setup to WE# high
W11
tQVVL
W12
150
-
ns
1,2,3
0
-
ns
1,2,3
1,2
20
-
ns
200
-
ns
1,2,5
VPP hold from Status read
0
-
ns
tQVBL
WP# hold from Status read
0
-
ns
W13
tBHWH
WP# setup to WE# high
200
-
ns
W14
tWHGL
WE# high to OE# low
0
-
ns
1,2,9
W16
tWHQV
WE# high to read valid
tAVQV + 35
-
ns
1,2,3,6,10
0
-
ns
1,2,3,6,8
1,2,3,7
1,2,3,7
Write to Asynchronous Read Specifications
W18
Datasheet
54
tWHAV
WE# high to Address valid
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 26: AC Write Specifications (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Write to Synchronous Read Specifications
W19
tWHCH/L
WE# high to Clock valid
19
-
ns
W20
tWHVH
WE# high to ADV# high
19
-
ns
1,2,3,6,10
Write Specifications with Clock Active
W21
tVHWL
ADV# high to WE# low
-
27
ns
W22
tCHWL
Clock high to WE# low
-
27
ns
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
1,2,3,11
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).
tWHVH or tWHCH/L must be met when transiting from a write cycle to a synchronous burst read.
VPP and WP# should be at a valid level until erase or program success is determined.
This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20
for synchronous read.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20ns.
Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
This specification must be complied with by customer’s writing timing. The result would be unpredictable if any violation
to this timing specification.
Figure 25: Write-to-Write Timing
W5
W8
W5
W8
Address [A]
W2
W6
W2
W6
CE# [E]
W3
W9
W3
WE# [W]
OE# [G]
W4
W7
W4
W7
Data [D/Q]
W1
RST# [P]
Datasheet
55
Apr 2010
Order Number:208033-02
P30-65nm SBC
Figure 26: Asynchronous Read-to-Write Timing
R1
R2
W5
W8
Address [A]
R3
R8
CE# [E]
R4
R9
OE# [G]
W2
W3
W6
WE# [W]
R15
R17
WAIT [T]
R7
W7
R6
R10
W4
Q
Data [D/Q]
D
R5
RST# [P]
Note:
WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted.
Figure 27: Write-to-Asynchronous Read Timing
W5
W8
R1
Address [A]
ADV# [V]
W2
W6
R10
CE# [E]
W3
W18
WE# [W]
W14
OE# [G]
R15
R17
WAIT [T]
R4
W4
Data [D/Q]
W7
D
R2
R3
R8
R9
Q
W1
RST# [P]
Datasheet
56
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Figure 28: Synchronous Read-to-Write Timing
Latency Count
R301
R302
R306
CLK [C]
R2
R101
W5
W18
Address [A]
R105
R102
R106
R104
ADV# [V]
R303
R11
R3
R13
W6
CE# [E]
R4
R8
OE# [G]
W22
W2
W21
W21
W22
W15
W8
W3
W9
WE#[W]
R16
R307
R312
WAIT [T]
R304
R7
R305
Note:
W7
Q
Data [D/Q]
D
D
WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low). Clock is
ignored during write operation.
Figure 29: Write-to-Synchronous Read Timing
Latency Count
R302
R301
R2
CLK[C]
W5
W8
R306
Address [A]
R106
R104
ADV#[V]
W6
W2
R303
R11
CE# [E]
W18
W19
W20
W3
WE# [W]
R4
OE# [G]
R15
R307
WAIT [T]
W7
W4
Data [D/Q]
R304
R305
R304
R3
D
Q
Q
W1
RST# [P]
Note:
WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low).
Datasheet
57
Apr 2010
Order Number:208033-02
P30-65nm SBC
Program and Erase Characteristics
15.5
Table 27: Program and Erase Specifications
Num
Symbol
VPPH
VPPL
Parameter
Min
Typ
Max
Min
Typ
Max
175
-
40
175
Unit
Notes
µs
1
µs
1
Conventional Word Programming
W200
tPROG/W
Program
Time
Single word
-
40
Buffered Programming
W250
tPROG/Buffer
Program
Time
Aligned 16-Wd, BP time
(32 Byte)
-
70
200
-
70
200
Aligned 32-Wd, BP time
(64 Byte)
-
85
200
-
85
200
one full buffer (256
Words)
-
284
1280
-
160
800
Buffered Enhanced Factory Programming
W451
tBEFP/B
W452
tBEFP/Setup
Program
Single byte
BEFP Setup
n/a
n/a
n/a
-
0.31
-
n/a
n/a
n/a
10
-
-
0.5
4
µs
1,2
1
Erase and Suspend
W501
tERS/B
W600
tSUSP/P
W601
tSUSP/E
W602
tERS/SUSP
Erase Time
Suspend
Latency
128-KByte Array Block
-
0.5
4
32-KByte Parameter
Block
-
0.4
2.5
-
0.4
2.5
Program suspend
-
20
25
-
20
25
Erase suspend
-
20
25
-
20
25
-
500
-
-
500
-
3.2
-
-
3.2
-
Erase to Suspend
s
1
µs
1,3
Blank Check
W702
tBC/AB
blank
check
Array Block
-
ms
Notes:
1.
Typical values measured at TC = +25°C and nominal voltages. Performance numbers are valid for all speed versions.
Excludes system overhead. Sampled, but not 100% tested.
2.
Averaged over entire device.
3.
W602 is the typical time between an initial block erase or erase resume command and the a subsequent erase suspend
command. Violating the specification repeatedly during any particular block erase may cause erase failures.
Datasheet
58
Apr 2010
Order Number: 208033-02
P30-65nm SBC
16.0
Ordering Information
Figure 30: Decoder for discrete Products
J S 2 8 F 1 2 8 P 3 0 B F 7 5 *
Device Features*
Package Designator
JS = 56- Lead TSOP, lead- free
RC = 64- Ball Easy BGA, leaded
PC = 64- Ball Easy BGA, lead- free
Speed
65ns
75ns
Device Details
Product Line Designator
F = 65 nm lithography
28F = Numonyx ® Flash Memory
Parameter Location
B = Bottom Parameter
T = Top Parameter
Device Density
128 = 128-Mbit
640 = 64 - Mbit
Product Family
®
TM
P 30 = Numonyx Axcell P30 Flash Memory
V CC = 1 . 7 – 2 . 0 V
V CCQ = 1 . 7 – 3. 6 V
.
Table 28: Valid Combinations for Discrete Products
Note:
Datasheet
59
64-Mbit
128-Mbit
JS28F640P30BF75*
JS28F128P30BF75*
JS28F640P30TF75*
JS28F128P30TF75*
PC28F640P30BF65*
PC28F128P30BF65*
PC28F640P30TF65*
PC28F128P30TF65*
RC28F640P30BF65*
RC28F128P30BF65*
RC28F640P30TF65*
RC28F128P30TF65*
The last digit is randomly assigned to cover packing media and/or features or other specific configuration. For
further information on ordering products or for product part numbers, go to:
http://www.numonyx.com/en-US/MemoryProducts/Pages/PartNumberLookup.aspx.
Apr 2010
Order Number:208033-02
P30-65nm SBC
.
Figure 31: Decoder for SCSP package
P F 4 8 F 3 0 0 0 P 0 Z B Q E *
Device Features*
Package Designator
RD = SCSP, leaded
Device Details
PF = SCSP, lead-free
E = 65nm lithography
Ballout Descriptor
Product Designator
®
48F = Numonyx Flash Memory Only
Q = QUAD+ ballout
0 = Discrete ballout
Device Density
Parameter Location
3 = 128- Mbit
0 = No die
B = Bottom Parameter
T = Top Parameter
Product Family
I/ O Voltage, CE # Configuration
P = Numonyx ® Axcell™ Flash Memory
0 = No second flash die
Z = Individual Chip Enable(s)
VCC = 1. 7 to 2. 0 V
VCCQ = 1. 7 to 3. 6 V
Table 29: Valid Combinations for QUAD+ Package Products
128-Mbit
PF48F3000P0ZBQE*
PF48F3000P0ZTQE*
RD48F3000P0ZBQE*
RD48F3000P0ZTQE*
Note:
Datasheet
60
The last digit is randomly assigned to cover packing media and/or features or other specific configuration. For
further information on ordering products or for product part numbers, go to:
http://www.numonyx.com/en-US/MemoryProducts/Pages/PartNumberLookup.aspx.
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Appendix A Supplemental Reference Information
A.1
Common Flash Interface
The Common Flash Interface (CFI) is part of an overall specification for multiple
command-set and control-interface descriptions. This appendix describes the database
structure containing the data returned by a read operation after issuing the Read CFI
command (see Section 6.2, “Device Command Bus Cycles” on page 20). System
software can parse this database structure to obtain information about the flash device,
such as block size, density, bus width, and electrical specifications. The system
software will then know which command set(s) to use to properly perform flash writes,
block erases, reads and otherwise control the flash device.
A.1.1
Query Structure Output
The Query database allows system software to obtain information for controlling the
flash device. This section describes the device’s CFI-compliant interface that allows
access to Query data.
Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical
offset value is the address relative to the maximum bus width supported by the device.
On this family of devices, the Query table device starting address is a 10h, which is a
word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0)
and 00h in the high byte (DQ15-8).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of wordwide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs have 00h on
the upper byte in this mode.
Table 30: Summary of Query Structure Output as a Function of Device and Mode
Device
Device Addresses
Datasheet
61
Hex
Offset
00010:
00011:
00012:
Hex
Code
51
52
59
ASCII
Value
"Q"
"R"
"Y"
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 31: Example of Query Structure Output of x16 Devices
Offset
Hex Code
AX-A1
A.1.2
Value
D15-D0
00010h
0051
“Q”
00011h
0052
“R”
00012h
0059
“Y”
00013h
P_IDLO
00014h
P_IDHI
00015h
PLO
00016h
PHI
00017h
A_IDLO
00018h
A_IDHI
...
...
PrVendor ID#
PrVendor TblAdr
AltVendor ID#
...
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or database. Table 32 summarizes the structure sub-sections and address
locations.
Table 32: Query Structure
00001-Fh
00010h
0001Bh
00027h
P(3)
Note:
1.
2.
3.
Reserved
CFI query identification string
System interface information
Device geometry definition
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
Vendor-defined additional information specific
Primary Numonyx-specific Extended Query
to the Primary Vendor Algorithm
Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of
device bus width and mode.
BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord).
Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table.
A.1.3
Read CFI Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
Datasheet
62
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 33: CFI Identification
Offset
Length
10h
3
Query-unique ASCII string “QRY“
13h
2
15h
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
17h
2
19h
2
Datasheet
63
Description
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
Hex
Add. Code Value
10:
--51
"Q"
11:
--52
"R"
12:
--59
"Y"
13:
--01
14:
--00
15:
--0A
16:
--01
17:
--00
18:
--00
19:
--00
1A:
--00
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 34: System Interface Information
Add
Hex
Code
Value
VCC logic supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1B:
--17
1.7V
1
VCC logic supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1C:
--20
2.0V
1Dh
1
VPP [programming] supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
1D:
--85
8.5V
1Eh
1
VPP [programming] supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
1E:
--95
9.5V
1Fh
1
“n” such that typical single word program time-out = 2n
1F:
--06
64µs
20:
--09
512µs
21:
--09
0.5s
Offset
Length
1Bh
1
1Ch
n
µ-sec
µ-sec
20h
1
“n” such that typical full buffer write time-out = 2
21h
1
“n” such that typical block erase time-out = 2n m-sec
22h
Datasheet
64
Description
n
1
“n” such that typical full chip erase time-out = 2 m-sec
22:
--00
NA
23h
1
“n” such that maximum word program time-out = 2n times
typical
23:
--02
256µs
24h
1
“n” such that maximum buffer write time-out = 2n times
typical
24:
--02
2048µs
25h
1
“n” such that maximum block erase time-out = 2n times
typical
25:
--03
4s
26h
1
“n” such that maximum chip erase time-out = 2n times typical
26:
--00
NA
Apr 2010
Order Number: 208033-02
P30-65nm SBC
A.1.4
Device Geometry Definition
Table 35: Device Geometry Definition
Offset
Length
27h
1
Description
“n” such that device size = 2n in number of bytes
Add
Hex
Code
27:
See Table Below
Value
Flash device interface code assignment:
"n" such that n+1 specifies the bit field that represents the flash device width
capabilities as described in the table:
28h
2
2Ah
2Ch
7
6
5
4
3
2
1
0
_
_
_
_
x64
x32
x16
x8
15
14
13
12
11
10
9
8
_
_
_
_
_
_
_
_
2
“n” such that maximum number of bytes in write buffer = 2n
1
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or more contiguous
same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4
Erase Block Region 1 Information
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
28:
--01
29:
--00
2A:
--09
2B:
--00
2C:
x16
512
See Table Below
2D:
2D
2E:
2F:
See Table Below
30:
31:
31h
4
Erase Block Region 2 Information
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
32:
33:
See Table Below
34:
35:
35h
4
36:
Reserved for future erase block region information
37:
See Table Below
38:
Address
64-Mbit
--B
--T
128-Mbit
--B
--T
Address
64-Mbit
--B
128-Mbit
--T
--02
--B
--00
--T
27:
--17
--17
--18
--18
30:
--00
--02
28:
--01
--01
--01
--01
31:
--3E
--03
--7E
--03
29:
--00
--00
--00
--00
32:
--00
--00
--00
--00
2A
--09
--09
--09
--09
33:
--00
--80
--00
--80
2B
--00
--00
--00
--00
34:
--02
--00
--02
--00
2C:
--02
--02
--02
--02
35:
--00
--00
--00
--00
2D:
--03
--3E
--03
--7E
36:
--00
--00
--00
--00
2E:
--00
--00
--00
--00
37:
--00
--00
--00
--00
2F:
--80
-00
--80
--00
38:
--00
--00
--00
--00
Datasheet
65
Apr 2010
Order Number:208033-02
P30-65nm SBC
A.1.5
Numonyx-Specific Extended Query Table
Table 36: Primary Vendor-Specific Extended Query
Offset(1) Length
Description
P = 10Ah
(Optional flash features and com m ands)
(P+0)h
3
Primary extended query table
(P+1)h
Unique ASCII string “PRI“
(P+2)h
(P+3)h
1
Major version number, ASCII
(P+4)h
1
Minor version number, ASCII
(P+5)h
4
Optional feature and command support (1=yes, 0=no)
bits 10–31 are reserved; undefined bits are “0.” If bit 31 is
(P+6)h
“1” then another 31 bit field of Optional features follows at
(P+7)h
the end of the bit–30 field.
(P+8)h
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
bit 8 Synchronous read supported
bit 9 Simultaneous operations supported
bit 10 Extended Flash Array Blocks supported
bit 11 Permanent Block Locking of up to Full Main Array supported
bit 12 Permanent Block Locking of up to Partial Main Array supported
bit 30 CFI Link(s) to follow
bit 31 Another "Optional Features" field to follow
(P+9)h
1
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
(P+A)h
2
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
(P+B)h
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Dow n Bit Status active
bit 4 EFA Block Lock-Bit Status register active
bit 5 EFA Block Lock-Dow n Bit Status active
(P+C)h
1
V CC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
(P+D)h
1
V PP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
Datasheet
66
Hex
Add. Code
10A
--50
10B:
--52
10C:
--49
10D:
--31
10E:
--34
10F:
--E6
110:
--01
111:
--00
112:
--00
bit 0 = 0
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 1
bit 9 = 0
bit 10 = 0
bit 11 = 0
bit 12 = 0
bit 30 = 0
bit 31 = 0
113:
--01
Value
"P"
"R"
"I"
"1"
"4"
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
No
No
No
No
No
No
bit 0
114:
115:
bit 0
bit 1
bit 4
bit 5
116:
=1
--03
--00
=1
=1
=0
=0
--18
Yes
Yes
Yes
No
No
1.8V
117:
--90
9.0V
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 37: OTP Register Information
Offset(1) Length
Description
P = 10Ah
(Optional flash features and commands)
Number of Protection register fields in JEDEC ID space.
(P+E)h
1
“00h,” indicates that 256 protection fields are available
(P+F)h
4
Protection Field 1: Protection Description
(P+10)h
This field describes user-available One Time Programmable
(P+11)h
(OTP) Protection register bytes. Some are pre-programmed
w ith device-unique serial numbers. Others are user
(P+12)h
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The follow ing bytes are factory
pre-programmed and user-programmable.
Hex
Add. Code Value
118: --02
2
119:
11A:
11B:
11C:
--80
--00
--03
--03
80h
00h
8 byte
8 byte
11D:
11E:
11F:
120:
121:
122:
123:
124:
125:
126:
--89
--00
--00
--00
--00
--00
--00
--10
--00
89h
00h
00h
00h
0
0
0
16
0
16
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
(P+18)h
(P+19)h
(P+1A)h
(P+1B)h
(P+1C)h
Datasheet
67
10
Protection Field 2: Protection Description
Bits 0–31 point to the Protection register physical Lock-w ord
address in the Jedec-plane.
Follow ing bytes are factory or user-programmable.
bits 32–39 = “n” such that n = factory pgm'd groups (low byte)
bits 40–47 = “n” such that n = factory pgm'd groups (high byte)
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n” such that n = user pgm'd groups (low byte)
bits 64–71 = “n” such that n = user pgm'd groups (high byte)
bits 72–79 = “n” such that 2n = user programmable bytes/group
--04
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 38: Burst Read Information
Offset
P=10Ah
Length
Description
(Optional flash features and commands)
Add.
Hex
Code
Value
127:
--04
16 Byte
(P+1D)h
1
Page Mode Read capability
bits 0-7 = “n” such that 2n HEX value represents the number
of read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
(P+1E)h
1
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
128:
--04
4
(P+1F)h
1
Synchronous mode read capability configuration 1
Bits 3-7 = Reserved
bits 0-2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0-2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
129:
--01
4
(P+20)h
1
Synchronous mode read capability configuration 2
12A:
--02
8
(P+21)h
1
Synchronous mode read capability configuration 3
12B:
--03
16
(P+22)h
1
Synchronous mode read capability configuration 4
12C:
--07
Cont
Table 39: Partition and Erase Block Region Information
Offset(1)
P = 10Ah
Bottom
Top
(P+23)h
Datasheet
68
Description
(Optional flash features and commands)
Number of device hardw are-partition regions w ithin the device.
x = 0: a single hardw are partition device (no fields follow ).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
(P+23)h
See table below
Address
Bot
Top
Len
1
12D:
12D:
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 40: Partition Region 1 Information (Sheet 1 of 2)
Offset(1)
P = 10Ah
Description
Bottom
Top
(Optional flash features and commands)
(P+24)h (P+24)h Data size of this Parition Region Information field
(P+25)h (P+25)h (# addressable locations, including this field)
(P+26)h (P+26)h Number of identical partitions w ithin the partition region
(P+27)h (P+27)h
(P+28)h (P+28)h Number of program or erase operations allow ed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+29)h
(P+29)h Simultaneous program or erase operations allow ed in other partitions w hile a
partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+2A)h (P+2A)h Simultaneous program or erase operations allow ed in other partitions w hile a
partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+2B)h (P+2B)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w / contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Datasheet
69
See table below
Address
Bot
Top
Len
2
12E:
12E
12F
12F
2
130:
130:
131:
131:
1
132:
132:
1
133:
133:
1
134:
134:
1
135:
135:
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 41: Partition Region 1 Information (Sheet 2 of 2)
Offset(1)
P = 10Ah
Description
Bottom
Top
(Optional flash features and com m ands)
(P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information
(P+2D)h (P+2D)h
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
(P+2E)h (P+2E)h
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+2F)h (P+2F)h
(P+30)h (P+30)h Partition 1 (Erase Block Type 1)
(P+31)h (P+31)h
Block erase cycles x 1000
(P+32)h (P+32)h Partition 1 (erase block Type 1) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+33)h
(P+34)h
(P+35)h
(P+36)h
(P+37)h
(P+38)h
(P+39)h
(P+3A)h
(P+3B)h
(P+3C)h
(P+3D)h
(P+3E)h
(P+3F)h
(P+40)h
(P+33)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities
defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition Region 1 (Erase Block Type 1) Programming Region Information
(P+34)h
bits 0–7 = x, 2^x = Programming Region aligned size (bytes)
(P+35)h
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
(P+36)h
bits 16–23 = y = Control Mode valid size in bytes
(P+37)h
bits 24-31 = Reserved
(P+38)h
bits 32-39 = z = Control Mode invalid size in bytes
(P+39)h
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
(P+3A)h Partition Region 1 Erase Block Type 2 Information
(P+3B)h
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
(P+3C)h
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+3D)h
(P+3E)h Partition 1 (Erase Block Type 2)
(P+3F)h
Block erase cycles x 1000
(P+40)h Partition 1 (erase block Type 2) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
13D:
13D:
1
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
1
14B:
14B:
Partition Region 1 (Erase Block Type 2) Programming Region Information
6
bits 0–7 = x, 2^x = Programming Region aligned size (bytes)
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode valid size in bytes
bits 24-31 = Reserved
bits 32-39 = z = Control Mode invalid size in bytes
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
14C:
14D:
14E:
14F:
150:
151:
14C:
14D:
14E:
14F:
150:
151:
(P+41)h
(P+41)h Partition 1 (erase block Type 2) page mode and synchronous mode capabilities
defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
(P+42)h
(P+43)h
(P+44)h
(P+45)h
(P+46)h
(P+47)h
(P+42)h
(P+43)h
(P+44)h
(P+45)h
(P+46)h
(P+47)h
Datasheet
70
See table below
Address
Bot
Top
Len
4
136:
136:
137:
137:
138:
138:
139:
139:
2
13A:
13A:
13B:
13B:
1
13C:
13C:
1
6
4
2
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 42: Partition and Erase Block Region Information
64-Mbit
Add
Datasheet
71
128-Mbit
--B
--T
--B
--T
12D:
--01
--01
--01
--01
12E:
--24
--24
--24
--24
12F:
--00
--00
--00
--00
130:
--01
--01
--01
--01
131:
--00
--00
--00
--00
132:
--11
--11
--11
--11
133:
--00
--00
--00
--00
134:
--00
--00
--00
--00
135:
--02
--02
--02
--02
136:
--03
--3E
--03
--7E
137:
--00
--00
--00
--00
138:
--80
--00
--80
--00
139:
--00
--02
--00
--02
13A:
--64
--64
--64
--64
13B:
--00
--00
--00
--00
13C:
--02
--02
--02
--02
13D:
--03
--03
--03
--03
13E:
--00
--00
--00
--00
13F:
--80
--80
--80
--80
140:
--00
--00
--00
--00
141:
--00
--00
--00
--00
142
--00
--00
--00
--00
143:
--80
--80
--80
--80
144:
--3E
--03
--7E
--03
145:
--00
--00
--00
--00
146:
--00
--80
--00
--80
147:
--02
--00
--02
--00
148:
--64
--64
--64
--64
149:
--00
--00
--00
--00
14A:
--02
--02
--02
--02
14B:
--03
--03
--03
--03
14C:
--00
--00
--00
--00
14D:
--80
--80
--80
--80
14E:
--00
--00
--00
--00
14F:
--00
--00
--00
--00
150:
--00
--00
--00
--00
151:
--80
--80
--80
--80
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 43: CFI Link Information
Length
4
1
Datasheet
72
Description
(Optional flash features and commands)
CFI Link Field bit definitions
Bits 0–9 = Address offset (within 32Mbit segment) of referenced CFI table
Bits 10–27 = nth 32Mbit segment of referenced CFI table
Bits 28–30 = Memory Type
Bit 31 = Another CFI Link field immediately follows
CFI Link Field Quantity Subfield definitions
Bits 0–3 = Quantity field (n such that n+1 equals quantity)
Bit 4 = Table & Die relative location
Bit 5 = Link Field & Table relative location
Bits 6–7 = Reserved
Add.
152:
153:
154:
155:
Hex
Code
Value
--FF
156:
--FF
Apr 2010
Order Number: 208033-02
P30-65nm SBC
A.2
Flowcharts
Figure 32: Word Program Flowchart
Start
Command Cycle
- Issue Program Command
- Address = location to program
- Data = 0x40
Data Cycle
- Address = location to program
- Data = Data to program
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal D7
No
D7 = '1'
?
No
Yes
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
Suspend
?
No
Yes
Program Suspend
See Suspend/
Resume Flowchart
Errors
?
Yes
Error-Handler
User Defined Routine
End
Datasheet
73
Apr 2010
Order Number:208033-02
P30-65nm SBC
Figure 33: Program Suspend/Resume Flowchart
PROGRAM SUSPEND /RESUME PROCEDURE
Bus
Command
Operation
Start
Read
Status
Write
Write 70h
Any Address
Write
Program Suspend
Write B0h
Any Address
0
Status register data
Initiate a read cycle to update Status
register
Addr = Suspended block (BA)
Standby
Check SR.7
1 = WSM ready
0 = WSM busy
Standby
Check SR.2
1 = Program suspended
0 = Program completed
1
SR. 2 =
Read
0
Program
Completed
1
Array
Write
Write FFh
Any Address
Read
Read Array
Data
Done
Reading
Program
Yes
Resume
Read
Array
Data = FFh
Addr = Block address to read (BA)
Read array data from block other than
the one being programmed
Program Data = D0 h
Resume Addr = Suspended block (BA)
No
Read
Array
Write FFh
Program
Resumed
Read Array
Data
Status
Write70h
Any Address
Datasheet
74
Write
Write D0h
Any Address
Read
Data = 70h
Addr = Block to suspend (BA)
Program Data = B0h
Suspend Addr = X
Read
Read Status
Register
SR. 7 =
Read
Status
Comments
PGM_ SUS. WMF
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Figure 34: Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Start
Write 0 x70 ,
Same Partition
Write 0xB0,
Any Address
Bus
Command
Operation
(Read Status )
(Erase Suspend )
Read Status
Register
SR[7 ] =
Read Array
Data
Read or
Program ?
No
Data = 0xB0
Erase
Addr = Same partition address as
Suspend
above
None
Status Register data.
Addr = Same partition
Idle
None
Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle
None
Check SR[6]:
1 = Erase suspended
0 = Erase completed
Write
Read or
Write
Program
Program
Loop
Data = 0x70
Addr = Any partition address
Read
Erase
Completed
0
1
Read
Write
Read
Status
0
1
SR[6 ] =
Write
Comments
Write
Done
Data = 0xFF or 0x40
Read Array
Addr = Any address within the
or Program
suspended partition
None
Read array or program data from/to
block other than the one being erased
Program Data = 0xD0
Resume Addr = Any address
If the suspended partition was placed in
Read Array mode or a Program Loop
:
Yes
(Erase Resume )
Write 0xD0,
Any Address
Erase
Resumed
(Read Status )
Datasheet
75
Write 0 x70 ,
Same Partition
Write
Read
Return partition to Status mode:
Status Data = 0x70
Register Addr = Same partition
Write 0xFF,
(Read Array )
Erased Partition
Read Array
Data
Apr 2010
Order Number:208033-02
P30-65nm SBC
Figure 35: Buffer Program Flowchart
Start
Device
Supports Buffer
Writes?
No
Use Single Word
Programming
Yes
Set Timeout or
Loop Counter
Bus
Operation
Command
Write
Write to
Buffer
Read
(Note 7)
SR. 7 = Valid
Addr = Block Address
Standby
Check SR.7
1 = Device WSM is Busy
0 = Device WSM is Ready
Yes
Clear Status Register
50h
Address within Device
Get Next
Target Address
Issue Write to Buffer
Command E8h
Block Address
0 = No
Timeout
or Count
Expired ?
Data = Write Buffer Data
Addr =Address within buffer range
Write
( Notes5 , 6)
Data = Write Buffer Data
Addr = Block Address
Program
Confirm
Data = D0H
Addr = Block Address
Status register Data
CE# and OE# low updates SR
Addr = Block Address
Check SR.7
1 = WSM Ready
0 = WSM Busy
Notes:
1. Word count values on DQ 0-DQ 15 are loaded into the Count
register. Count ranges for this device are N=0000h to 00FFh.
Yes
.
2. The device outputs the Status Register when read.
Write Word Count
Block Address
3. Write Buffer contents will be programmed at the device start
address or destination flash address .
Write Buffer Data
Start Address
X = X +1
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A8-A1 of the start
address =0).
.
Write Buffer Data
Address within buffer range
X =0
5. The device aborts the Buffered Program command if the
current address is outside the original block address .
.
No
No
Yes
6. The Status register indicates an “improper command
Sequence” if the Buffered Program command is aborted.
Follow this with a Clear Status Register command .
Abort Bufferred
Program?
Yes
Write Confirm D0h
Block Address
7. The device defaults to output SR data after the Buffered
Programming Setup Command (E8h) is issued . CE# or OE#
must be be toggled to update Status Register . Don’t issue the
Read SR command (70h), which would be interpreted by the
internal state machine as Buffer Word Count.
Write to another
Block Address
Buffered Program
Aborted
8. Full status check can be done after all erase and write
sequences complete . Write FFh after the last operation to
reset the device to read array mode.
Read Status Register
No
SR. 7 =?
Write
( Notes3 , 4)
Standby
1 = Yes
X =N?
Data = N- 1 = Word Count
N = 0 corresponds to count= 1
Addr = Block Address
Read
No
Is WSM Ready ?
SR. 7 =
Write
( Notes1 , 2)
Write
Read Status Register
Block Address
(note 7)
Comments
Data = E8H
Addr = Block Address
0
Suspend
Program
Yes
Suspend
Program
Loop
1
Full Status
Check if Desired
Yes
Another Buffered
Programming?
No
Program Complete
Datasheet
76
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Figure 36: Program Suspend/Resume Flowchart
PROGRAM SUSPEND /RESUME PROCEDURE
Bus
Command
Operation
Start
Read
Status
Write
Write 70h
Any Address
Write
Program Suspend
Write B0h
Any Address
0
Status register data
Initiate a read cycle to update Status
register
Addr = Suspended block (BA)
Standby
Check SR.7
1 = WSM ready
0 = WSM busy
Standby
Check SR.2
1 = Program suspended
0 = Program completed
1
SR. 2 =
Read
0
Program
Completed
1
Array
Write
Write FFh
Any Address
Read
Read Array
Data
Done
Reading
Program
Yes
Resume
Read
Array
Data = FFh
Addr = Block address to read (BA)
Read array data from block other than
the one being programmed
Program Data = D0 h
Resume Addr = Suspended block (BA)
No
Read
Array
Write FFh
Program
Resumed
Read Array
Data
Status
Write70h
Any Address
Datasheet
77
Write
Write D0h
Any Address
Read
Data = 70h
Addr = Block to suspend (BA)
Program Data = B0h
Suspend Addr = X
Read
Read Status
Register
SR. 7 =
Read
Status
Comments
PGM_ SUS. WMF
Apr 2010
Order Number:208033-02
P30-65nm SBC
Figure 37: BEFP Flowchart
Setup Phase
Program/Verify Phase
Start
Read Status
Register
Exit Phase
A
B
Issue BEFP Setup Cmd
(Data = 0x80)
Read Status
Register
No (SR.0=1)
Buffer Ready ?
No (SR.7=0)
BEFP Exited ?
Issue BEFP Confirm Cmd
(Data = 00D0h)
Yes (SR.0=0)
Write Data Word to Buffer
Yes (SR.7=1)
BEFP
Setup
Delay
Full Status
Register check for
errors
Buffer Full ?
No
Read Status
Register
Finish
Yes
BEFP Setup
Done ?
Read Status
Register
Yes (SR.7=0)
A
No (SR.7=1)
Program
Done ?
SR Error Handler
(User-Defined)
No (SR.0=1)
Yes (SR.0=0)
Exit
Yes
Program
More Data ?
No
Write 0xFFFFh outside Block
Datasheet
78
B
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Figure 38: Block Erase Flowchart
Start
Command Cycle
- Issue Erase command
- Address = Block to be erased
- Data = 0x20
Confirm Cycle
- Issue Confirm command
- Address = Block to be erased
- Data = Erase confirm (0xD0)
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal SR.7
No
SR.7 = '1'
?
No
Yes
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
Suspend
?
No
Yes
Erase Suspend
See Suspend/
Resume Flowchart
Errors
?
Yes
Error-Handler
User Defined Routine
End
Datasheet
79
Apr 2010
Order Number:208033-02
P30-65nm SBC
Figure 39: Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Bus
Command
Operation
Start
Lock
Setup
Write
Write 60 h
Block Address
Lock
Confirm
Write
Write 01 ,D0,2Fh
Block Address
Lock
Setup
Comments
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Lock,
Data = 01h (Lock block)
Unlock, or
D0h (Unlock block)
Lockdown
2Fh (Lockdown block)
Confirm Addr = Block to lock/unlock/lock-down (BA)
Read ID Plane
Write
( Optional)
Op tion al
Write 90 h
Yes
Read
Array
Data = 90h
Addr = Block address offset +2 ( BA+2)
Read
Block Lock Block Lock status data
( Optional)
Status Addr = Block address offset +2 ( BA+2)
Read Block Lock
Status
Locking
Change ?
Read ID
Plane
No
Confirm locking change on DQ1, DQ0 .
(See Block Locking State Transitions Table
for valid combinations.)
Standby
( Optional)
Write
Read
Array
Data = FFh
Addr = Block address (BA)
Write FFh
Any Address
Lock Change
Complete
Datasheet
80
LOCK_OP.WMF
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Figure 40: OTP Register Programming Flowchart
Start
OTP Program Setup
- Write 0xC0
- OTP Address
Confirm Data
- Write OTP Address and Data
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal SR.7
SR.7 = '1'
?
No
Yes
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
End
Datasheet
81
Apr 2010
Order Number:208033-02
P30-65nm SBC
Figure 41: Status Register Flowchart
Start
Command Cycle
- Issue Status Register Command
- Address = any device address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
No
SR7 = '1'
Yes
- Set/Reset
by WSM
SR6 = '1'
Yes
Erase Suspend
See Suspend /Resume Flowchart
Yes
Program Suspend
See Suspend /Resume Flowchart
No
SR2 = '1'
No
SR5 = '1'
Yes
SR4 = '1'
Yes
Error
Command Sequence
No
No
Error
Erase Failure
SR4 = '1'
Yes
Error
Program Failure
Yes
Error
VPEN/PP < VPENLK/PPLK
Yes
Error
Block Locked
No
- Set by WSM
- Reset by user
- See Clear Status
Register Command
SR3 = '1'
No
SR1 = '1'
No
End
Datasheet
82
Apr 2010
Order Number: 208033-02
P30-65nm SBC
A.3
Write State Machine
Show here are the command state transitions (Next State Table) based on incoming
commands. Only one partition can be actively programming or erasing at a time. Each
partition stays in its last read state (Read Array, Read Device ID, Read CFI or Read
Status Register) until a new command changes it. The next WSM state does not depend
on the partition’s output state.
Note:
IS refers to Illegal State in the Next State Tables.
Table 44: Next State Table for P3x-65nm (Sheet 1 of 3)
OTP
Busy
IS in OTP Busy
Setup
Busy
Word
Program
EFI
IS in OTP
Busy
IS in
Pgm
Busy
IS in Pgm
Busy
Ready (Unlock
Block)
IS in S-fn Susp
Datasheet
83
OTP
Setup
Ready Ready Ready
(Lock Ready
(Lock
Error (Lock down (Set
Block
Block CR)
[Botc
)
)
h])
OTP Busy
Illegal State in OTP
Busy
OTP Busy
OTP Busy
Pgm Busy
Pgm
Susp
IS in
Pgm
Susp
Pgm
Suspend
WSM Operation Completes
N/A
N/A
N/A
Ready (Lock Error
[Botch])
N/A
N/A
OTP Busy
N/A
N/A
OTP Busy
Ready
OTP Busy
Pgm
Busy
Pgm
Susp
Word Pgm Busy
IS in Pgm
Susp
Pgm
Busy
Pgm Susp
Word
Pgm
Susp
(Er
bits
clear)
IS in Word Pgm
Busy
N/A
Pgm Busy
Word Pgm Busy
N/A
Pgm Busy
Word Program
Suspend
N/A
Word Pgm Susp
N/A
Ready
Pgm Busy
Word
Illegal State in Pgm
Pgm
Suspend
Susp
N/A
Word Program Suspend
Sub-function Setup
Sub-op-code Load 1
Sub-function Load 2 if word count >0, else Sub-function confirm
N/A
Sub-function Confirm if data load in program buffer is complete, ELSE Sub-function Load 2
Ready (Error [Botch])
S-fn
Busy
IS in
S-fn
Busy
S-fn Busy
S-fn
Busy
Illegal State S-fn
in S-fn Busy Busy
Ready (Error [Botch])
S-fn
Susp
IS in Subfunction Busy
Sub-function
Susp
Ready
Word Program Busy
Pgm
Busy
IS in Pgm
Suspend
EFI Setup
Sub-function
Setup
Sub-op-code
Load 1
Sub-function
Load 2
Sub-function
Confirm
Sub-function
Busy
BC
Setup
Ready (Lock Error [Botch])
IS in Pgm Busy
Suspend
Lock/RCR
/ECR Setup
BEFP
Setup
Erase
Setup
EFI
Setup
OTP Busy
IS in
OTP
OTP Busy
Busy
OTP Busy
Ready
other
Ready
Setup
Busy
BP Setup
Ready (Lock
Error [Botch])
Lock/RCR/ECR Setup
OTP
Program
Setup
Ready
Ready
(90h,
(03h,
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) 98h) (60h) (BCh) (C0h) (01h) (2Fh) 04h)
Other Commands (2)
Block Address Change
Write ECR/RCR Confirm (7)
Lock-down Blk Confirm (7)
Lock Blk Confirm (7)
OTP Setup
Blank Check
Lock/RCR/ECR Setup
Read ID/Query
Clear SR (5)
Read Status
Pgm/Ers Suspend
Confirm (7)
BEFP Setup (6)
Erase Setup (4,9)
EFI Command Setup
BP Setup (8)
Word Pgm Setup (4,9)
Current Chip State
Array Read (3)
Command Input and Resulting Chip Next State(1)
S-fn Busy
IS in S-fn Busy
S-fn Busy
S-fn Busy
Ready
Sub-function Busy
S-fn
Susp
IS in
Illegal State S-fn
S-fn Sub-function
in S-fn Busy Busy
Susp
S-fn
Suspend
S-fn
Susp S-fn
(Er
IS in S-fn Susp
bits Susp
clear)
Sub-function Suspend
S-fn Suspend
N/A
S-fn Susp
N/A
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 44: Next State Table for P3x-65nm (Sheet 2 of 3)
Buffer
Pgm
(BP)
Ready (Error [Botch])
IS in
BP
Busy
BP
Busy
BP Busy
Illegal State
in BP Busy
BP
Busy
BP
Busy
IS in
BP
Susp
Setup
BP Suspend
Illegal State
in BP Busy
Ready (Error [Botch])
IS in
Erase
Busy Erase
Busy
Erase Busy
IS in Erase Busy
EFI
Word
BP Setup
Pgm
Setup
in
Erase Setup
in
Erase
Susp
in
Erase Erase Susp
Susp
Susp
IS in Erase Susp
Setup
Word
Pgm
busy
in
Erase
Susp
Busy
IS in
Pgm
busy
in Ers
Susp
Word Pgm
busy in
Erase Susp
IS in Erase
Busy
BP Busy
Illegal State in
Word Program
Suspend in Erase
Suspend
Setup
BP Load 1 (8)
BP Load 2
(8)
BP Confirm
BP Busy
BP
Busy
BP Suspend
IS in BP Suspend
BP
Susp
BP
(Er
Susp
bits
clear)
BP Suspend
Erase
Busy
BP Busy
WSM Operation Completes
Other Commands (2)
BP Busy
IS in BP Susp
BP Suspend
Ready (Error [Botch])
Erase Erase
Busy Susp
Erase Busy
IS in Erase Busy
Erase Busy
N/A
BP Susp
N/A
Ready (Err
Botch0])
N/A
Ers Busy
N/A
Ready
Word iS in
Pgm pgm
susp susp
in Ers in Ers
susp Susp
Word Pgm
susp in Ers
susp
iS in pgm
susp in Ers
Susp
Word
Pgm
busy
in
Erase
Susp
Word
Pgm
Word Word
Word
Pgm Pgm Susp Pgm
in Ers
susp susp Susp susp
in Ers in Ers
in Ers
(Er
susp susp
susp
bits
clear)
N/A
N/A
Ready
Erase Suspend
N/A
Erase Susp
N/A
N/A
Word Pgm busy in
Erase Susp
N/A
Erase
Susp
IS in
Word Pgm Busy in Ers
Ers Suspend
Susp
Word Pgm busy in Erase Suspend
iS in Word Pgm
susp in Ers Susp
Word Pgm susp in
Ers susp
N/A
N/A
Word Pgm busy in Erase Suspend
BP Load 1 in Erase Suspend
BP Load 2 in Erase Suspend if word count >0, else BP confirm
BP Confirming Erase Suspend if data load in program buffer is complete, ELSE BP load 2 in Erase Suspend
Erase Suspend (Error [BotchBP])
BP
IS in
BP
BP
BP
Illegal State Busy
Busy Busy BP Busy in in BP Busy in in Ers Susp BP Busy in Ers Susp
in Ers
Erase Susp
Susp in Ers
in
Ers
Ers
Susp
Susp
Susp
Susp
IS in BP Busy
BP Susp
IS in BP Busy
Erase Busy
Lock/
Erase
RCR/
Susp
ECR
IS in
IS in Erase Erase
Erase
Erase
(Er
Setup Erase Erase
Suspend
Busy
Suspend
Susp
Susp
bits
in
Susp
clear)
Erase
Susp
Erase Suspend
Word Pgm busy in Erase Suspend
Word
Word
Pgm Pgm
IS in Word
busy
IS in Word Pgm
Word Pgm busy in
Pgm busy in
Susp
in
Erase Susp
busy in Ers Susp
Ers Susp
in Ers
Erase Susp
Susp
Illegal state(IS)
in Pgm busy in
Erase Suspend
Suspend
BP Confirm if data
Ready
(Error load in program
buffer is
[Botc complete, else BP
h])
load 2
Ready (Error [Botch])
BP
Susp
IS in BP Susp
Suspend
other
BP Busy
BP
Susp
Busy
Block Address Change
Write ECR/RCR Confirm (7)
Lock-down Blk Confirm (7)
Lock Blk Confirm (7)
BP Confirm if data load in program buffer is complete, ELSE BP load 2
BP Susp
Datasheet
84
OTP Setup
BP Load 2 (8)
BP Busy
BP in
Erase
Suspend
Blank Check
(90h,
(03h,
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) 98h) (60h) (BCh) (C0h) (01h) (2Fh) 04h)
BP Load 1
BP Load 2 if word count >0, else BP confirm
BP Confirm
Word
Pgm in
Erase
Suspend
Lock/RCR/ECR Setup
Setup
BP Load 1 (8)
IS in BP Busy
Erase
Read ID/Query
Clear SR (5)
Read Status
Pgm/Ers Suspend
Confirm (7)
BEFP Setup (6)
Erase Setup (4,9)
EFI Command Setup
BP Setup (8)
Array Read (3)
Current Chip State
Word Pgm Setup (4,9)
Command Input and Resulting Chip Next State(1)
Ers
Susp
(Error
[Botc
h])
BP Confirm in
Erase Suspend
when count=0,
ELSE BP load 2
N/A
BP Busy in Ers
Susp
Erase Susp (Error [Botch BP])
IS in BP Busy in
Erase Suspend
BP Busy in Ers Susp
BP
Susp
in Ers
Susp
(Er
bits
clear)
BP Suspend
BP Susp in
Ers Susp
BP
Susp
in Ers
Susp
IS in BP Busy in
Erase Suspend
Erase
Susp
IS in
Ers
Susp
BP Busy in Erase Suspend
IS in
BP
BP
BP
BP Suspend Illegal State Busy
Susp
Susp
in Erase
in BP Busy in
in Ers in Ers
in Ers
Suspend
Ers Susp
Susp
Susp
Susp
N/A
BP Susp in Ers Susp
N/A
BP Susp in Ers
Susp
N/A
in Erase Suspend
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Table 44: Next State Table for P3x-65nm (Sheet 3 of 3)
EFI Setup
Sub-function
Setup
Sub-op-code
Load 1
Sub-function
Load 2
Sub-function
Confirm
EFI in
Erase
Suspend
Sub-function
Busy
Blank Check Busy
Setup
BEFP Busy
Datasheet
85
WSM Operation Completes
Other Commands (2)
Block Address Change
Write ECR/RCR Confirm (7)
Lock-down Blk Confirm (7)
Lock Blk Confirm (7)
OTP Setup
Blank Check
Lock/RCR/ECR Setup
Read ID/Query
Sub-function Confirm in Erase Suspend if data load in program buffer is complete, ELSE Sub-function Load 2
Erase Suspend (Error [Botch])
S-fn
IS in
Busy S-fn
S-fn
Busy S-fn S-fn Busy in Illegal State in Ers Susp
in S-fn Busy Susp
Busy
in Ers
in Ers in Ers Ers Suspend in Ers Susp
Susp
Susp
Susp
Ers
Susp
(Error
[Botc
h])
Sub-function
Confirm if data
load in program
buffer is
complete, ELSE
Sub-function
Load 2
N/A
S-fn Busy in Ers
Susp
IS in
S-fn S-fn
Susp
in Ers Susp
in Ers
Susp Susp
S-fn
Suspend in
Ers Susp
Illegal State S-fn
Busy
in S-fn Busy in Ers
in Ers Susp
Susp
N/A
Erase Suspend (Error [Botch])
S-fn Busy in Ers
Susp
IS in S-fn Busy in
Ers Susp
S-fn Busy in Ers
Susp
S-fn
Suspend in
Ers Susp
S-fn
Susp
in Ers S-fn
Susp
Susp in Ers
(Er
bits Susp
clear)
Erase
Susp
IS in
Ers
Susp
Sub-function Busy in Ers Susp
IS in S-fn Susp in
Ers Susp
S-fn Suspend in Ers
Susp
N/A
S-fn Susp in Ers
Susp
Ers
Ers
Susp Ers Susp Ers
Susp
Susp
(Error Blk
Blk
CR
[Botc
LkLock Down Set
h])
N/A
Ers Susp (Error
[Botch])
N/A
Ready (Error
[Botch])
N/A
BC Busy
Ready
BEFP Busy
Ready
N/A
Sub-Function Suspend in Erase Suspend
Erase Suspend (Lock Error
[Botch])
Ready (Error [Botch])
BC
Busy
IS in
BC
Busy
BC Busy
IS in BC
Busy
IS in Blank Check
Busy
BEFP
Clear SR (5)
Sub-op-code Load 1 in Erase Suspend
Setup
Blank
Check
other
Sub-function Load 2 in Erase Suspend if word count >0, else Sub-function confirm in Erase Suspend
IS in Phase-1
Susp
Lock/RCR/ECR/Lock
EFA Block Setup in
Erase Suspend
Read Status
(90h,
(03h,
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) 98h) (60h) (BCh) (C0h) (01h) (2Fh) 04h)
Sub-function Setup in Erase Suspend
IS in Subfunction Busy
Sub-function
Susp
Pgm/Ers Suspend
Confirm (7)
BEFP Setup (6)
Erase Setup (4,9)
EFI Command Setup
BP Setup (8)
Array Read (3)
Current Chip State
Word Pgm Setup (4,9)
Command Input and Resulting Chip Next State(1)
Ers
Susp
(Unlock
Block
)
BC
Busy
Ers Susp (Lock Error [Botch])
Ready (Error [Botch])
Blank Check Busy
IS in BC Busy
BC Busy
N/A
BP Busy
BEFP
Load
Ready (Error [Botch])
Data
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands
Ready
treated as data. (7)
Ready (Error [Botch])
N/A
Apr 2010
Order Number:208033-02
P30-65nm SBC
Table 45: Output Next State Table for P3x-65nm
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Other Commands (2)
Status Read
Status Read
Status Read
ID/Query Read
Array Read
Status Read
Status
Read
Output MUX
Does not Change
Status Read
Status
Read
Output MUX
doesn’t Change
Status Read
Output MUX will not change
Output MUX does
not Change
Output MUX does not Change
Array
Read
Status Read
Array Read
Ready,
Word Pgm Suspend,
BP Suspend,
Phase-1 BP Suspend,
Erase Suspend,
BP Suspend in Erase Suspend
Phase-1 BP Susp in Ers Susp
other
WSM Operation Completes
(90h,
(03h,
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) 98h) (60h) (BCh) (C0h) (01h) (2Fh) 04h)
BEFP Setup,
BEFP Pgm & Verify Busy,
Erase Setup,
OTP Setup,
BP Setup, Load 1, Load 2
BP Setup, Load1, Load 2 - in
Erase Susp.
BP Confirm
EFI Sub-function Confirm
WordPgmSetup,
Word Pgm Setup in Erase
Susp,
BP Confirm in Erase Suspend,
EFI S-fn Confirm in Ers Susp,
Blank Check Setup,
Blank Check Busy
Lock/RCR/ECR Setup,
Lock/RCR/ECR Setup in Erase
Susp
EFI S-fn Setup, Ld 1, Ld 2
EFI S-fn Setup, Ld1, Ld 2 - in
Erase Susp.
BP Busy
BP Busy in Erase Suspend
EFI Sub-function Busy
EFI Sub-fn Busy in Ers Susp
Word Program Busy,
Word Pgm Busy in Erase
Suspend,
OTP Busy
Erase Busy
Block Address Change
Write ECR/RCR Confirm (7)
Lock-down Blk Confirm (7)
Lock Blk Confirm (7)
OTP Setup
Blank Check
Lock/RCR/ECR Setup
Read ID/Query
Clear SR (5)
Read Status
Pgm/Ers Suspend
Confirm (7)
BEFP Setup (6)
Erase Setup (4,9)
EFI Command Setup
BP Setup (8)
Word Pgm Setup (4,9)
Current Chip State
Array Read (3)
Command Input to Chip and Resulting Output MUX Next State(1)
IS refers to Illegal State in the Next State Table.
“Illegal commands” include commands outside of the allowed command set.
The device defaults to "Read Array" on powerup.
If a “Read Array” is attempted when the device is busy, the result will be “garbage” data (we should not tell the user that
it will actually be Status Register data). The key point is that the output mux will be pointing to the “array”, but garbage
data will be output. “Read ID” and "Read Query" commands do the exact same thing in the device. The ID and Query data
are located at different locations in the address map.
The Clear Status command only clears the error bits in the Status Register if the device is not in the following modes:1.
WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes) 2. Suspend states (Erase
Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend).
BEFP writes are only allowed when the Status Register bit #0 = 0 or else the data is ignored.
Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register and Blank Check) perform the
operation and then move to the Ready State.
Buffered programming will botch when a different block address (as compared to the address given on the first data write
cycle) is written during the BP Load1 and BP Load2 states.
All two cycle commands will be considered as a contiguous whole during device suspend states. Individual commands will
not be parsed separately. (I.e. If an erase set-up command is issued followed by a D0h command, the D0h command will
not resume the program operation. Issuing the erase set-up places the CUI in an “illegal state”. A subsequent command
will clear the “illegal state”, but the command will be otherwise ignored.
Datasheet
86
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Appendix B Conventions - Additional Documentation
B.1
BEFP :
Acronyms
Buffer Enhanced Factory Programming
CUI :
Command User Interface
CFI :
Common Flash Interface
EFI :
Extended Function Interface
SBC :
Single Bit per Cell
OTP :
One-Time Programmable
PLR :
one-time programmable Lock Register
PR :
one-time programmable Register
RCR :
Read Configuration Register
RFU :
Reserved for Future Use
SR :
Status Register
SRD :
Status Register Data
WSM :
Write State Machine
B.2
VCC :
Definitions and Terms
Signal or voltage connection
VCC :
Signal or voltage level
h:
Hexadecimal number suffix
0b :
Binary number prefix
0x :
Exadecimal number prefix
SR.4 :
Denotes an individual register bit.
SR[3,1] :
Denotes a group individual register bits.
SR[3:1] :
Denotes a group continuous register bits.
A[15:0] :
Denotes a group of similarly named signals, such as address or data bus.
A5 :
Denotes one element of a signal group membership, such as an individual address
bit.
Bit :
Single Binary unit
Byte :
Eight bits
Word :
Two bytes, or sixteen bits
Kbit :
1024 bits
KByte :
1024 bytes
KWord :
1024 words
Mbit :
1,048,576 bits
MByte :
1,048,576 bytes
MWord :
1,048,576 words
K:
1,000
Datasheet
87
Apr 2010
Order Number:208033-02
P30-65nm SBC
M:
1,000,000
Block :
A group of bits, bytes, or words within the flash memory array that erase
simultaneously.
Array block :
An array block that is usually used to store code and/or data.
Datasheet
88
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Appendix C Revision History
Date
Revision
Description
Jun 2009
01
Initial release
Apr 2010
02
Update the buffered program performance, suspend latency, BEFP performance in Table 27,
“Program and Erase Specifications” on page 58.
Update the 40Mhz spec for TSOP package in Table 25, “AC Read Specifications” on
page 50.
Add tDVWH timing comments in Table 26, “AC Write Specifications” on page 54.
Reflect the program performance in CFI in Table 34, “System Interface Information”
on page 64.
Update the URL for part number lookup.
Datasheet
89
Apr 2010
Order Number:208033-02
P30-65nm SBC
Datasheet
90
Apr 2010
Order Number: 208033-02
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