APEX20KC

APEX 20KC ® Programmable Logic Device Data Sheet February 2004 ver. 2.2 Features... ■ ■ Programmable logic device (PLD) manufactured using a 0.15-µm alllayer copper-metal fabrication process – 25 to 35% faster design performance than APEXTM 20KE devices – Pin-compatible with APEX 20KE devices – High-performance, low-power copper interconnect – MultiCoreTM architecture integrating look-up table (LUT) logic and embedded memory – LUT logic used for register-intensive functions – Embedded system blocks (ESBs) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM) High-density architecture – 200,000 to 1 million typical gates (see Table 1) – Up to 38,400 logic elements (LEs) – Up to 327,680 RAM bits that can be used without reducing available logic Note (1) EP20K400C 1,052,000 400,000 16,640 104 212,992 4 -7, -8, -9 1,664 488 Table 1. APEX 20KC Device Features Feature Maximum system gates Typical gates LEs ESBs Maximum RAM bits PLLs (2) Speed grades (3) Maximum macrocells Maximum user I/O pins Notes to Table 1: (1) (2) (3) EP20K200C 526,000 200,000 8,320 52 106,496 2 -7, -8, -9 832 376 EP20K600C 1,537,000 600,000 24,320 152 311,296 4 -7, -8, -9 2,432 588 EP20K1000C 1,772,000 1,000,000 38,400 160 327,680 4 -7, -8, -9 2,560 708 The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to 57,000 additional gates. PLL: phase-locked loop. The -7 speed grade provides the fastest performance. Altera Corporation DS-APEX20KC-2.2 1 APEX 20KC Programmable Logic Device Data Sheet ...and More Features ■ ■ ■ Low-power operation design – 1.8-V supply voltage (see Table 2) – Copper interconnect reduces power consumption – MultiVoltTM I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces – ESBs offering programmable power-saving mode Flexible clock management circuitry with up to four phase-locked loops (PLLs) – Built-in low-skew clock tree – Up to eight global clock signals – ClockLockTM feature reducing clock delay and skew – ClockBoostTM feature providing clock multiplication and division – ClockShiftTM feature providing programmable clock phase and delay shifting Powerful I/O features – Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits – Support for high-speed external memories, including DDR synchronous dynamic RAM (SDRAM) and ZBT static RAM (SRAM) – 16 input and 16 output LVDS channels at 840 megabits per second (Mbps) – Direct connection from I/O pins to local interconnect providing fast tCO and tSU times for complex logic – MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces – Programmable clamp to VCCIO – Individual tri-state output enable control for each pin – Programmable output slew-rate control to reduce switching noise – Support for advanced I/O standards, including low-voltage differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, SSTL-3 and SSTL-2, GTL+, and HSTL Class I – Supports hot-socketing operation – Pull-up on I/O pins before and during configuration Table 2. APEX 20KC Supply Voltages Feature Internal supply voltage (VCCINT) 1.8 V Voltage MultiVolt I/O interface voltage levels (VCCIO) 1.8 V, 2.5 V, 3.3 V, 5.0 V (1) Note to Table 2: (1) APEX 20KC devices can be 5.0-V tolerant by using an external resistor. 2 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet ■ ■ Advanced interconnect structure – Copper interconnect for high performance – Four-level hierarchical FastTrack® interconnect structure providing fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Interleaved local interconnect allows one LE to drive 29 other LEs through the fast local interconnect Advanced software support – Software design support and automatic place-and-route provided by the Altera® QuartusTM II development system for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations – Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions optimized for APEX 20KC architecture available – NativeLinkTM integration with popular synthesis, simulation, and timing analysis tools – Quartus II SignalTap® embedded logic analyzer simplifies in-system design evaluation by giving access to internal nodes during device operation – Supports popular revision-control software packages including PVCS, RCS, and SCCS Notes (1), (2) 652-Pin BGA Table 3. APEX 20KC QFP & BGA Package Options & I/O Count Device EP20K200C EP20K400C EP20K600C EP20K1000C 208-Pin PQFP 240-Pin PQFP 136 168 356-Pin BGA 271 488 488 488 Altera Corporation 3 APEX 20KC Programmable Logic Device Data Sheet Table 4. APEX 20KC FineLine BGA Package Options & I/O Count Notes (1), (2) Device EP20K200C EP20K400C EP20K600C EP20K1000C Notes to Tables 3 and 4: (1) (2) (3) I/O counts include dedicated input and clock pins. APEX 20KC device package types include plastic quad flat pack (PQFP), 1.27-mm pitch ball-grid array (BGA), and 1.00-mm pitch FineLine BGATM packages. This device uses a thermally enhanced package, which is taller than the regular package. Consult the Altera Device Package Information Data Sheet for detailed package size information. 484 Pin 376 672 Pin 1,020 Pin 488 (3) 508 (3) 508 (3) 588 708 Table 5. APEX 20KC QFP & BGA Package Sizes Feature Pitch (mm) Area (mm2) Length × Width (mm × mm) 208-Pin PQFP 0.50 924 30.4 × 30.4 240-Pin PQFP 0.50 1,218 34.9 × 34.9 356-Pin BGA 1.27 1,225 35.0 × 35.0 652-Pin BGA 1.27 2,025 45.0 × 45.0 Table 6. APEX 20KC FineLine BGA Package Sizes Feature Pitch (mm) Area (mm ) Length × Width (mm × mm) 2 484 Pin 1.00 529 23 × 23 672 Pin 1.00 729 27 × 27 1,020 Pin 1.00 1,089 33 × 33 General Description Similar to APEX 20K and APEX 20KE devices, APEX 20KC devices offer the MultiCore architecture, which combines the strengths of LUT-based and product-term-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for datapath, register-intensive, mathematical, or digital signal processing (DSP) designs. Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. LUT- and productterm-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20KC architecture uniquely suited for SOPC designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20KC device. 4 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet APEX 20KC devices include additional features such as enhanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry. Table 7 shows the features included in APEX 20KC devices. Table 7. APEX 20KC Device Features (Part 1 of 2) Feature MultiCore system integration Hot-socketing support SignalTap logic analysis 32-/64-bit, 33-MHz PCI 32-/64-bit, 66-MHz PCI MultiVolt I/O Full support Full support Full support Full compliance Full compliance in -7 and -8 speed grades in selected devices 1.8-V, 2.5-V, or 3.3-V VCCIO VCCIO selected bank by bank 5.0-V tolerant with use of external resistor Clock delay reduction m /(n × v) clock multiplication Drive ClockLock output off-chip External clock feedback ClockShift circuitry LVDS support Up to four PLLs ClockShift clock phase adjustment Eight APEX 20KC Devices ClockLock support Dedicated clock and input pins Altera Corporation 5 APEX 20KC Programmable Logic Device Data Sheet Table 7. APEX 20KC Device Features (Part 2 of 2) Feature I/O standard support APEX 20KC Devices 1.8-V, 2.5-V, 3.3-V, 5.0-V I/O 3.3-V PCI and PCI-X 3.3-V AGP CTT GTL+ LVCMOS LVTTL True-LVDSTM and LVPECL data pins (in EP20K400C and larger devices) LVDS and LVPECL clock pins (in all devices) LVDS and LVPECL data pins up to 156 Mbps (in EP20K200C devices) HSTL Class I PCI-X SSTL-2 Class I and II SSTL-3 Class I and II CAM Dual-port RAM FIFO RAM ROM Memory support All APEX 20KC devices are reconfigurable and are 100% tested prior to shipment. As a result, test vectors do not have to be generated for faultcoverage purposes. Instead, the designer can focus on simulation and design verification. In addition, the designer does not need to manage inventories of different application-specific integrated circuit (ASIC) designs; APEX 20KC devices can be configured on the board for the specific functionality required. APEX 20KC devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable EPC16, EPC8, EPC4, EPC2, and EPC1 configuration devices and one-time programmable (OTP) EPC1 configuration devices, which configure APEX 20KC devices via a serial data stream. Moreover, APEX 20KC devices contain an optimized interface that permits microprocessors to configure APEX 20KC devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat APEX 20KC devices as memory and configure the device by writing to a virtual memory location, making reconfiguration easy. 6 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet After an APEX 20KC device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. APEX 20KC devices are supported by the Altera Quartus II development system, a single, integrated package that offers HDL and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, SignalTap logic analysis, and device configuration. The Quartus II software runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations. The Quartus II software provides NativeLink interfaces to other industrystandard PC- and UNIX workstation-based EDA tools. For example, designers can invoke the Quartus II software from within third-party design tools. Further, the Quartus II software contains built-in optimized synthesis libraries; synthesis tools can use these libraries to optimize designs for APEX 20KC devices. For example, the Synopsys Design Compiler library, supplied with the Quartus II development system, includes DesignWare functions optimized for the APEX 20KC architecture. Functional Description APEX 20KC devices incorporate LUT-based logic, product-term-based logic, and memory into one device on an all-copper technology process. Signal interconnections within APEX 20KC devices (as well as to and from device pins) are provided by the FastTrack interconnect—a series of fast, continuous row and column channels that run the entire length and width of the device. Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack interconnect. Each IOE contains a bidirectional I/O buffer and a register that can be used as either an input or output register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional performance. IOEs provide a variety of features, such as 3.3-V, 64-bit, 66-MHz PCI compliance; JTAG BST support; slew-rate control; and tri-state buffers. APEX 20KC devices offer enhanced I/O support, including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL, 3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V AGP I/O standards. Altera Corporation 7 APEX 20KC Programmable Logic Device Data Sheet The ESB can implement a variety of memory functions, including CAM, RAM, dual-port RAM, ROM, and FIFO functions. Embedding the memory directly into the die improves performance and reduces die area compared to distributed-RAM implementations. Moreover, the abundance of cascadable ESBs allows APEX 20KC devices to implement multiple wide memory blocks for high-density designs. The ESB’s high speed ensures it can implement small memory blocks without any speed penalty. Additionally, designers can use the ESBs to create as many different-sized memory blocks as the system requires. Figure 1 shows an overview of the APEX 20KC device. Figure 1. APEX 20KC Device Block Diagram Clock Management Circuitry ClockLock IOE IOE IOE IOE FastTrack Interconnect Four-input LUT for data path and DSP functions. Product-term integration for high-speed control logic and state machines. LUT IOE Product Term Memory LUT Product Term Memory LUT Product Term Memory LUT Product Term Memory LUT IOE LUT IOE Product Term Memory LUT Product Term Memory LUT Product Term Memory LUT Product Term Memory IOE IOEs support PCI, GTL+, SSTL-3, LVDS, and other standards. IOE IOE IOE IOE Flexible integration of embedded memory, including CAM, RAM, ROM, FIFO, and other memory functions. APEX 20KC devices provide four dedicated clock pins and four dedicated input pins that drive register control inputs. These signals ensure efficient distribution of high-speed, low-skew control signals, which use dedicated routing channels to provide short delays and low skews. Four of the dedicated inputs drive four global signals. These four global signals can also be driven by internal logic, providing an ideal solution for a clock divider or internally generated asynchronous clear signals with high fan-out. The dedicated clock pins featured on the APEX 20KC devices can also feed logic. The devices also feature ClockLock and ClockBoost clock management circuitry. 8 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet MegaLAB Structure APEX 20KC devices are constructed from a series of MegaLABTM structures. Each MegaLAB structure contains 16 logic array blocks (LABs), one ESB, and a MegaLAB interconnect, which routes signals within the MegaLAB structure. In EP20K1000C devices, MegaLAB structures contain 24 LABs. Signals are routed between MegaLAB structures and I/O pins via the FastTrack interconnect. In addition, edge LABs can be driven by I/O pins through the local interconnect. Figure 2 shows the MegaLAB structure. Figure 2. MegaLAB Structure MegaLAB Interconnect To Adjacent LAB or IOEs LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE9 LE10 LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE9 LE10 LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE9 LE10 ESB Local Interconnect LABs Logic Array Block Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains, LAB control signals, and the local interconnect. The local interconnect transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs. The Quartus II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of a fast local interconnect for high performance. Figure 3 shows the APEX 20KC LAB. APEX 20KC devices use an interleaved LAB structure. This structure allows each LE to drive two local interconnect areas, minimizing the use of the MegaLAB and FastTrack interconnect and providing higher performance and flexibility. Each LE can drive 29 other LEs through the fast local interconnect. Altera Corporation 9 APEX 20KC Programmable Logic Device Data Sheet Figure 3. LAB Structure Row Interconnect MegaLAB Interconnect LEs drive local, MegaLAB, row, and column interconnects. To/From Adjacent LAB, ESB, or IOEs To/From Adjacent LAB, ESB, or IOEs Local Interconnect Column Interconnect The 10 LEs in the LAB are driven by two local interconnect areas. These LEs can drive two local interconnect areas. Each LAB contains dedicated logic for driving control signals to its LEs and ESBs. The control signals include clock, clock enable, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, and synchronous load signals. A maximum of six control signals can be used at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB’s clock and clock enable signals are linked (e.g., any LE in a particular LAB using CLK1 will also use CLKENA1). LEs with the same clock but different clock enable signals either use both clock signals in one LAB or are placed into separate LABs. If both the rising and falling edges of a clock are used in a LAB, both LABwide clock signals are used. 10 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The LAB-wide control signals can be generated from the LAB local interconnect, global signals, and dedicated clock pins. The inherent low skew of the FastTrack interconnect enables it to be used for clock distribution. Figure 4 shows the LAB control signal generation circuit. Figure 4. LAB Control Signal Generation Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect SYNCLOAD or LABCLKENA2 SYNCCLR or LABCLK2 (2) LABCLKENA1 LABCLR1 (1) 4 4 LABCLK1 LABCLR2 (1) Notes to Figure 4: (1) (2) The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the LAB. The SYNCCLR signal can be generated by the local interconnect or global signals. Logic Element The LE, the smallest unit of logic in the APEX 20KC architecture, is compact and provides efficient logic usage. Each LE contains a four-input LUT, which is a function generator that can quickly implement any function of four variables. In addition, each LE contains a programmable register and carry and cascade chains. Each LE drives the local interconnect, MegaLAB interconnect, and FastTrack interconnect routing structures. See Figure 5. Altera Corporation 11 APEX 20KC Programmable Logic Device Data Sheet Figure 5. APEX 20KC Logic Element Register Bypass LAB-wide LAB-wide Synchronous Synchronous Load Clear Cascade-In Packed Register Select Programmable Register Carry-In data1 data2 data3 data4 Look-Up Table (LUT) Carry Chain Cascade Chain Synchronous Load & Clear Logic D PRN Q To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect ENA CLRN To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect labclr1 labclr2 Chip-Wide Reset Asynchronous Clear/Preset/ Load Logic Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2 Carry-Out Cascade-Out Each LE’s programmable register can be configured for D, T, JK, or SR operation. The register’s clock and clear control signals can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the register is bypassed and the output of the LUT drives the outputs of the LE. Each LE has two outputs that drive the local, MegaLAB, or FastTrack interconnect routing structure. Each output can be driven independently by the LUT’s or register’s output. For example, the LUT can drive one output while the register drives the other output. This feature, called register packing, improves device utilization because the register and the LUT can be used for unrelated functions. The LE can also drive out registered and unregistered versions of the LUT output. 12 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The APEX 20KC architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. A carry chain supports high-speed arithmetic functions such as counters and adders, while a cascade chain implements wide-input functions such as equality comparators with minimum delay. Carry and cascade chains connect LEs 1 through 10 in an LAB and all LABs in the same MegaLAB structure. Carry Chain The carry chain provides a very fast carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higherorder bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the APEX 20KC architecture to implement high-speed counters, adders, and comparators of arbitrary width. Carry chain logic can be created automatically by the Quartus II Compiler during design processing, or manually by the designer during design entry. Parameterized functions such as DesignWare functions from Synopsys and library of parameterized modules (LPM) functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than ten LEs by automatically linking LABs together. For enhanced fitting, a long carry chain skips alternate LABs in a MegaLAB structure. A carry chain longer than one LAB skips either from an even-numbered LAB to the next evennumbered LAB, or from an odd-numbered LAB to the next oddnumbered LAB. For example, the last LE of the first LAB in the upper-left MegaLAB structure carries to the first LE of the third LAB in the MegaLAB structure. Figure 6 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT and the carry chain logic generates the carry-out signal, which is routed directly to the carryin signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is driven onto the local, MegaLAB, or FastTrack interconnect routing structures. Altera Corporation 13 APEX 20KC Programmable Logic Device Data Sheet Figure 6. APEX 20KC Carry Chain Carry-In a1 b1 LUT Register s1 Carry Chain LE1 a2 b2 LUT Register s2 Carry Chain LE2 an bn LUT Register sn Carry Chain LEn LUT Register Carry-Out Carry Chain LEn + 1 14 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Cascade Chain With the cascade chain, the APEX 20KC architecture can implement functions with a very wide fan-in. Adjacent LUTs can compute portions of a function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR (via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each additional LE provides four more inputs to the effective width of a function, with a short cascade delay. Cascade chain logic can be created automatically by the Quartus II Compiler during design processing, or manually by the designer during design entry. Cascade chains longer than ten LEs are implemented automatically by linking LABs together. For enhanced fitting, a long cascade chain skips alternate LABs in a MegaLAB structure. A cascade chain longer than one LAB skips either from an even-numbered LAB to the next even-numbered LAB, or from an odd-numbered LAB to the next odd-numbered LAB. For example, the last LE of the first LAB in the upper-left MegaLAB structure carries to the first LE of the third LAB in the MegaLAB structure. Figure 7 shows how the cascade function can connect adjacent LEs to form functions with a wide fan-in. Figure 7. APEX 20KC Cascade Chain AND Cascade Chain OR Cascade Chain d[3..0] LUT LE1 d[3..0] LUT LE1 d[7..4] LUT LE2 d[7..4] LUT LE2 d[(4n – 1)..(4n – 4)] LUT LEn d[(4n – 1)..(4n – 4)] LUT LEn Altera Corporation 15 APEX 20KC Programmable Logic Device Data Sheet LE Operating Modes The APEX 20KC LE can operate in one of the following three modes: ■ ■ ■ Normal mode Arithmetic mode Counter mode Each mode uses LE resources differently. In each mode, seven available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The Quartus II software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions that specify which LE operating mode to use for optimal performance. Figure 8 shows the LE operating modes. 16 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 8. APEX 20KC LE Operating Modes Normal Mode (1) Carry-In (3) data1 data2 data3 data4 4-Input LUT D PRN Q Cascade-In LAB-Wide Clock Enable (2) LE Out LE Out ENA CLRN Cascade-Out Arithmetic Mode Carry-In Cascade-In LAB-Wide Clock Enable (2) LE Out data1 data2 3-Input LUT 3-Input LUT Carry-Out Cascade-Out PRN D Q LE Out ENA CLRN Counter Mode Carry-In Cascade-In LAB-Wide Synchronous Load (6) LAB-Wide Synchronous Clear (6) LAB-Wide Clock Enable (2) LE Out (4) data1 (5) data2 (5) data3 (data) 3-Input LUT Carry-Out Cascade-Out PRN Q 3-Input LUT D LE Out ENA CLRN Notes to Figure 8: (1) (2) (3) (4) (5) (6) LEs in normal mode support register packing. There are two LAB-wide clock enables per LAB. When using the carry-in in normal mode, the packed register feature is unavailable. A register feedback multiplexer is available on LE1 of each LAB. The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for LEs other than the second LE in an LAB. The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB. Altera Corporation 17 APEX 20KC Programmable Logic Device Data Sheet Normal Mode The normal mode is suitable for general logic applications, combinatorial functions, or wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a four-input LUT. The Quartus II Compiler automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. LEs in normal mode support packed registers. Arithmetic Mode The arithmetic mode is ideal for implementing adders, accumulators, and comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT computes a three-input function; the other generates a carry output. As shown in Figure 8, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, when implementing an adder, this output is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The Quartus II software implements parameterized functions that use the arithmetic mode automatically where appropriate; the designer does not need to specify how the carry chain will be used. Counter Mode The counter mode offers clock enable, counter enable, synchronous up/down control, synchronous clear, and synchronous load options. The counter enable and synchronous up/down control signals are generated from the data inputs of the LAB local interconnect. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. Consequently, if any of the LEs in an LAB use the counter mode, other LEs in that LAB must be used as part of the same counter or be used for a combinatorial function. The Quartus II software automatically places any registers that are not used by the counter into other LABs. 18 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The counter mode uses two 3-input LUTs: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading, and another AND gate provides synchronous clearing. If the cascade function is used by an LE in counter mode, the synchronous clear or load overrides any signal carried on the cascade chain. The synchronous clear overrides the synchronous load. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. Clear & Preset Logic Control Logic for the register’s clear and preset signals is controlled by LAB-wide signals. The LE directly supports an asynchronous clear function. The Quartus II Compiler can use a NOT-gate push-back technique to emulate an asynchronous preset or to emulate simultaneous preset and clear or asynchronous load. However, this technique uses three additional LEs per register. All emulation is performed automatically when the design is compiled. Registers that emulate simultaneous preset and load will enter an unknown state upon power-up or when the chip-wide reset is asserted. In addition to the two clear and preset modes, APEX 20KC devices provide a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. Use of this pin is controlled through an option in the Quartus II software that is set before compilation. The chip-wide reset overrides all other control signals. Registers using an asynchronous preset are preset when the chip-wide reset is asserted; this effect results from the inversion technique used to implement the asynchronous preset. FastTrack Interconnect In the APEX 20KC architecture, connections between LEs, ESBs, and I/O pins are provided by the FastTrack interconnect. The FastTrack interconnect is a series of continuous horizontal and vertical routing channels that traverse the device. This global routing structure provides predictable performance, even in complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. The FastTrack interconnect consists of row and column interconnect channels that span the entire device. The row interconnect routes signals throughout a row of MegaLAB structures; the column interconnect routes signals throughout a column of MegaLAB structures. When using the row and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE, or ESB in a device. See Figure 9. Altera Corporation 19 APEX 20KC Programmable Logic Device Data Sheet Figure 9. APEX 20KC Interconnect Structure Row Interconnect I/O I/O I/O I/O I/O MegaLAB MegaLAB MegaLAB MegaLAB I/O I/O Column Interconnect MegaLAB MegaLAB MegaLAB MegaLAB I/O I/O MegaLAB MegaLAB MegaLAB MegaLAB I/O I/O I/O I/O I/O A row line can be driven directly by LEs, IOEs, or ESBs in that row. Further, a column line can drive a row line, allowing an LE, IOE, or ESB to drive elements in a different row via the column and row interconnect. The row interconnect drives the MegaLAB interconnect to drive LEs, IOEs, or ESBs in a particular MegaLAB structure. A column line can be directly driven by LEs, IOEs, or ESBs in that column. A column line on a device’s left or right edge can also be driven by row IOEs. The column line is used to route signals from one row to another. A column line can drive a row line; it can also drive the MegaLAB interconnect directly, allowing faster connections between rows. Figure 10 shows how the FastTrack interconnect uses the local interconnect to drive LEs within MegaLAB structures. 20 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 10. FastTrack Connection to Local Interconnect I/O Row I/O LL AA BB LE AS BB ELL SAA BBB L A B MegaLAB Structure MegaLAB Structure Column Row MegaLAB Interconnect Row & Column Interconnect Drives MegaLAB Interconnect MegaLAB Interconnect Drives Local Interconnect Column L A B L A B L A B E S B Altera Corporation 21 APEX 20KC Programmable Logic Device Data Sheet Figure 11 shows the intersection of a row and column interconnect, and how these forms of interconnects and LEs drive each other. Figure 11. Driving the FastTrack Interconnect Row Interconnect MegaLAB Interconnect Column Interconnect LE Local Interconnect APEX 20KC devices include an enhanced interconnect structure for faster routing of input signals with high fan-out. Column I/O pins can drive the FastRowTM interconnect, which routes signals directly into the local interconnect without having to drive through the MegaLAB interconnect. The FastRow lines traverse two MegaLAB structures. Also, these pins can drive the local interconnect directly for fast setup times. On EP20K400C and larger devices, the FastRow interconnect drives the two MegaLAB structures in the top left corner, the two MegaLAB structures in the two right corner, the two MegaLAB structures in the bottom left corner, and the two MegaLAB structures in the bottom right corner. On EP20K200C and smaller devices, FastRow interconnect drives the two MegaLAB structures on the top and the two MegaLAB structures on the bottom of the device. On all devices, the FastRow interconnect drives all local interconnect in the appropriate MegaLAB structures except the end local interconnect on the side of the MegaLAB opposite the ESB. Pins using the FastRow interconnect achieve a faster set-up time, as the signal does not need to use a MegaLAB interconnect line to reach the destination LE. Figure 12 shows the FastRow interconnect. 22 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 12. APEX 20KC FastRow Interconnect IOE IOE FastRow Interconnect Drives Local Interconnect in Two MegaLAB Structures IOE IOE Select Vertical I/O Pins Drive Local Interconnect and FastRow Interconnect FastRow Interconnect Local Interconnect LEs MegaLAB LABs MegaLAB Table 8 summarizes how various elements of the APEX 20KC architecture drive each other. Altera Corporation 23 APEX 20KC Programmable Logic Device Data Sheet Table 8. APEX 20KC Routing Scheme Source Row Column I/O Pin I/O Pin LE ESB Destination Local MegaLAB Interconnect Interconnect v v FastRow Column Row FastTrack Interconnect FastTrack Interconnect Interconnect v v v v v v v v v v v v v v v v v v v Row I/O pin Column I/O pin LE ESB Local interconnect MegaLAB interconnect Row FastTrack interconnect Column FastTrack interconnect FastRow interconnect v v v Product-Term Logic The product-term portion of the MultiCore architecture is implemented with the ESB. The ESB can be configured to act as a block of macrocells on an ESB-by-ESB basis. Each ESB is fed by 32 inputs from the adjacent local interconnect; therefore, it can be driven by the MegaLAB interconnect or the adjacent LAB. Also, nine ESB macrocells feed back into the ESB through the local interconnect for higher performance. Dedicated clock pins, global signals, and additional inputs from the local interconnect drive the ESB control signals. In product-term mode, each ESB contains 16 macrocells. Each macrocell consists of two product terms and a programmable register. Figure 13 shows the ESB in product-term mode. 24 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 13. Product-Term Logic in ESB Dedicated Clocks Global Signals 4 4 MegaLAB Interconnect 65 9 32 Macrocell Inputs (1 to 16) CLK[1..0] ENA[1..0] CLRN[1..0] 16 To Row and Column Interconnect From Adjacent LAB 2 2 2 Local Interconnect Macrocells APEX 20KC macrocells can be configured individually for either sequential or combinatorial logic operation. The macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. Combinatorial logic is implemented in the product terms. The productterm select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as parallel expanders to be used to increase the logic available to another macrocell. One product term can be inverted; the Quartus II software uses this feature to perform De Morgan’s inversion for more efficient implementation of wide OR functions. The Quartus II Compiler can use a NOT-gate push-back technique to emulate an asynchronous preset. Figure 14 shows the APEX 20KC macrocell. Altera Corporation 25 APEX 20KC Programmable Logic Device Data Sheet Figure 14. APEX 20KC Macrocell ESB-Wide ESB-Wide ESB-Wide Clears Clock Enables Clocks 2 Parallel Logic Expanders (From Other Macrocells) 2 2 Programmable Register ProductTerm Select Matrix D Clock/ Enable Select Q ESB Output ENA CLRN 32 Signals from Local Interconnect Clear Select For registered functions, each macrocell register can be programmed individually to implement D, T, JK, or SR operation with programmable clock control. The register can be bypassed for combinatorial operation. During design entry, the designer specifies the desired register type; the Quartus II software then selects the most efficient register operation for each registered function to optimize resource utilization. The Quartus II software or other synthesis tools can also select the most efficient register operation automatically when synthesizing HDL designs. Each programmable register can be clocked by one of two ESB-wide clocks. The ESB-wide clocks can be generated from device dedicated clock pins, global signals, or local interconnect. Each clock also has an associated clock enable, generated from the local interconnect. The clock and clock enable signals are related for a particular ESB; any macrocell using a clock also uses the associated clock enable. If both the rising and falling edges of a clock are used in an ESB, both ESB-wide clock signals are used. 26 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The programmable register also supports an asynchronous clear function. Within the ESB, two asynchronous clears are generated from global signals and the local interconnect. Each macrocell can either choose between the two asynchronous clear signals or choose to not be cleared. Either of the two clear signals can be inverted within the ESB. Figure 15 shows the ESB control logic when implementing product-terms. Figure 15. ESB Product-Term Mode Control Logic Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect 4 4 CLK2 CLKENA2 CLK1 CLKENA1 CLR2 CLR1 Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 32 product terms to feed the macrocell OR logic directly, with two product terms provided by the macrocell and 30 parallel expanders provided by the neighboring macrocells in the ESB. The Quartus II Compiler can allocate up to 15 sets of up to two parallel expanders per set to the macrocells automatically. Each set of two parallel expanders incurs a small, incremental timing delay. Figure 16 shows the APEX 20KC parallel expanders. Altera Corporation 27 APEX 20KC Programmable Logic Device Data Sheet Figure 16. APEX 20KC Parallel Expanders From Previous Macrocell ProductTerm Select Matrix Macrocell ProductTerm Logic Parallel Expander Switch ProductTerm Select Matrix Parallel Expander Switch Macrocell ProductTerm Logic 32 Signals from Local Interconnect To Next Macrocell Embedded System Block The ESB can implement various types of memory blocks, including dual-port RAM, ROM, FIFO, and CAM blocks. The ESB includes input and output registers; the input registers synchronize writes, and the output registers can pipeline designs to improve system performance. The ESB offers a dual-port mode, which supports simultaneous reads and writes at two different clock frequencies. Figure 17 shows the ESB block diagram. Figure 17. ESB Block Diagram wraddress[] data[] wren inclock inclocken inaclr rdaddress[] q[] rden outclock outclocken outaclr 28 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet ESBs can implement synchronous RAM, which is easier to use than asynchronous RAM. A circuit using asynchronous RAM must generate the RAM write enable (WE) signal, while ensuring that its data and address signals meet setup and hold time specifications relative to the WE signal. In contrast, the ESB’s synchronous RAM generates its own WE signal and is self-timed with respect to the global clock. Circuits using the ESB’s selftimed RAM must only meet the setup and hold time specifications of the global clock. ESB inputs are driven by the adjacent local interconnect, which in turn can be driven by the FastTrack or MegaLAB interconnect. Because the ESB can be driven by the local interconnect, an adjacent LE can drive it directly for fast memory access. ESB outputs drive the FastTrack and MegaLAB interconnects. In addition, ten ESB outputs, nine of which are unique output lines, drive the local interconnect for fast connection to adjacent LEs or for fast feedback product-term logic. When implementing memory, each ESB can be configured in any of the following sizes: 128 × 16, 256 × 8, 512 × 4, 1,024 × 2, or 2,048 × 1. By combining multiple ESBs, the Quartus II software implements larger memory blocks automatically. For example, two 128 × 16 RAM blocks can be combined to form a 128 × 32 RAM block, and two 512 × 4 RAM blocks can be combined to form a 512 × 8 RAM block. Memory performance does not degrade for memory blocks up to 2,048 words deep. Each ESB can implement a 2,048-word-deep memory; the ESBs are used in parallel, eliminating the need for any external control logic and its associated delays. To create a high-speed memory block that is more than 2,048 words deep, ESBs drive tri-state lines. Each tri-state line connects all ESBs in a column of MegaLAB structures, and drives the MegaLAB interconnect and row and column FastTrack interconnect throughout the column. Each ESB incorporates a programmable decoder to activate the tri-state driver appropriately. For instance, to implement 8,192-word-deep memory, four ESBs are used. Eleven address lines drive the ESB memory, and two more drive the tri-state decoder. Depending on which 2,048-word memory page is selected, the appropriate ESB driver is turned on, driving the output to the tri-state line. The Quartus II software automatically combines ESBs with tri-state lines to form deeper memory blocks. The internal tri-state control logic is designed to avoid internal contention and floating lines. See Figure 18. Altera Corporation 29 APEX 20KC Programmable Logic Device Data Sheet Figure 18. Deep Memory Block Implemented with Multiple ESBs Address Decoder ESB ESB to System Logic ESB The ESB implements two forms of dual-port memory: read/write clock mode and input/output clock mode. The ESB can also be used for bidirectional, dual-port memory applications in which two ports read or write simultaneously. To implement this type of dual-port memory, two ESBs are used to support two simultaneous reads or writes. The ESB can also use Altera megafunctions to implement dual-port RAM applications where both ports can read or write, as shown in Figure 19. Figure 19. APEX 20KC ESB Implementing Dual-Port RAM Port A address_a[] data_a[] we_a clkena_a Clock A Port B address_b[] data_b[] we_b clkena_b Clock B 30 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Read/Write Clock Mode The read/write clock mode contains two clocks. One clock controls all registers associated with writing: data input, WE, and write address. The other clock controls all registers associated with reading: read enable (RE), read address, and data output. The ESB also supports clock enable and asynchronous clear signals; these signals also control the read and write registers independently. Read/write clock mode is commonly used for applications where reads and writes occur at different system frequencies. Figure 20 shows the ESB in read/write clock mode. Figure 20. ESB in Read/Write Clock Mode Dedicated Inputs & Global Signals Dedicated Clocks 4 4 RAM/ROM 128 × 16 256 × 8 512 × 4 Data In 1,024 × 2 2,048 × 1 Data Out D ENA Q Note (1) data[ ] D ENA Q To MegaLAB, FastTrack & Local Interconnect ress[ ] D ENA Q Address wren Write Enable utclken nclken D Q ENA nclock Write Pulse Generator utclock Note to Figure 20: (1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset. Altera Corporation 31 APEX 20KC Programmable Logic Device Data Sheet Input/Output Clock Mode The input/output clock mode contains two clocks. One clock controls all registers for inputs into the ESB: data input, WE, RE, read address, and write address. The other clock controls the ESB data output registers. The ESB also supports clock enable and asynchronous clear signals; these signals also control the reading and writing of registers independently. Input/output clock mode is commonly used for applications where the reads and writes occur at the same system frequency, but require different clock enable signals for the input and output registers. Figure 21 shows the ESB in input/output clock mode. Figure 21. ESB in Input/Output Clock Mode Dedicated Inputs & Global Signals Dedicated Clocks 4 data[ ] D ENA Q Note (1) 4 RAM/ROM 128 × 16 256 × 8 512 × 4 Data In 1,024 × 2 2,048 × 1 Data Out D ENA Q To MegaLAB, FastTrack & Local Interconnect rdaddress[ ] D ENA Q Read Address wraddress[ ] D ENA Q Write Address rden Read Enable D Q wren ENA outclken Write Enable inclken D ENA Q inclock Write Pulse Generator outclock Note to Figure 21: (1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset. 32 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Single-Port Mode The APEX 20KC ESB also supports a single-port mode, which is used when simultaneous reads and writes are not required. See Figure 22. Figure 22. ESB in Single-Port Mode Dedicated Inputs & Global Signals Dedicated Clocks 4 data[ ] D ENA Q Note (1) 4 RAM/ROM 128 × 16 256 × 8 512 × 4 Data In 1,024 × 2 2,048 × 1 Data Out D ENA Q To MegaLAB, FastTrack & Local Interconnect address[ ] D ENA Q Address wren Write Enable outclken inclken D Q ENA inclock Write Pulse Generator outclock Note toFigure 22: (1) All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset. Content-Addressable Memory In APEX 20KC devices, the ESB can implement CAM. CAM can be thought of as the inverse of RAM. When read, RAM outputs the data for a given address. Conversely, CAM outputs an address for a given data word. For example, if the data FA12 is stored in address 14, the CAM outputs 14 when FA12 is driven into it. Altera Corporation 33 APEX 20KC Programmable Logic Device Data Sheet CAM is used for high-speed search operations. When searching for data within a RAM block, the search is performed serially. Thus, finding a particular data word can take many cycles. CAM searches all addresses in parallel and outputs the address storing a particular word. When a match is found, a match flag is set high. Figure 23 shows the CAM block diagram. 34 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 23. APEX 20KC CAM Block Diagram wraddress[] data[] wren inclock inclocken inaclr data_address[] match outclock outclocken outaclr CAM can be used in any application requiring high-speed searches, such as networking, communications, data compression, and cache management. The APEX 20KC on-chip CAM provides faster system performance than traditional discrete CAM. Integrating CAM and logic into the APEX 20KC device eliminates off-chip and on-chip delays, improving system performance. When in CAM mode, the ESB implements 32-word, 32-bit CAM. Wider or deeper CAM can be implemented by combining multiple CAMs with some ancillary logic implemented in LEs. The Quartus II software combines ESBs and LEs automatically to create larger CAMs. CAM supports writing “don’t care” bits into words of the memory. The “don’t care” bit can be used as a mask for CAM comparisons; any bit set to “don’t care” has no effect on matches. The output of the CAM can be encoded or unencoded. When encoded, the ESB outputs an encoded address of the data’s location. For instance, if the data is located in address 12, the ESB output is 12. When unencoded, the ESB uses its 16 outputs to show the location of the data over two clock cycles. In this case, if the data is located in address 12, the 12th output line goes high. When using unencoded outputs, two clock cycles are required to read the output because a 16-bit output bus is used to show the status of 32 words. The encoded output is better suited for designs that ensure duplicate data is not written into the CAM. If duplicate data is written into two locations, the CAM’s output will be incorrect. If the CAM may contain duplicate data, the unencoded output is a better solution; CAM with unencoded outputs can distinguish multiple data locations. CAM can be pre-loaded with data during configuration, or it can be written during system operation. In most cases, two clock cycles are required to write each word into CAM. When “don’t care” bits are used, a third clock cycle is required. Altera Corporation 35 APEX 20KC Programmable Logic Device Data Sheet f For more information on APEX 20KC devices and CAM, see Application Note 119 (Implementing High-Speed Search Applications with APEX CAM). Driving Signals to the ESB ESBs provide flexible options for driving control signals. Different clocks can be used for the ESB inputs and outputs. Registers can be inserted independently on the data input, data output, read address, write address, WE, and RE signals. The global signals and the local interconnect can drive the WE and RE signals. The global signals, dedicated clock pins, and local interconnect can drive the ESB clock signals. Because the LEs drive the local interconnect, the LEs can control the WE and RE signals and the ESB clock, clock enable, and asynchronous clear signals. Figure 24 shows the ESB control signal generation logic. Figure 24. ESB Control Signal Generation Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect RDEN 4 4 WREN INCLKENA OUTCLKENA OUTCLR INCLOCK OUTCLOCK INCLR An ESB is fed by the local interconnect, which is driven by adjacent LEs (for high-speed connection to the ESB) or the MegaLAB interconnect. The ESB can drive the local, MegaLAB, or FastTrack interconnect routing structure to drive LEs and IOEs in the same MegaLAB structure or anywhere in the device. 36 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Implementing Logic in ROM In addition to implementing logic with product terms, the ESB can implement logic functions when it is programmed with a read-only pattern during configuration, creating a large LUT. With LUTs, combinatorial functions are implemented by looking up the results, rather than by computing them. This implementation of combinatorial functions can be faster than using algorithms implemented in general logic, a performance advantage that is further enhanced by the fast access times of ESBs. The large capacity of ESBs enables designers to implement complex functions in one logic level without the routing delays associated with linked LEs or distributed RAM blocks. Parameterized functions such as LPM functions can take advantage of the ESB automatically. Further, the Quartus II software can implement portions of a design with ESBs where appropriate. Programmable Speed/Power Control APEX 20KC ESBs offer a high-speed mode that supports very fast operation on an ESB-by-ESB basis. When high speed is not required, this feature can be turned off to reduce the ESB’s power dissipation by up to 50%. ESBs that run at low power incur a nominal timing delay adder. This Turbo BitTM option is available for ESBs that implement product-term logic or memory functions. An ESB that is not used will be powered down so that it does not consume DC current. Designers can program each ESB in the APEX 20KC device for either high-speed or low-power operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths operate at reduced power. I/O Structure The APEX 20KC IOE contains a bidirectional I/O buffer and a register that can be used either as an input register for external data requiring fast setup times or as an output register for data requiring fast clock-to-output performance. IOEs can be used as input, output, or bidirectional pins. Altera Corporation 37 APEX 20KC Programmable Logic Device Data Sheet APEX 20KC devices include an enhanced IOE, which drives the FastRow interconnect. The FastRow interconnect connects a column I/O pin directly to the LAB local interconnect within two MegaLAB structures. This feature provides fast setup times for pins that drive high fan-outs with complex logic, such as PCI designs. For fast bidirectional I/O timing, LE registers using local routing can improve setup times and OE timing. The APEX 20KC IOE also includes direct support for open-drain operation, giving faster clock-to-output for open-drain signals. Some programmable delays in the APEX 20KC IOE offer multiple levels of delay to fine-tune setup and hold time requirements. The Quartus II Compiler sets these delays by default to minimize setup time while providing a zero hold time. The Quartus II Compiler uses the programmable inversion option to invert signals from the row and column interconnect automatically where appropriate. Because the APEX 20KC IOE offers one output enable per pin, the Quartus II Compiler can emulate open-drain operation efficiently. The APEX 20KC IOE includes programmable delays that can be activated to ensure zero hold times, minimum clock-to-output times, input IOE register-to-core register transfers, or core-to-output IOE register transfers. A path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Table 9 describes the APEX 20KC programmable delays and their logic options in the Quartus II software. Table 9. APEX 20KC Programmable Delay Chains Programmable Delay Input pin to core delay Input pin to input register delay Core to output register delay Output register tCO delay Clock enable delay Quartus II Logic Option Decrease input delay to internal cells Decrease input delay to input registers Decrease input delay to output register Increase delay to output pin Increase clock enable delay The Quartus II Compiler can program these delays automatically to minimize setup time while providing a zero hold time. 38 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The register in the APEX 20KC IOE can be programmed to power-up high or low after configuration is complete. If it is programmed to power-up low, an asynchronous clear can control the register. If it is programmed to power-up high, an asynchronous preset can control the register. This feature is useful for cases where the APEX 20KC device controls an activelow input or another device; it prevents inadvertent activation of the input upon power-up. Figure 25 shows how fast bidirectional I/O pins are implemented in APEX 20KC devices. This feature is useful for cases where the APEX 20KC device controls an active-low input or another device; it prevents inadvertent activation of the input upon power-up. Altera Corporation 39 APEX 20KC Programmable Logic Device Data Sheet Figure 25. APEX 20KC Bidirectional I/O Registers Row, Column, FastRow, 4 Dedicated or Local Interconnect Clock Inputs 4 Dedicated Inputs Peripheral Control Bus Notes (1), (2) OE Register D Q VCC ENA CLRN Chip-Wide Reset VCC OE[7..0] Chip-Wide Output Enable Input Pin to Core Delay (1) Input Pin to Core Delay (1) 12 4 VCC Core to Output Register Delay Input Pin to Input Register Delay CLK[1..0] Output Register D Q Output Register t CO Delay VCCIO Optional PCI Clamp Open-Drain Output Slew-Rate Control ENA CLRN/ PRN CLK[3..0] VCC ENA[5..0] Clock Enable Delay (1) VCC CLRn[1..0] Chip-Wide Reset Input Register D VCC ENA CLRN Q Input Pin to Core Delay (1) VCC Chip-Wide Reset 40 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Notes to Figure 25: (1) (2) This programmable delay has four settings: off and three levels of delay. The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin. Each IOE drives a row, column, MegaLAB, or local interconnect when used as an input or bidirectional pin. A row IOE can drive a local, MegaLAB, row, and column interconnect; a column IOE can drive the column interconnect. Figure 26 shows how a row IOE connects to the interconnect. Figure 26. Row IOE Connection to the Interconnect Row Interconnect MegaLAB Interconnect Any LE can drive a pin through the row, column, and MegaLAB interconnect. IOE LAB Each IOE can drive local, MegaLAB, row, and column interconnect. Each IOE data and OE signal is driven by the local interconnect. IOE An LE can drive a pin through the local interconnect for faster clock-to-output times. Altera Corporation 41 APEX 20KC Programmable Logic Device Data Sheet Figure 27 shows how a column IOE connects to the interconnect. Figure 27. Column IOE Connection to the Interconnect Each IOE can drive a column interconnect. IOEs can also drive FastRow and column interconnects. Each IOE data and OE signal is driven by local interconnect. IOE IOE An LE or ESB can drive a pin through a local interconnect for faster clock-to-output times. LAB Any LE or ESB can drive a column pin through a row, column, and MegaLAB interconnect. Column Interconnect Row Interconnect MegaLAB Interconnect Dedicated Fast I/O Pins APEX 20KC devices incorporate an enhancement to support bidirectional pins with high internal fan-out such as PCI control signals. These pins are called dedicated fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and replace dedicated inputs. These pins can be used for fast clock, clear, or high fan-out logic signal distribution. They also can drive out. The dedicated fast I/O pin data output and tri-state control are driven by local interconnect from the adjacent MegaLAB for high speed. 42 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Advanced I/O Standard Support APEX 20KC IOEs support the following I/O standards: LVTTL, LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS, LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2 Class I and II. f For more information on I/O standards supported by APEX 20KC devices, see Application Note 117 (Using Selectable I/O Standards in Altera Devices). The APEX 20KC device contains eight I/O banks. In QFP packages, the banks are linked to form four I/O banks. The I/O banks directly support all standards except LVDS and LVPECL. All I/O banks can support LVDS and LVPECL at up to 156 Mbps per channel with the addition of external resistors. In addition, one block within a bank contains circuitry to support high-speed True-LVDS and LVPECL inputs, and another block within a bank supports high-speed True-LVDS and LVPECL outputs. The LVDS blocks support all of the I/O standards. Each I/O bank has its own VCCIO pins. A single device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can support a different standard independently. Each bank can also use a separate VREF level so that each bank can support any of the terminated standards (such as SSTL-3) independently. Within a bank, any one of the terminated standards can be supported. EP20K400C and larger APEX 20KC devices support the LVDS interface for data pins (EP20K200C devices support LVDS clock pins, but not data pins). EP20K400C and EP20K600C devices support LVDS for data pins at up to 840 Mbps per channel. EP20K1000C devices support LVDS on 16 channels at up to 750 Mbps. Each bank can support multiple standards with the same VCCIO for output pins. Each bank can support one voltage-referenced I/O standard, but it can support multiple I/O standards with the same VCCIO voltage level. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. When the LVDS banks are not used for the LVDS I/O standard, they support all of the other I/O standards. Figure 28 shows the arrangement of the APEX 20KC I/O banks. Altera Corporation 43 APEX 20KC Programmable Logic Device Data Sheet Figure 28. APEX 20KC I/O Banks I/O Bank 1 I/O Bank 2 I/O Bank 8 LVDS Output Block (2) (1) I/O Bank 7 Regular I/O Banks Support ■ LVPECL ■ LVTTL ■ LVCMOS ■ 2.5 V ■ 1.8 V ■ 3.3-V PCI ■ GTL+ ■ HSTL ■ SSTL-2 Class I and II ■ SSTL-3 Class I and II ■ CTT ■ AGP Individual Power Bus I/O Bank 3 (1) LVDS Input Block (2) I/O Bank 4 I/O Bank 6 Notes to Figure 28: (1) (2) I/O Bank 5 For more information on placing I/O pins in LVDS blocks, refer to the “Guidelines for Using LVDS Blocks” section in Application Note 120 (Using LVDS in APEX 20KE Devices). If the LVDS input and output blocks are not used for LVDS, they can support all of the I/O standards and can be used as input, output, or bidirectional pins with VCCIO set to 3.3 V, 2.5 V, or 1.8 V. Power Sequencing & Hot Socketing Because APEX 20KC devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order. 44 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Signals can be driven into APEX 20KC devices before and during powerup without damaging the device. In addition, APEX 20KC devices do not drive out during power-up. Once operating conditions are reached and the device is configured, APEX 20KC devices operate as specified by the user. MultiVolt I/O Interface The APEX architecture supports the MultiVolt I/O interface feature, which allows APEX devices in all packages to interface with systems of different supply voltages. The devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). APEX 20KC devices support the MultiVolt I/O interface feature. The APEX 20KC VCCINT pins must always be connected to a 1.8-V power supply. With a 1.8-V VCCINT level, input pins are 1.8-V, 2.5-V, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.8-V, 2.5-V, or 3.3-V power supply, depending on the I/O standard requirements. When the VCCIO pins are connected to a 1.8-V power supply, the output levels are compatible with 1.8-V systems. When VCCIO pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3 V and compatible with 3.3-V or 5.0-V systems. An APEX 20KC device is 5.0-V tolerant with the addition of a resistor and the PCI clamp diode enabled. f For more information on 5.0-V tolerance, refer to the “5.0-V Tolerance in APEX 20KE Devices White Paper,” as the information found therein also applies to APEX 20KC devices. Table 10 summarizes APEX 20KC MultiVolt I/O support. Table 10. APEX 20KC MultiVolt I/O Support VCCIO (V) 1.8 1.8 2.5 3.3 Notes to Table 10: (1) (2) (3) The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO, except for the 5.0-V input case. An APEX 20KC device can be made 5.0-V tolerant with the addition of an external resistor and the PCI clamp diode enabled. When VCCIO = 3.3 V, an APEX 20KC device can drive a 2.5-V device with 3.3-V tolerant inputs. Input Signals (V) 2.5 v (1) v v Output Signals (V) 5.0 1.8 v v v (2) v (3) v v 3.3 v (1) v (1) v 2.5 3.3 5.0 v Altera Corporation 45 APEX 20KC Programmable Logic Device Data Sheet Open-drain output pins on APEX 20KC devices (with a series resistor and a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a VIH of 3.5 V. When the pin is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-drain pin will only drive low or tristate; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor. ClockLock & ClockBoost Features APEX 20KC devices support the ClockLock and ClockBoost clock management features, which are implemented with PLLs. The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device. This reduction minimizes clock-to-output and setup times while maintaining zero hold times. The ClockBoost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by sharing resources within the device. The ClockBoost circuitry allows the designer to distribute a low-speed clock and multiply that clock on-device. APEX 20KC devices include a high-speed clock tree; unlike ASICs, the user does not have to design and optimize the clock tree. The ClockLock and ClockBoost features work in conjunction with the APEX 20KC device’s high-speed clock to provide significant improvements in system performance and bandwidth. APEX 20KC devices in -7 and -8 speed grades have PLLs and support the ClockLock and ClockBoost features. The ClockLock and ClockBoost features in APEX 20KC devices are enabled through the Quartus II software. External devices are not required to use these features. APEX 20KC ClockLock Feature APEX 20KC devices include up to four PLLs, which can be used independently. Two PLLs are designed for either general-purpose use or LVDS use (on devices that support LVDS I/O pins). The remaining two PLLs are designed for general-purpose use. The EP20K200C devices have two PLLs; the EP20K400C and larger devices have four PLLs. The following sections describe some of the features offered by the APEX 20KC PLLs. External PLL Feedback The ClockLock circuit’s output can be driven off-chip to clock other devices in the system; further, the feedback loop of the PLL can be routed off-chip. This feature allows the designer to exercise fine control over the I/O interface between the APEX 20KC device and another high-speed device, such as SDRAM. 46 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Clock Multiplication The APEX 20KC ClockBoost circuit can multiply or divide clocks by a programmable number. The clock can be multiplied by m/(n × k), where m and k range from 2 to 160 and n ranges from 1 to 16. Clock multiplication and division can be used for time-domain multiplexing and other functions, which can reduce design LE requirements. Clock Phase & Delay Adjustment The APEX 20KC ClockShift feature allows the clock phase and delay to be adjusted. The clock phase can be adjusted by 90° steps. The clock delay can be adjusted to increase or decrease the clock delay by an arbitrary amount, up to one clock period. LVDS Support All APEX 20KC devices support differential LVDS buffers on the input and output clock signals that interface with external devices. This is controlled in the Quartus II software by assigning the clock pins with an LVDS I/O standard assignment. Two high-speed PLLs are designed to support the LVDS interface. When using LVDS, the I/O clock runs at a slower rate than the data transfer rate. Thus, PLLs are used to multiply the I/O clock internally to capture the LVDS data. For example, an I/O clock may run at 105 MHz to support 840 Mbps LVDS data transfer. In this example, the PLL multiplies the incoming clock by eight to support the high-speed data transfer. You can use PLLs in EP20K400C and larger devices for high-speed LVDS interfacing. Lock Signals The APEX 20KC ClockLock circuitry supports individual LOCK signals. The LOCK signal drives high when the ClockLock circuit has locked onto the input clock. The LOCK signals are optional for each ClockLock circuit; when not used, they are I/O pins. Altera Corporation 47 APEX 20KC Programmable Logic Device Data Sheet ClockLock & ClockBoost Timing Parameters For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device. The clock generated by the ClockLock and ClockBoost circuitry must also meet certain specifications. If the incoming clock meets these requirements during configuration, the APEX 20KC ClockLock and ClockBoost circuitry will lock onto the clock during configuration. The circuit will be ready for use immediately after configuration. In APEX 20KC devices, the clock input standard is programmable, so the PLL cannot respond to the clock until the device is configured. The PLL locks onto the input clock as soon as configuration is complete. Figure 29 shows the incoming and generated clock specifications. 1 For more information on ClockLock and ClockBoost circuitry, see Application Note 115: Using the ClockLock and ClockBoost PLL Features in APEX Devices. Figure 29. Specifications for the Incoming & Generated Clocks The tI parameter refers to the nominal input clock period; the tO parameter refers to the nominal output clock period. f CLK1, f CLK2 , f CLK4 t INDUTY t I + t CLKDEV Input Clock t R (1) t F (1) tO tI + t INCLKSTB t OUTDUTY ClockLock Generated Clock tO tO + t JITTER tO t JITTER Note to Figure 29: (1) Rise and fall times are measured from 10% to 90%. 48 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Tables 11 and 12 summarize the ClockLock and ClockBoost parameters for APEX 20KC devices. Table 11. APEX 20KC ClockLock & ClockBoost Parameters Symbol tR tF t INDUTY t INJITTER tOUTJITTER Note (1) Min Typ Max 5 5 40 60 2% of input period 0.35% of output period 45 55 40 Parameter Input rise time Input fall time Input duty cycle Input jitter peak-to-peak RMS jitter on ClockLock or ClockBoost-generated clock Duty cycle for ClockLock or ClockBoost-generated clock Condition Unit ns ns % % % tOUTDUTY % µs tLOCK (2), (3) Time required for ClockLock or ClockBoost to acquire lock Table 12. APEX 20KC Clock Input & Output Parameters (Part 1 of 2) Symbol Parameter I/O Standard Note (1) -8 Speed Grade Min 200 1.5 20 (5) (5) (5) (5) (5) (5) (5) (5) (5) -7 Speed Grade Min Max 500 335 335 (5) (5) (5) (5) (5) (5) (5) (5) (5) Units Max 500 200 200 (5) (5) (5) (5) (5) (5) (5) (5) (5) MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz fVCO (4) fCLOCK0 fCLOCK1 fCLOCK0_EXT Voltage controlled oscillator operating range Clock0 PLL output frequency for internal use Clock1 PLL output frequency for internal use Output clock frequency for external clock0 output 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class I SSTL-2 Class II SSTL-3 Class I SSTL-3 Class II LVDS 200 1.5 20 (5) (5) (5) (5) (5) (5) (5) (5) (5) Altera Corporation 49 APEX 20KC Programmable Logic Device Data Sheet Table 12. APEX 20KC Clock Input & Output Parameters (Part 2 of 2) Symbol Parameter I/O Standard Note (1) -8 Speed Grade Min (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) -7 Speed Grade Min Max (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) Units Max (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz fCLOCK1_EXT Output clock frequency for external clock1 output 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class I SSTL-2 Class II SSTL-3 Class I SSTL-3 Class II LVDS (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) fIN Input clock frequency 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class I SSTL-2 Class II SSTL-3 Class I SSTL-3 Class II LVDS Notes to Tables 11 and 12: (1) (2) (3) All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications are not met, creating an erroneous clock within the device. The maximum lock time is 40 µs or 2,000 input clock cycles, whichever occurs first. Before configuration, the PLL circuits are disable and powered down. During configuration, the PLLs remain disabled. The PLLs begin to lock once the device is in the user mode. If the clock enable feature is used, lock begins once the CLKLK_ENA pin goes high in user mode. The PLL VCO operating range is 200 MHz ≤ fVCO ≤ 840 MHz for LVDS mode. Contact Altera Applications for information on these parameters. (4) (5) SignalTap Embedded Logic Analyzer APEX 20KC devices include device enhancements to support the SignalTap embedded logic analyzer. By including this circuitry, the APEX 20KC device provides the ability to monitor design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages such as FineLine BGA packages because adding a connection to a pin during the debugging process can be difficult after a board is designed and manufactured. 50 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet IEEE Std. 1149.1 (JTAG) Boundary-Scan Support All APEX 20KC devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed before or after configuration, but not during configuration. APEX 20KC devices can also use the JTAG port for configuration with the Quartus II software or with hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Finally, APEX 20KC devices use the JTAG port to monitor the logic operation of the device with the SignalTap embedded logic analyzer. APEX 20KC devices support the JTAG instructions shown in Table 13. Table 13. APEX 20KC JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap embedded logic analyzer. EXTEST BYPASS Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. Used when configuring an APEX 20KC device via the JTAG port with a MasterBlasterTM or ByteBlasterMVTM download cable, or when using a Jam File or Jam Byte-Code File via an embedded processor. Monitors internal device operation with the SignalTap embedded logic analyzer. USERCODE IDCODE ICR Instructions SignalTap Instructions Altera Corporation 51 APEX 20KC Programmable Logic Device Data Sheet The APEX 20KC device instruction register length is 10 bits. The APEX 20KC device USERCODE register length is 32 bits. Tables 14 and 15 show the boundary-scan register length and device IDCODE information for APEX 20KC devices. Table 14. APEX 20KC Boundary-Scan Register Length Device EP20K200C EP20K400C EP20K600C EP20K1000C Boundary-Scan Register Length 1,164 1,506 1,806 2,190 Table 15. 32-Bit APEX 20KC Device IDCODE Device Version (4 Bits) EP20K200C EP20K400C EP20K600C EP20K1000C Notes to Table 15: (1) (2) The most significant bit (MSB) is on the left. The IDCODE’s least significant bit (LSB) is always 1. IDCODE (32 Bits) (1) Part Number (16 Bits) 1000 0010 0000 0000 1000 0100 0000 0000 1000 0110 0000 0000 1001 0000 0000 0000 Manufacturer Identity (11 Bits) 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 1 (1 Bit) (2) 1 1 1 1 0000 0000 0000 0000 Figure 30 shows the timing requirements for the JTAG signals. 52 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 30. APEX 20KC JTAG Waveforms TMS TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH tJSZX tJSCO tJSXZ Table 16 shows the JTAG timing parameters and values for APEX 20KC devices. Table 16. APEX 20KC JTAG Timing Parameters & Values Symbol tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance 20 45 35 35 35 Parameter Min 100 50 50 20 45 Max Unit ns ns ns ns ns 25 25 25 ns ns ns ns ns ns ns ns f For more information, see the following documents: ■ Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) Altera Corporation 53 APEX 20KC Programmable Logic Device Data Sheet ■ Jam Programming & Test Language Specification Generic Testing Each APEX 20KC device is functionally tested. Complete testing of each configurable SRAM bit and all logic functionality ensures 100% yield. AC test measurements for APEX 20KC devices are made under conditions equivalent to those defined in the “Timing Model” section on page 65. Multiple test patterns can be used to configure devices during all stages of the production flow. AC test criteria include: ■ ■ ■ ■ Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast-ground-current transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Operating Conditions Tables 17 through 20 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for 1.8-V APEX 20KC devices. Note (1) Min –0.5 –0.5 –0.5 –25 No bias Under bias PQFP, RQFP, TQFP, and BGA packages, under bias Ceramic PGA packages, under bias –65 –65 Table 17. APEX 20KC Device Absolute Maximum Ratings Symbol Parameter Conditions With respect to ground (2) Max 2.5 4.6 4.6 25 150 135 135 150 Unit V V V mA °C °C °C °C V CCINT Supply voltage V CCIO VI I OUT T STG T AMB TJ DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature 54 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 18. APEX 20KC Device Recommended Operating Conditions Symbol V CCINT V CCIO Parameter Supply voltage for internal logic and input buffers Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation Supply voltage for output buffers, 1.8-V operation (3), (4) (3), (4) (3), (4) (3), (4) (2), (5) Conditions Min 1.71 (1.71) 3.00 (3.00) 2.375 (2.375) 1.71 (1.71) –0.5 0 0 –40 Max 1.89 (1.89) 3.60 (3.60) 2.625 (2.625) 1.89 (1.89) 4.1 V CCIO 85 100 40 40 Unit V V V V V V °C °C ns ns VI VO TJ tR tF Input voltage Output voltage Operating junction temperature Input rise time (10% to 90%) Input fall time (90% to 10%) For commercial use For industrial use Table 19. APEX 20KC Device DC Operating Conditions Symbol II I OZ I CC0 Notes (6), (7) Min –10 –10 10 Parameter Input pin leakage current (8) Tri-stated I/O pin leakage current (8) V CC supply current (standby) (All ESBs in power-down mode) Conditions V I = 3.6 to 0.0 V V O = 4.1 to –0.5 V V I = ground, no load, no toggling inputs, -7 speed grade V I = ground, no load, no toggling inputs, -8, -9 speed grades Typ Max 10 10 Unit µA µA mA 5 mA R CONF Value of I/O pin pull-up resistor before and during configuration V CCIO = 3.0 V (9) V CCIO = 2.375 V (9) V CCIO = 1.71 V (9) 20 30 60 50 80 150 kΩ kΩ kΩ 1 DC operating specifications on APEX 20KC I/O standards are listed in Tables 21 to 35. Altera Corporation 55 APEX 20KC Programmable Logic Device Data Sheet Table 20. APEX 20KC Device Capacitance Symbol CIN CINCLK COUT (1) (2) Note (10) Conditions Min Max 8 12 8 Parameter Input capacitance Input capacitance on dedicated clock pin Output capacitance Unit pF pF pF VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz Notes to Tables 17 through 20: See the Operating Requirements for Altera Devices Data Sheet. Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for input currents less than 100 mA and time periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. (5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (6) Typical values are for T A = 25° C, V CCINT = 1.8 V, and V CCIO = 1.8 V, 2.5 V or 3.3 V. (7) These values are specified under the APEX 20KC device recommended operating conditions, shown in Table 18 on page 55. (8) This value is specified for normal device operation. The value may vary during power-up. (9) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO. (10) Capacitance is sample-tested only. Tables 21 through 35 list the DC operating specifications for the supported I/O standards. These tables list minimal specifications only; APEX 20KC devices may exceed these specifications. Table 21. LVTTL I/O Specifications Symbol VCCIO VIH VIL II VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum 3.0 2.0 –0.3 Maximum 3.6 VCCIO + 0.3 0.8 10 Units V V V µA V VIN = 0 V or 3.3 V IOH = –12 mA, VCCIO = 3.0 V (1) IOL = 12 mA, VCCIO = 3.0 V (2) –10 2.4 0.4 V 56 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 22. LVCMOS I/O Specifications Symbol VCCIO VIH VIL II VOH VOL Parameter Power supply voltage range High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum 3.0 2.0 –0.3 Maximum 3.6 VCCIO + 0.3 0.8 10 Units V V V µA V VIN = 0 V or 3.3 V VCCIO = 3.0 V IOH = –0.1 mA (1) VCCIO = 3.0 V IOL = 0.1 mA (2) –10 VCCIO – 0.2 0.2 V Table 23. 2.5-V I/O Specifications Symbol VCCIO VIH VIL II VOH Parameter Output supply voltage High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum 2.375 1.7 –0.3 Maximum 2.625 VCCIO + 0.3 0.8 10 Units V V V µA V V V VIN = 0 V or 3.3 V IOH = –0.1 mA (1) IOH = –1 mA (1) IOH = –2 mA (1) IOL = 0.1 mA (2) IOL = 1 mA (2) IOL = 2 mA (2) –10 2.1 2.0 1.7 VOL 0.2 0.4 0.7 V V V Altera Corporation 57 APEX 20KC Programmable Logic Device Data Sheet Table 24. 1.8-V I/O Specifications Symbol VCCIO VIH VIL II VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum 1.7 0.65 × VCCIO Maximum 1.9 VCCIO + 0.3 0.35 × VCCIO Units V V V µA V VIN = 0 V or 3.3 V IOH = –2 mA (1) IOL = 2 mA (2) –10 VCCIO – 0.45 10 0.45 V Table 25. 3.3-V PCI Specifications Symbol VCCIO VIH VIL II VOH VOL Parameter I/O supply voltage High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum 3.0 0.5 × VCCIO –0.5 Typical 3.3 Maximum 3.6 VCCIO + 0.5 0.3 × VCCIO 10 Units V V V µA V 0 < VIN < VCCIO IOUT = –500 µA IOUT = 1,500 µA –10 0.9 × VCCIO 0.1 × VCCIO V 58 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 26. 3.3-V PCI-X Specifications Symbol VCCIO VIH VIL VIPU IIL VOH VOL Lpin Parameter Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage Input pin leakage current High-level output voltage Low-level output voltage Pin Inductance Conditions Minimum 3.0 0.5 × VCCIO –0.5 0.7 × VCCIO Typical 3.3 Maximum 3.6 VCCIO + 0.5 0.35 × VCCIO Units V V V V 0 < VIN < VCCIO IOUT = –500 µA IOUT = 1,500 µA –10.0 0.9 × VCCIO 10.0 µA V 0.1 × VCCIO 15.0 V nH Table 27. 3.3-V LVDS I/O Specifications Symbol VCCIO VOD ∆ VOD Parameter I/O supply voltage Differential output voltage Change in VOD between high and low Change in VOS between high and low Differential input threshold Receiver input voltage range Receiver differential input resistor (external to APEX devices) Conditions RL = 100 Ω RL = 100 Ω Minimum 3.135 250 Typical 3.3 Maximum 3.465 650 50 Units V mV mV VOS ∆ VOS Output offset voltage RL = 100 Ω RL = 100 Ω 1.125 1.25 1.375 50 V mV VTH VIN RL VCM = 1.2 V –100 0.0 90 100 100 2.4 110 mV V Ω Altera Corporation 59 APEX 20KC Programmable Logic Device Data Sheet Table 28. GTL+ I/O Specifications Symbol VTT VREF VIH VIL VOL Parameter Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage Conditions Minimum 1.35 0.88 VREF + 0.1 Typical 1.5 1.0 Maximum 1.65 1.12 Units V V V VREF – 0.1 IOL = 36 mA (2) 0.65 V V Table 29. SSTL-2 Class I Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 2.375 VREF – 0.04 1.15 VREF + 0.18 –0.3 Typical 2.5 VREF 1.25 Maximum 2.625 VREF + 0.04 1.35 VCCIO + 0.3 VREF – 0.18 Units V V V V V V IOH = –7.6 mA (1) IOL = 7.6 mA (2) VTT + 0.57 VTT – 0.57 V 60 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 30. SSTL-2 Class II Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 2.375 VREF – 0.04 1.15 VREF + 0.18 –0.3 Typical 2.5 VREF 1.25 Maximum 2.625 VREF + 0.04 1.35 VCCIO + 0.3 VREF – 0.18 Units V V V V V V IOH = –15.2 mA (1) IOL = 15.2 mA (2) VTT + 0.76 VTT – 0.76 V Table 31. SSTL-3 Class I Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 3.0 VREF – 0.05 1.3 VREF + 0.2 –0.3 Typical 3.3 VREF 1.5 Maximum 3.6 VREF + 0.05 1.7 VCCIO + 0.3 VREF – 0.2 Units V V V V V V IOH = –8 mA (1) IOL = 8 mA (2) VTT + 0.6 VTT – 0.6 V Altera Corporation 61 APEX 20KC Programmable Logic Device Data Sheet Table 32. SSTL-3 Class II Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 3.0 VREF – 0.05 1.3 VREF + 0.2 –0.3 Typical 3.3 VREF 1.5 Maximum 3.6 VREF + 0.05 1.7 VCCIO + 0.3 VREF – 0.2 Units V V V V V V IOH = –16 mA (1) IOL = 16 mA (2) VTT + 0.8 VTT – 0.8 V Table 33. HSTL Class I I/O Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 1.71 VREF – 0.05 0.68 VREF + 0.1 –0.3 Typical 1.8 VREF 0.75 Maximum 1.89 VREF + 0.05 0.90 VCCIO + 0.3 VREF – 0.1 Units V V V V V V IOH = –8 mA (1) IOL = 8 mA (2) VCCIO – 0.4 0.4 V 62 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 34. 3.3-V AGP I/O Specifications Symbol VCCIO VREF VIH VIL VOH VOL II Parameter I/O supply voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input pin leakage current Conditions Minimum 3.15 0.39 × VCCIO 0.5 × VCCIO Typical 3.3 Maximum 3.45 0.41 × VCCIO VCCIO + 0.5 0.3 × VCCIO Units V V V V V V µA IOUT = –500 µA IOUT = 1,500 µA 0 < VIN < VCCIO 0.9 × VCCIO 3.6 0.1 × VCCIO –10 10 Table 35. CTT I/O Specifications Symbol VCCIO VTT/VREF (3) VIH VIL II VOH VOL IO Parameter I/O supply voltage Termination and reference voltage High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum 3.0 1.35 VREF + 0.2 Typical 3.3 1.5 Maximum 3.6 1.65 Units V V V VREF – 0.2 0 < VIN < VCCIO IOH = –8 mA (1) IOL = 8 mA (2) –10 –10 VREF + 0.4 VREF – 0.4 10 10 V µA V V µA GND ≤ VOUT ≤ VCCIO Output leakage current (when output is high Z) Notes to Tables 21 through 35: (1) (2) (3) The IOH parameter refers to high-level output current. The IOL parameter refers to low-level output current. This parameter applies to open-drain pins as well as output pins. VREF specifies center point of switching range. Figure 31 shows the output drive characteristics of APEX 20KC devices. Altera Corporation 63 APEX 20KC Programmable Logic Device Data Sheet Figure 31. Output Drive Characteristics of APEX 20KC Devices 120 110 100 90 80 Typical IO 70 Output Current (mA) 60 50 40 30 20 10 0.5 1 1.5 2 2.5 3 IOH VCCINT = 1.8 V VCCIO = 3.3 V Room Temperature IOL Note (1) 60 55 50 45 40 VCCINT = 1.8 V VCCIO = 2.5V Room Temperature IOL Typical IO 35 Output Current (mA) 30 25 20 15 10 5 0.5 1 1.5 IOH 2 2.5 3 Vo Output Voltage (V) Vo Output Voltage (V) 26 24 22 20 18 Typical IO 16 Output Current (mA) 14 12 10 8 6 4 2 0.5 1 1.5 2.0 IOH VCCINT = 1.8V VCCIO = 1.8V Room Temperature IOL Vo Output Voltage (V) Note to Figure 31: (1) These are transient (AC) currents. 64 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Timing Model The high-performance FastTrack and MegaLAB interconnect routing resources ensure predictable performance, accurate simulation, and accurate timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and therefore have unpredictable performance. Figure 32 shows the fMAX timing model for APEX 20KC devices. Figure 32. fMAX Timing Model LE t SU Routing Delay tH t t CO LUT t t t F1—4 F5—20 F20+ ESB t t t t t t t t t ESBARC ESBSRC ESBAWC ESBSWC ESBWASU ESBWDSU ESBSRASU ESBWESU ESBDATASU t ESBWADDRSU t ESBRADDRSU t ESBDATACO1 t ESBDATACO2 t ESBDD t PD t PTERMSU t PTERMCO Figures 33 and 34 show the asynchronous and synchronous timingwaveforms, respectively, for the ESB macroparameters in Table 37. Altera Corporation 65 APEX 20KC Programmable Logic Device Data Sheet Figure 33. ESB Asynchronous Timing Waveforms ESB Asynchronous Read RE Rdaddress a0 a1 a2 tESBARC a3 Data-Out d0 d1 d2 d3 ESB Asynchronous Write WE tESBWP tESBWDSU tESBWDH Data-In din0 tESBWASU tESBWCCOMB din1 tESBWAH Wraddress a0 a1 tESBDD a2 Data-Out din0 din1 dout2 66 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 34. ESB Synchronous Timing Waveforms ESB Synchronous Read WE Rdaddress a0 tESBDATASU a1 tESBDATAH a2 tESBARC a3 CLK tESBDATACO2 Data-Out d1 d2 d3 ESB Synchronous Write (ESB Output Registers Used) WE Data-In din1 din2 din3 Wraddress a0 a1 tESBWESU tESBDATASU a2 tESBDATAH a3 tESBWEH a2 CLK tESBSWC tESBDATACO1 Data-Out dout0 dout1 din1 din2 din3 din2 Figure 35 shows the timing model for bidirectional I/O pin timing. Altera Corporation 67 APEX 20KC Programmable Logic Device Data Sheet Figure 35. Synchronous Bidirectional Pin External Timing OE Register (1) D PRN Q Dedicated Clock tXZBIDIR tZXBIDIR tOUTCOBIDIR Bidirectional Pin CLRN Output IOE Register D PRN Q CLRN Input Register (1), (2) PRN D Q tINSUBIDIR tINHBIDIR CLRN Notes to Figure 35: (1) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin. Use the “Output Enable Routing = Single-Pin” option in the Quartus II software to set the output enable register. Use the “Decrease Input Delay to Internal Cells = OFF” option in the Quartus II software to set the LAB-adjacent input register. This maintains a zero hold time for LAB-adjacent registers while giving a fast, position-independent setup time. Set “Decrease Input Delay to Internal Cells = ON” and move the input register farther away from the bidirectional pin for a faster setup time with zero hold time. The exact position where zero hold occurs with the minimum setup time varies with device density and speed grade. (2) Tables 36 to 38 describes the fMAX timing parameters shown in Figure 32. Table 39 describes the functional timing parameters. Table 36. APEX 20KC fMAX LE Timing Parameters Symbol tSU tH tCO tLUT LE register setup time before clock LE register hold time before clock LE register clock-to-output delay LUT delay for data-in to data-out Parameter 68 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 37. APEX 20KC fMAX ESB Timing Parameters Symbol tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPD tPTERMSU tPTERMCO ESB asynchronous read cycle time ESB synchronous read cycle time ESB asynchronous write cycle time ESB synchronous write cycle time ESB write address setup time with respect to WE ESB write address hold time with respect to WE ESB data setup time with respect to WE ESB data hold time with respect to WE ESB read address setup time with respect to RE ESB read address hold time with respect to RE ESB WE setup time before clock when using input register ESB data setup time before clock when using input register ESB write address setup time before clock when using input registers ESB read address setup time before clock when using input registers ESB clock-to-output delay when using output registers ESB clock-to-output delay without output registers ESB data-in to data-out delay for RAM mode ESB macrocell input to non-registered output ESB macrocell register setup time before clock ESB macrocell register clock-to-output delay Parameter Table 38. APEX 20KC fMAX Routing Delays Symbol tF1-4 tF5-20 tF20+ Parameter Fan-out delay estimate using local interconnect Fan-out delay estimate using MegaLab interconnect Fan-out delay estimate using FastTrack interconnect Altera Corporation 69 APEX 20KC Programmable Logic Device Data Sheet Table 39. APEX 20KC Minimum Pulse Width Timing Parameters Symbol tCH tCL tCLRP tPREP tESBCH tESBCL tESBWP tESBRP Parameter Minimum clock high time from clock pin Minimum clock low time from clock pin LE clear pulse width LE preset pulse width Clock high time Clock low time Write pulse width Read pulse width Tables 40 and 41 describe APEX 20KC external timing parameters. The timing values for these pin-to-pin delays are reported for all pins using the 3.3-V LVTTL I/O standard. Table 40. APEX 20KC External Timing Parameters Symbol tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL Note (1) Conditions Clock Parameter Setup time with global clock at IOE register Hold time with global clock at IOE register Clock-to-output delay with global clock at IOE output register Setup time with PLL clock at IOE input register Hold time with PLL clock at IOE input register Clock-to-output delay with PLL clock at IOE output register (2) (2) 70 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 41. APEX 20KC External Bidirectional Timing Parameters Symbol tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL Note (1) Condition Parameter Setup time for bidirectional pins with global clock at LAB-adjacent input register Hold time for bidirectional pins with global clock at LAB-adjacent input register Clock-to-output delay for bidirectional pins with global clock at IOE register Synchronous output enable register to output buffer disable delay Synchronous output enable register to output buffer enable delay Setup time for bidirectional pins with PLL clock at LAB-adjacent input register Hold time for bidirectional pins with PLL clock at LAB-adjacent input register Clock-to-output delay for bidirectional pins with PLL clock at IOE register (2) Synchronous output enable register to output buffer disable delay with PLL Synchronous output enable register to output buffer enable delay with PLL (2) (2) (2) (2) (2) Notes to Tables 40 and 41: (1) (2) These timing parameters are sample-tested only. For more information, refer to Table 43. Tables 42 and 43 define the timing delays for each I/O standard. Some output standards require test load circuits for AC timing measurements as shown in Figures 36 through 38. Table 42. APEX 20KC Selectable I/O Standard Input Adder Delays (Part 1 of 2) Symbol LVCMOS LVTTL 2.5 V 1.8 V PCI GTl+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II Note (1) Condition Parameter Input adder delay for the LVCMOS I/O standard Input adder delay for the LVTTL I/O standard Input adder delay for the 2.5-V I/O standard Input adder delay for the 1.8-V I/O standard Input adder delay for the PCI I/O standard Input adder delay for the GTL+ I/O standard Input adder delay for the SSTL-3 Class I I/O standard Input adder delay for the SSTL-3 Class II I/O standard Input adder delay for the SSTL -2 Class I I/O standard Input adder delay for the SSTL -2 Class II I/O standard Altera Corporation 71 APEX 20KC Programmable Logic Device Data Sheet Table 42. APEX 20KC Selectable I/O Standard Input Adder Delays (Part 2 of 2) Symbol LVDS CTT AGP Note (1) Condition Parameter Input adder delay for the LVDS I/O standard Input adder delay for the CTT I/O standard Input adder delay for the AGP I/O standard Table 43. APEX 20KC Selectable I/O Standard Output Adder Delays Symbol LVCMOS LVTTL Note (1) Condition Parameter Output adder delay for the LVCMOS I/O standard Output adder delay for the LVTTL I/O standard Cload = 35 pF Rup = 564.5 Ω Rdn = 430 Ω (2) Cload = 35 pF Rup = 450 Ω Rdn = 450 Ω (2) Cload = 35 pF Rup = 520 Ω Rdn = 480 Ω (2) Cload = 10 pF Rup = 1M Ω Rdn = 25 Ω (2) Cload = 30 pF Rup = 25 Ω (2) 2.5 V Output adder delay for the 2.5-V I/O standard 1.8 V Output adder delay for the 1.8-V I/O standard PCI Output adder delay for the PCI I/O standard GTl+ SSTL-3 Class I Output adder delay for the GTL+ I/O standard Output adder delay for the SSTL-3 Class I I/O standard Cload1 = 0 pF Cload2 = 30 pF R = 25 Ω (2) Output adder delay for the SSTL-3 Class II I/O standard Cload1 = 0 pF Cload2 = 30 pF R = 25 Ω (2) Output adder delay for the SSTL-2 Class I I/O standard Output adder delay for the SSTL-2 Class II I/O standard Output adder delay for the LVDS I/O standard Output adder delay for the CTT I/O standard Output adder delay for the AGP I/O standard Cload = 4 pF R=100 Ω (2) SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II LVDS CTT AGP Note to Tables 42 and 43: (1) (2) These delays report the differences in delays for different I/O standards. Add the delay for the I/O standard that is used to the external timing parameters. See Figure 36 for more information. 72 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 36. AC Test Conditions for LVTTL, 2.5 V, 1.8 V, PCI & GTL+ I/O Standards VCCIO Rup Ouptut pin Cload Rdn Figure 37. AC Test Conditions for SSTL-3 Class I & II I/O Standards VCCIO R Output pin R Cload2 Cload1 Figure 38. AC Test Conditions for the LVDS I/O Standard Positive Output pin R Negative Output pin Cload Altera Corporation 73 APEX 20KC Programmable Logic Device Data Sheet Tables 44 through 67 show the fMAX and external timing parameters for EPC20K200C, EP20K400C, EP20K600C, and EP20K1000C devices. Table 44. EP20K200C fMAX LE Timing Microparameters Symbol -7 Speed Grade Min tSU tH tCO tLUT 0.01 0.10 0.27 0.65 -8 Speed Grade Min 0.01 0.10 0.30 0.78 -9 Speed Grade Min 0.01 0.10 0.32 0.92 Unit Max Max Max ns ns ns ns Table 45. EP20K200C fMAX ESB Timing Microparameters Symbol -7 Speed Grade Min tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPD tPTERMSU tPTERMCO 0.58 1.10 0.45 0.44 0.57 0.44 1.25 0.00 0.00 2.01 –0.20 0.02 1.09 2.10 2.50 1.48 0.72 1.29 -8 Speed Grade Min Max 1.51 2.49 3.46 3.44 0.50 0.50 0.63 0.50 1.43 0.03 0.00 2.27 –0.24 0.00 1.28 2.52 2.97 1.78 -9 Speed Grade Min Max 1.69 2.72 3.86 3.85 0.54 0.55 0.68 0.55 1.56 0.11 0.00 2.45 –0.28 –0.02 1.43 2.82 3.32 2.00 0.81 1.45 Unit Max 1.30 2.35 2.92 3.05 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 46. EP20K200C fMAX Routing Delays Symbol -7 Speed Grade Min tF1-4 tF5-20 tF20+ -8 Speed Grade Min Max 0.17 0.94 1.13 -9 Speed Grade Min Max 0.20 1.12 1.35 Unit Max 0.15 0.81 0.98 ns ns ns Table 47. EP20K200C Minimum Pulse Width Timing Parameters Symbol -7 Speed Grade Min tCH tCL tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.33 1.33 0.20 0.20 1.33 1.33 1.05 0.87 -8 Speed Grade Min 1.66 1.66 0.20 0.20 1.66 1.66 1.28 1.06 -9 Speed Grade Min 2.00 2.00 0.20 0.20 2.00 2.00 1.44 1.19 Unit Max Max Max ns ns ns ns ns ns ns ns Table 48. EP20K200C External Timing Parameters Symbol -7 Speed Grade Min tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.23 0.00 2.00 0.81 0.00 0.50 2.36 3.79 -8 Speed Grade Min 1.26 0.00 2.00 0.92 0.00 0.50 2.62 4.31 -9 Speed Grade Min 1.33 0.00 2.00 4.70 Unit Max Max Max ns ns ns ns ns ns Altera Corporation 75 APEX 20KC Programmable Logic Device Data Sheet Table 49. EP20K200C External Bidirectional Timing Parameters Symbol -7 Speed Grade Min tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 2.82 0.00 0.50 2.36 4.69 4.69 1.38 0.00 2.00 3.79 6.12 6.12 3.47 0.00 0.50 2.62 4.82 4.82 -8 Speed Grade Min 1.78 0.00 2.00 4.31 6.51 6.51 -9 Speed Grade Min 1.99 0.00 2.00 4.70 7.89 7.89 - Unit Max Max Max ns ns ns ns ns ns ns ns ns ns Table 50. EP20K400C fMAX LE Timing Parameters Symbol -7 Speed Grade Min tSU tH tCO tLUT 0.01 0.10 0.27 0.65 -8 Speed Grade Min 0.01 0.10 0.30 0.78 -9 Speed Grade Min 0.01 0.10 0.32 0.92 Unit Max Max Max ns ns ns ns 76 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 51. EP20K400C fMAX ESB Timing Parameters Symbol -7 Speed Grade Min tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPD tPTERMSU tPTERMCO 0.58 1.10 0.45 0.44 0.57 0.44 1.25 0.00 0.00 2.01 −0.20 0.02 1.09 2.10 2.50 1.48 0.72 1.29 -8 Speed Grade Min Max 1.51 2.49 3.46 3.44 0.50 0.50 0.63 0.50 1.43 0.03 0.00 2.27 −0.24 0.00 1.28 2.52 2.97 1.78 -9 Speed Grade Min Max 1.69 2.72 3.86 3.85 0.54 0.55 0.68 0.55 1.56 0.11 0.00 2.45 −0.28 −0.02 1.43 2.82 3.32 2.00 0.81 1.45 Unit Max 1.30 2.35 2.92 3.05 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 52. EP20K400C fMAX Routing Delays Symbol -7 Speed Grade Min tF1-4 tF5-20 tF20+ -8 Speed Grade Min Max 0.17 1.06 1.96 -9 Speed Grade Min Max 0.19 1.25 2.30 Unit Max 0.15 0.94 1.73 ns ns ns Altera Corporation 77 APEX 20KC Programmable Logic Device Data Sheet Table 53. EP20K400C Minimum Pulse Width Timing Parameters Symbol -7 Speed Grade Min tCH tCL tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.33 1.33 0.20 0.20 1.33 1.33 1.05 0.87 -8 Speed Grade Min 1.66 1.66 0.20 0.20 1.66 1.66 1.28 1.06 -9 Speed Grade Min 2.00 2.00 0.20 0.20 2.00 2.00 1.44 1.19 Unit Max Max Max ns ns ns ns ns ns ns ns Table 54. EP20K400C External Timing Parameters Symbol -7 Speed Grade Min tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.37 0.00 2.00 0.80 0.00 0.50 2.27 4.25 -8 Speed Grade Min 1.52 0.00 2.00 0.91 0.00 0.50 2.55 4.61 -9 Speed Grade Min 1.64 0.00 2.00 5.03 Unit Max Max Max ns ns ns ns ns ns 78 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 55. EP20K400C External Bidirectional Timing Parameters Symbol -7 Speed Grade Min tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 3.22 0.00 0.50 2.27 4.62 4.62 1.29 0.00 2.00 4.25 6.55 6.55 3.80 0.00 0.50 2.55 4.84 4.84 -8 Speed Grade Min 1.67 0.00 2.00 4.61 6.97 6.97 -9 Speed Grade Min 1.92 0.00 2.00 5.03 7.35 7.36 - Unit Max Max Max ns ns ns ns ns ns ns ns ns ns Table 56. EP20K600C fMAX LE Timing Parameters Symbol -7 Speed Grade Min tSU tH tCO tLUT 0.01 0.10 0.27 0.65 -8 Speed Grade Min 0.01 0.10 0.30 0.78 -9 Speed Grade Min 0.01 0.10 0.32 0.92 Unit Max Max Max ns ns ns ns Altera Corporation 79 APEX 20KC Programmable Logic Device Data Sheet Table 57. EP20K600C fMAX ESB Timing Parameters Symbol -7 Speed Grade Min tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPD tPTERMSU tPTERMCO 0.58 1.10 0.45 0.44 0.57 0.44 1.25 0.00 0.00 2.01 −0.20 0.02 1.09 2.10 2.50 1.48 0.72 1.29 -8 Speed Grade Min Max 1.51 2.49 3.46 3.44 0.50 0.50 0.63 0.50 1.43 0.03 0.00 2.27 −0.24 0.00 1.28 2.52 2.97 1.78 -9 Speed Grade Min Max 1.69 2.72 3.86 3.85 0.54 0.55 0.68 0.55 1.56 0.11 0.00 2.45 −0.28 −0.02 1.43 2.82 3.32 2.00 0.81 1.45 Unit Max 1.30 2.35 2.92 3.05 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 58. EP20K600C fMAX Routing Delays Symbol -7 Speed Grade Min tF1-4 tF5-20 tF20+ -8 Speed Grade Min Max 0.16 1.05 1.98 -9 Speed Grade Min Max 0.18 1.20 2.23 Unit Max 0.15 0.94 1.76 ns ns ns 80 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 59. EP20K600C Minimum Pulse Width Timing Parameters Symbol -7 Speed Grade Min tCH tCL tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.33 1.33 0.20 0.20 1.33 1.33 1.05 0.87 -8 Speed Grade Min 1.66 1.66 0.20 0.20 1.66 1.66 1.28 1.06 -9 Speed Grade Min 2.00 2.00 0.20 0.20 2.00 2.00 1.44 1.19 Unit Max Max Max ns ns ns ns ns ns ns ns Table 60. EP20K600C External Timing Parameters Symbol -7 Speed Grade Min tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.28 0.00 2.00 0.80 0.00 0.50 2.37 4.29 -8 Speed Grade Min 1.40 0.00 2.00 0.91 0.00 0.50 2.63 4.77 -9 Speed Grade Min 1.45 0.00 2.00 5.11 Unit Max Max Max ns ns ns ns ns ns Altera Corporation 81 APEX 20KC Programmable Logic Device Data Sheet Table 61. EP20K600C External Bidirectional Timing Parameters Symbol -7 Speed Grade Min tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 3.99 0.00 0.50 2.37 6.35 6.35 2.03 0.00 2.00 4.29 8.31 8.31 4.77 0.00 0.50 2.63 6.94 6.94 -8 Speed Grade Min 2.57 0.00 2.00 4.77 9.14 9.14 -9 Speed Grade Min 2.97 0.00 2.00 5.11 9.76 9.76 - Unit Max Max Max ns ns ns ns ns ns ns ns ns ns Table 62. EP20K1000C fMAX LE Timing Microparameters Symbol -7 Speed Grade Min tSU tH tCO tLUT 0.01 0.10 0.27 0.66 -8 Speed Grade Min 0.01 0.10 0.30 0.79 -9 Speed Grade Min 0.01 0.10 0.32 0.92 Unit Max Max Max ns ns ns ns 82 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 63. EP20K1000C fMAX ESB Timing Microparameters Symbol -7 Speed Grade Min tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPD tPTERMSU tPTERMCO 0.61 1.13 0.51 0.38 0.62 0.38 1.40 0.00 0.00 1.92 –0.20 0.00 1.12 2.11 2.56 1.49 0.69 1.32 -8 Speed Grade Min Max 1.57 2.50 3.46 3.43 0.50 0.51 0.62 0.51 1.47 0.07 0.00 2.19 –0.28 –0.03 1.30 2.53 2.96 1.79 -9 Speed Grade Min Max 1.65 2.73 3.86 3.83 0.52 0.57 0.66 0.57 1.53 0.18 0.00 2.35 –0.32 –0.05 1.46 2.84 3.30 2.02 0.77 1.48 Unit Max 1.48 2.36 2.93 3.08 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 64. EP20K1000C fMAX Routing Delays Symbol -7 Speed Grade Min tF1-4 tF5-20 tF20+ -8 Speed Grade Min Max 0.17 1.31 2.71 -9 Speed Grade Min Max 0.19 1.50 3.19 Unit Max 0.15 1.13 2.30 ns ns ns Altera Corporation 83 APEX 20KC Programmable Logic Device Data Sheet Table 65. EP20K1000C Minimum Pulse Width Timing Parameters Symbol -7 Speed Grade Min tCH tCL tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.33 1.33 0.20 0.20 1.33 1.33 1.04 0.87 -8 Speed Grade Min 1.66 1.66 0.20 0.20 1.66 1.66 1.26 1.05 -9 Speed Grade Min 2.00 2.00 0.20 0.20 2.00 2.00 1.41 1.18 Unit Max Max Max ns ns ns ns ns ns ns ns Table 66. EP20K1000C External Timing Parameters Symbol -7 Speed Grade Min tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.14 0.00 2.00 0.81 0.00 0.50 2.32 4.63 -8 Speed Grade Min 1.14 0.00 2.00 0.92 0.00 0.50 2.55 5.26 -9 Speed Grade Min 1.11 0.00 2.00 5.69 Unit Max Max Max ns ns ns ns ns ns 84 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Table 67. EP20K1000C External Bidirectional Timing Parameters Symbol -7 Speed Grade Min tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 4.17 0.00 0.50 2.32 6.67 6.67 1.86 0.00 2.00 4.63 8.98 8.98 5.27 0.00 0.50 2.55 7.18 7.18 -8 Speed Grade Min 2.54 0.00 2.00 5.26 9.89 9.89 -9 Speed Grade Min 3.15 0.00 2.00 5.69 10.67 10.67 - Unit Max Max Max ns ns ns ns ns ns ns ns ns ns Tables 68 and 69 show selectable I/O standard input and output delays for APEX 20KC devices. If you select an I/O standard input or output delay other than LVCMOS, add the delay for the selected speed grade to the LVCMOS value. Table 68. Selectable I/O Standard Input Delays Symbol -7 Speed Grade Min LVCMOS LVTTL 2.5 V 1.8 V PCI GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II LVDS CTT AGP -8 Speed Grade Min Max 0.00 0.00 0.00 0.11 0.04 0.25 –0.13 –0.13 –0.13 –0.13 –0.17 0.00 0.00 -9 Speed Grade Min Max 0.00 0.00 0.00 0.14 0.03 0.23 –0.13 –0.13 –0.13 –0.13 –0.16 0.00 0.00 Unit Min ns ns ns ns ns ns ns ns ns ns ns ns ns Max 0.00 0.00 0.00 0.04 0.00 –0.30 –0.19 –0.19 –0.19 –0.19 –0.19 0.00 0.00 Altera Corporation 85 APEX 20KC Programmable Logic Device Data Sheet Table 69. Selectable I/O Standard Output Delays Symbol -7 Speed Grade Min LVCMOS LVTTL 2.5 V 1.8 V PCI GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II LVDS CTT AGP -8 Speed Grad Min Max 0.00 0.00 0.00 1.41 –0.53 –0.29 –0.71 –0.71 –0.71 –0.71 –0.70 0.00 0.00 -9 Speed Grade Min Max 0.00 0.00 0.00 1.57 –0.56 –0.39 –0.75 –0.75 –0.75 –0.75 –0.73 0.00 0.00 Unit Min ns ns ns ns ns ns ns ns ns ns ns ns ns Max 0.00 0.00 0.00 1.18 –0.52 –0.18 –0.67 –0.67 –0.67 –0.67 –0.69 0.00 0.00 Power Consumption Configuration & Operation To estimate device power consumption, use the interactive power estimator on the Altera web site at http://www.altera.com. The APEX 20KC architecture supports several configuration schemes. This section summarizes the device operating modes and available device configuration schemes. Operating Modes The APEX architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode; normal device operation is called user mode. Before and during device configuration, all I/O pins are pulled to VCCIO by a built-in weak pull-up resistor. 86 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet SRAM configuration elements allow APEX 20KC devices to be reconfigured in-circuit by loading new configuration data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming user-mode operation. In-field upgrades can be performed by distributing new configuration files. Configuration Schemes The configuration data for an APEX 20KC device can be loaded with one of five configuration schemes (see Table 70), chosen on the basis of the target application. An EPC16, EPC2, or EPC1 configuration device, intelligent controller, or the JTAG port can be used to control the configuration of an APEX 20KC device. When a configuration device is used, the system can configure automatically at system power-up. Multiple APEX 20KC devices can be configured in any of five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Table 70. Data Sources for Configuration Configuration Scheme Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Passive parallel synchronous (PPS) JTAG Data Source EPC16, EPC8, EPC4, EPC2, or EPC1 configuration device MasterBlaster or ByteBlasterMV download cable or serial data source Parallel data source Parallel data source MasterBlaster or ByteBlasterMV download cable or a microprocessor with a Jam Standard Test and Programming Language (STAPL) or JBC File f Device PinOuts Ordering Information For more information on configuration, see Application Note 116 (Configuring SRAM-Based LUT Devices). See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Figure 39 describes the ordering codes for Stratix devices. For more information on a specific package, refer to the Altera Device Package Information Data Sheet. Altera Corporation 87 APEX 20KC Programmable Logic Device Data Sheet Figure 39. APEX 20KC Device Packaging Ordering Information EP20K Family Signature EP20K: APEX 20K 1000C F 1020 C 7 ES Optional Suffix Indicates specific device options or shipment method. ES: Engineering sample Device Type 200C 400C 600C 1000C Package Type Q: Plastic quad flat package (PQFP) B: Ball-grid array (BGA) F: FineLine BGA Speed Grade 7, 8, or 9, with 7 being the fastest Operating Temperature C: Commercial temperature (tJ = 0˚ C to 85˚ C) I: Industrial temperature (tJ = -40˚ C to 100˚ C) Pin Count Number of pins for a particular package Revision History The information contained in the APEX 20KC Programmable Logic Device Data Sheet version 2.2 supersedes information published in previous versions. Version 2.2 The following changes were made to the APEX 20KC Programmable Logic Device Data Sheet version 2.2: ■ ■ Updated Tables 1. Updated notes in Tables 20. Version 2.1 The following changes were made to the APEX 20KC Programmable Logic Device Data Sheet version 2.1: ■ ■ ■ ■ ■ ■ ■ ■ ■ Removed figure on AC Test Conditions. Updated conditions in Tables 40 and 41. Added Tables 42 and 43. Updated VOD in Table 27. Added Figures 36 through 38. Updated Tables 44 through 49. Updated Tables 62 through 67. Removed notes in Tables 44 through 67. Various textual changes throughout the document. 88 Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Altera Corporation 89 APEX 20KC Programmable Logic Device Data Sheet ® 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com Copyright © 2002 Altera Corporation. All rights reserved. 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