Section I. Arria GX Device Data Sheet
This section provides designers with the data sheet specifications for Arria® GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Arria GX devices. This section includes the following chapters:
■ ■ ■ ■ ■
Chapter 1, Arria GX Device Family Overview Chapter 2, Arria GX Architecture Chapter 3, Configuration and Testing Chapter 4, DC and Switching Characteristics Chapter 5, Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
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Arria GX Device Handbook, Volume 1
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Section I: Arria GX Device Data Sheet
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
1. Arria GX Device Family Overview
AGX51001-2.0
Introduction
The Arria® GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria GX devices include 4 to 12 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with the ability to develop proprietary, serial-based IP using its Basic mode. The transceivers build upon the success of the Stratix ® II GX family. The Arria GX FPGA technology offers a 1.2-V logic array with the right level of performance and dependability needed to support these mainstream protocols.
Features
The key features of Arria GX devices include:
■
Transceiver block features
■ ■
High-speed serial transceiver channels with CDR support up to 3.125 Gbps. Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels Support for the following CDR-based bus standards—PCI Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode) Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial Digital Interface (SDI), and Serial RapidIO 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array Channel aligner compliant with XAUI
■
■
■
■
■
■
■
■
■
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■
Main device features:
■
TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 380 MHz Up to 16 global clock networks with up to 32 regional clock networks per device High-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters Up to four enhanced phase-locked loops (PLLs) per device provide spread spectrum, programmable bandwidth, clock switch-over, and advanced multiplication and phase shifting Support for numerous single-ended and differential I/O standards High-speed source-synchronous differential I/O support on up to 47 channels Support for source-synchronous bus standards, including SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1 Support for high-speed external memory including DDR and DDR2 SDRAM, and SDR SDRAM Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM ) Support for remote configuration updates
■
■
■
■ ■ ■
■
■
■
Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with flip chip packages.
Table 1–1. Arria GX Device Features (Part 1 of 2) EP1AGX20C Feature C Package 484-pin, 780-pin (Flip chip) 8,632 21,580 C 484-pin (Flip chip) D 780-pin (Flip chip) C 484-pin (Flip chip) D 780-pin, 1152-pin (Flip chip) 13,408 33,520 20,064 50,160 24,040 60,100 36,088 90,220 C 484-pin D 780-pin E E 1152-pin (Flip chip) 1152-pin (Flip chip) (Flip chip) (Flip chip) EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E
ALMs Equivalent logic elements (LEs) Transceiver channels Transceiver data rate Sourcesynchronous receive channels
4 600 Mbps to 3.125 Gbps 31
4
8
4
8
4
8
12
12 600 Mbps to 3.125 Gbps 47
600 Mbps to 3.125 Gbps
600 Mbps to 3.125 Gbps
600 Mbps to 3.125 Gbps
31
31
31
31, 42
31
31
42
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Table 1–1. Arria GX Device Features (Part 2 of 2) EP1AGX20C Feature C Sourcesynchronous transmit channels M512 RAM blocks (32 × 18 bits) M4K RAM blocks (128 × 36 bits) M-RAM blocks (4096 × 144 bits) Total RAM bits Embedded multipliers (18 × 18) DSP blocks PLLs Maximum user I/O pins C D C D C D E E EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E
29
29
29
29
29, 42
29
29
42
45
166
197
313
326
478
118
140
242
252
400
1
1
2
2
4
1,229,184
1,348,416
2,475,072
2,528,640
4,477,824
40 10 4 230, 341 230
56 14 4 341 4 229
104 26 4, 8 350, 514 229 4
128 32 8 350 514
176 44 8 538
Arria GX devices are available in space-saving FBGA packages (refer to Table 1–2). All Arria GX devices support vertical migration within the same package. With vertical migration support, designers can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, the designer must cross-reference the available I/O pins with the device pin-outs for all planned densities of a given package type to identify which I/O pins are migratable.
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2) Source-Synchronous Channels Device Transceiver Channels 4 4 4 4 8 8 Receive 31 31 31 31 31 31, 42 Transmit 29 29 29 29 29 29, 42 Maximum User I/O Pin Count 484-Pin FBGA (23 mm) 230 230 229 229 — — 780-Pin FBGA (29 mm) 341 — — — 341 350 1152-Pin FBGA (35 mm) — — — — — 514
EP1AGX20C EP1AGX35C EP1AGX50C EP1AGX60C EP1AGX35D EP1AGX50D
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Chapter 1: Arria GX Device Family Overview Document Revision History
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 2 of 2) Source-Synchronous Channels Device Transceiver Channels 8 12 12 Receive 31 42 47 Transmit 29 42 45 Maximum User I/O Pin Count 484-Pin FBGA (23 mm) — — — 780-Pin FBGA (29 mm) 350 — — 1152-Pin FBGA (35 mm) — 514 538
EP1AGX60D EP1AGX60E EP1AGX90E
Table 1–3 lists the Arria GX device package sizes.
Table 1–3. Arria GX FBGA Package Sizes Dimension Pitch (mm) Area (mm2 ) Length × width (mm × mm) 484 Pins 1.00 529 23 × 23 780 Pins 1.00 841 29 × 29 1152 Pins 1.00 1225 35 × 35
Document Revision History
Table 1–4 lists the revision history for this chapter.
Table 1–4. Document Revision History Date and Document Version December 2009, v2.0 May 2008, v1.2 June 2007, v1.1 May 2007, v1.0
■ ■
Changes Made Document template update. Minor text edits.
Summary of Changes — — — —
Included support for SDI, SerialLite II, and XAUI. Included GIGE information. Initial Release
Arria GX Device Handbook, Volume 1
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2. Arria GX Architecture
AGX51002-2.0
Transceivers
Arria® G X devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix ® II GX device family. Arria GX transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks located on the right side of the device. You can configure the transceiver blocks to support the following serial connectivity protocols (functional modes):
■ ■ ■ ■ ■ ■
PCI Express (PIPE) Gigabit Ethernet (GIGE) XAUI Basic (600 Mbps to 3.125 Gbps) SDI (HD, 3G) Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)
Transceivers within each block are independent and have their own set of dividers. Therefore, each transceiver can operate at different frequencies. Each block can select from two reference clocks to provide two clock domains that each transceiver can select from. Table 2–1 lists the number of transceiver channels for each member of the Arria GX family.
Table 2–1. Arria GX Transceiver Channels Device EP1AGX20C EP1AGX35C EP1AGX35D EP1AGX50C EP1AGX50D EP1AGX60C EP1AGX60D EP1AGX60E EP1AGX90E Number of Transceiver Channels 4 4 8 4 8 4 8 12 12
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Figure 2–1 shows a high-level diagram of the transceiver block architecture divided into four channels.
Figure 2–1. Transceiver Block
Transceiver Block RX1 Channel 1 TX1 RX0 Arria GX Logic Array Channel 0 TX0 Supporting Blocks (PLLs, State Machines, Programming) REFCLK_1 REFCLK_0 RX2 Channel 2 TX2 RX3 Channel 3 TX3
Each transceiver block has:
■
Four transceiver channels with dedicated physical coding sublayer (PCS) and physical media attachment (PMA) circuitry One transmitter PLL that takes in a reference clock and generates high-speed serial clock depending on the functional mode Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from the received serial data stream State machines and other logic to implement special features required to support each protocol
■
■
■
Figure 2–2 shows functional blocks that make up a transceiver channel.
Figure 2–2. Arria GX Transceiver Channel Block Diagram
PMA Analog Section n Deserializer (1) Clock Recovery Unit PCS Digital Section FPGA Fabric
Word Aligner Rate Matcher XAUI Lane Deskew 8B/10B Decoder Phase Compensation FIFO Buffer m (2)
Byte Deserializer
Reference Clock
Receiver PLL
Reference Clock
Transmitter PLL
n Serializer (1) 8B/10B Encoder Byte Serializer Phase Compensation FIFO Buffer m (2)
Notes to Figure 2–2:
(1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA. n = 8 or 10. (2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, or 20.
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Each transceiver channel is full-duplex and consists of a transmitter channel and a receiver channel. The transmitter channel contains the following sub-blocks:
■ ■ ■ ■ ■
Transmitter phase compensation first-in first-out (FIFO) buffer Byte serializer (optional) 8B/10B encoder (optional) Serializer (parallel-to-serial converter) Transmitter differential output buffer
The receiver channel contains the following:
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
Receiver differential input buffer Receiver lock detector and run length checker CRU Deserializer Pattern detector Word aligner Lane deskew Rate matcher (optional) 8B/10B decoder (optional) Byte deserializer (optional) Receiver phase compensation FIFO buffer
You can configure the transceiver channels to the desired functional modes using the ALT2GXB MegaCore instance in the Quartus® II MegaWizard ™ Plug-in Manager for the Arria GX device family. Depending on the selected functional mode, the Quartus II software automatically configures the transceiver channels to employ a subset of the sub-blocks listed above.
Transmitter Path
This section describes the data path through the Arria GX transmitter. The sub-blocks are described in order from the PLD-transmitter parallel interface to the serial transmitter buffer.
Clock Multiplier Unit
Each transceiver block has a clock multiplier unit (CMU) that takes in a reference clock and synthesizes two clocks: a high-speed serial clock to serialize the data and a low-speed parallel clock to clock the transmitter digital logic (PCS). The CMU is further divided into three sub-blocks:
■ ■ ■
One transmitter PLL One central clock divider block Four local clock divider blocks (one per channel)
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Figure 2–3 shows the block diagram of the clock multiplier unit.
Figure 2–3. Clock Multiplier Unit
CMU Block
Transmitter Channels [3:2] LocalClock TX Clock Divider Block Gen Block
Transmitter High-Speed Serial and Low-Speed Parallel Clocks
Reference Clock from REFCLKs, Global Clock (1), Inter-Transceiver Lines
Transmitter PLL
Central Clock Divider Block
Transmitter High-Speed Serial and Low-Speed Parallel Clocks
Local Clock TX Clock Divider Block Transmitter Channels [1:0]
Gen Block
The transmitter PLL multiplies the input reference clock to generate the high-speed serial clock required to support the intended protocol. It implements a half-rate voltage controlled oscillator (VCO) that generates a clock at half the frequency of the serial data rate for which it is configured. Figure 2–4 shows the block diagram of the transmitter PLL.
Figure 2–4. Transmitter PLL
Transmitter PLL
To Inter-Transceiver Lines
/M
(1)
Dedicated REFCLK0 Dedicated REFCLK1
/2 /2
Phase Frequency INCLK Detector
up down
Charge Pump + Loop Filter Voltage Controlled Oscillator
/L(1)
High Speed Serial Clock
Inter-Transceiver Lines[2:0] Global Clock (2)
Notes to Figure 2–4:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers (clock multiplication factors). (2) The global clock line must be driven from an input pin only.
The reference clock input to the transmitter PLL can be derived from:
■
One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1) of the associated transceiver block PLD global clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL)
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■
Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
1
Altera® recommends using the dedicated reference clock input pins (REFCLK0 or REFCLK1) to provide reference clock for the transmitter PLL. Table 2–2 lists the adjustable parameters in the transmitter PLL.
Table 2–2. Transmitter PLL Specifications Parameter Input reference frequency range Data rate support Bandwidth Specifications 50 MHz to 622.08 MHz 600 Mbps to 3.125 Gbps Low, medium, or high
The transmitter PLL output feeds the central clock divider block and the local clock divider blocks. These clock divider blocks divide the high-speed serial clock to generate the low-speed parallel clock for the transceiver PCS logic and PLD-transceiver interface clock.
Transmitter Phase Compensation FIFO Buffer
A transmitter phase compensation FIFO is located at each transmitter channel’s logic array interface. It compensates for the phase difference between the transmitter PCS clock and the local PLD clock. The transmitter phase compensation FIFO is used in all supported functional modes. The transmitter phase compensation FIFO buffer is eight words deep in PCI Express (PIPE) mode and four words deep in all other modes. f For more information about architecture and clocking, refer to the Arria GX Transceiver Architecture chapter.
Byte Serializer
The byte serializer takes in two-byte wide data from the transmitter phase compensation FIFO buffer and serializes it into a one-byte wide data at twice the speed. The transmit data path after the byte serializer is 8 or 10 bits. This allows clocking the PLD-transceiver interface at half the speed when compared with the transmitter PCS logic. The byte serializer is bypassed in GIGE mode. After serialization, the byte serializer transmits the least significant byte (LSByte) first and the most significant byte (MSByte) last.
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Figure 2–5 shows byte serializer input and output. datain[15:0] is the input to the byte serializer from the transmitter phase compensation FIFO; dataout[7:0] is the output of the byte serializer.
Figure 2–5. Byte Serializer Operation (Note 1)
D1 D2 D3
datain[15:0] dataout[7:0]
Note to Figure 2–5:
{8'h00,8'h01}
xxxxxxxxxx xxxxxxxxxx
{8'h02,8'h03}
D1LSByte D1MSByte
xxxx
D2LSByte D2MSByte
8'h01
8'h00
8'h03
8'h02
(1) datain m ay be 16 or 20 bits. dataout may be 8 or 10 bits.
8B/10B Encoder
The 8B/10B encoder block is used in all supported functional modes. The 8B/10B encoder block takes in 8-bit data from the byte serializer or the transmitter phase compensation FIFO buffer. It generates a 10-bit code group with proper running disparity from the 8-bit character and a 1-bit control identifier (tx_ctrlenable). When tx_ctrlenable is low, the 8-bit character is encoded as data code group (Dx.y). When tx_ctrlenable is high, the 8-bit character is encoded as a control code group (Kx.y). The 10-bit code group is fed to the serializer. The 8B/10B encoder conforms to the IEEE 802.3 1998 edition standard. f For additional information regarding 8B/10B encoding rules, refer to the Specifications and Additional Information chapter. Figure 2–6 shows the 8B/10B conversion format.
Figure 2–6. 8B/10B Encoder
7 H 6 G 5 F 4 E 3 D 2 C 1 B 0 A Ctrl
8B-10B Conversion
j 9
h 8
g 7
f 6
i 5
e 4
d 3
c 2
b 1
a 0
MSB
LSB
During reset (tx_digitalreset), the running disparity and data registers are cleared and the 8B/10B encoder continously outputs a K28.5 pattern from the RD-column. After out of reset, the 8B/10B encoder starts with a negative disparity (RD-) and transmits three K28.5 code groups for synchronizing before it starts encoding the input data or control character.
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Transmit State Machine
The transmit state machine operates in either PCI Express (PIPE) mode, XAUI mode, or GIGE mode, depending on the protocol used. GIGE Mode In GIGE mode, the transmit state machine converts all idle ordered sets (/K28.5/, /Dx.y/) to either /I1/ or /I2/ ordered sets. The /I1/ set consists of a negative-ending disparity /K28.5/ (denoted by /K28.5/-), followed by a neutral /D5.6/. The /I2/ set consists of a positive-ending disparity /K28.5/ (denoted by /K28.5/+) and a negative-ending disparity /D16.2/ (denoted by /D16.2/-). The transmit state machines do not convert any of the ordered sets to match /C1/ or /C2/, which are the configuration ordered sets. (/C1/ and /C2/ are defined by [/K28.5/, /D21.5/] and [/K28.5/, /D2.2/], respectively). Both the /I1/ and /I2/ ordered sets guarantee a negative-ending disparity after each ordered set. XAUI Mode The transmit state machine translates the XAUI XGMII code group to the XAUI PCS code group. Table 2–3 lists the code conversion.
Table 2–3. On-Chip Termination Support by I/O Banks XGMII TXC 0 1 1 1 1 1 1 1 1 00 through FF 07 07 9C FB FD FE Refer to IEEE 802.3 reserved code groups Other value XGMII TXD Dxx.y K28.0 or K28.3 or K28.5 K28.5 K28.4 K27.7 K29.7 K30.7 Refer to IEEE 802.3 reserved code groups K30.7 PCS Code-Group Description Normal data Idle in ||I|| Idle in ||T|| Sequence Start Terminate Error Reserved code groups Invalid XGMII character
The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are automatically randomized based on a PRBS7 pattern with an ×7 + ×6 + 1 polynomial. The /K28.3/ (/A/) code group is automatically generated between 16 and 31 idle code groups. The idle randomization on the /A/, /K/, and /R/ code groups is automatically done by the transmit state machine.
Serializer (Parallel-to-Serial Converter)
The serializer block clocks in 8- or 10-bit encoded data from the 8B/10B encoder using the low-speed parallel clock and clocks out serial data using the high-speed serial clock from the central or local clock divider blocks. The serializer feeds the data LSB to MSB to the transmitter output buffer.
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Figure 2–7 shows the serializer block diagram.
Figure 2–7. Serializer
D9 D8 D7 D6 10 D5
From 8B/10B Encoder
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
To Transmitter Output Buffer
D4 D3 D2 D1 D0
Low-speed parallel clock CMU Central / Local Clock High-speed serial clock Divider
Transmitter Buffer
The Arria GX transceiver buffers support the 1.2- and 1.5-V PCML I/O standard at rates up to 3.125 Gbps. The common mode voltage (VCM ) of the output driver may be set to 600 or 700 mV. f For more information about the Arria GX transceiver buffers, refer to the Arria GX Transceiver Architecture chapter. The output buffer, as shown in Figure 2–8, is directly driven by the high-speed data serializer and consists of a programmable output driver, a programmable pre-emphasis circuit, and OCT circuitry.
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Figure 2–8. Output Buffer
Serializer
Output Buffer
Programmable Pre-Emphasis Programmable Output Driver
Output Pins
Programmable Output Driver The programmable output driver can be set to drive out differentially from 400 to 1200 mV. The differential output voltage (VOD ) can be statically set by using the ALTGXB megafunction. You can configure the output driver with 100- OCT or external OCT. Differential signaling conventions are shown in Figure 2–9. The differential amplitude represents the value of the voltage between the true and complement signals. Peak-to-peak differential voltage is defined as 2 (VHIGH – VLOW ) = 2 single-ended voltage swing. The common mode voltage is the average of V HIGH and VLOW.
Figure 2–9. Differential Signaling
Single-Ended Waveform
True
Vhigh +VOD -
Complement
Vlow Differential Waveform +400 +VOD 0-V Differential VOD (Differential) = Vhigh − Vlow 2 * VOD -VOD −400
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Programmable Pre-Emphasis The programmable pre-emphasis module controls the output driver to boost high frequency components and compensate for losses in the transmission medium, as shown in Figure 2–10. Pre-emphasis is set statically using the ALTGXB megafunction.
Figure 2–10. Pre-Emphasis Signaling
VMAX
VMIN
Pre-Emphasis % = (
VMAX VMIN
− 1) × 100
Pre-emphasis percentage is defined as (VMAX /VMIN – 1) × 100, where VM AX is the differential emphasized voltage (peak-to-peak) and VMIN is the differential steady-state voltage (peak-to-peak). PCI Express (PIPE) Receiver Detect The Arria GX transmitter buffer has a built-in receiver detection circuit for use in PCI Express (PIPE) mode. This circuit provides the ability to detect if there is a receiver downstream by sending out a pulse on the channel and monitoring the reflection. This mode requires a tri-stated transmitter buffer (in electrical idle mode). PCI Express (PIPE) Electric Idles (or Individual Transmitter Tri-State) The Arria GX transmitter buffer supports PCI Express (PIPE) electrical idles. This feature is only active in PCI Express (PIPE) mode. The tx_forceelecidle port puts the transmitter buffer in electrical idle mode. This port is available in all PCI Express (PIPE) power-down modes and has specific usage in each mode.
Receiver Path
This section describes the data path through the Arria GX receiver. The sub-blocks are described in order from the receiver buffer to the PLD-receiver parallel interface.
Receiver Buffer
The Arria GX receiver input buffer supports the 1.2-V and 1.5-V PCML I/O standards at rates up to 3.125 Gbps. The common mode voltage of the receiver input buffer is programmable between 0.85 V and 1.2 V. You must select the 0.85 V common mode voltage for AC- and DC-coupled PCML links and 1.2 V common mode voltage for DC-coupled LVDS links.
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The receiver has 100- on-chip differential termination (R D OCT) for different protocols, as shown in Figure 2–11. You can disable the receiver’s internal termination if external terminations and biasing are provided. The receiver and transmitter differential termination method can be set independently of each other.
Figure 2–11. Receiver Input Buffer
100-Ω Termination Input Pins Programmable Equalizer
Differential Input Buffer
If a design uses external termination, the receiver must be externally terminated and biased to 0.85 V or 1.2 V. Figure 2–12 shows an example of an external termination and biasing circuit.
Figure 2–12. External Termination and Biasing Circuit
Receiver External Termination and Biasing 50-W Termination Resistance VDD
R1 C1
Arria GX Device
Receiver
R1/R2 = 1K VDD ´ {R2/(R1 + R 2)} = 0.85/1.2 V RXIP R2 RXIN
Receiver External Termination and Biasing Transmission Line
Programmable Equalizer
The Arria GX receivers provide a programmable receiver equalization feature to compensate for the effects of channel attenuation for high-speed signaling. PCB traces carrying these high-speed signals have low-pass filter characteristics. Impedance mismatch boundaries can also cause signal degradation. Equalization in the receiver diminishes the lossy attenuation effects of the PCB at high frequencies.
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The receiver equalization circuit is comprised of a programmable amplifier. Each stage is a peaking equalizer with a different center frequency and programmable gain. This allows varying amounts of gain to be applied, depending on the overall frequency response of the channel loss. Channel loss is defined as the summation of all losses through the PCB traces, vias, connectors, and cables present in the physical link. The Quartus II software allows five equalization settings for Arria GX devices.
Receiver PLL and Clock Recovery Unit (CRU)
Each transceiver block has four receiver PLLs and CRU units, each of which is dedicated to a receiver channel. The receiver PLL is fed by an input reference clock. The receiver PLL, in conjunction with the CRU, generates two clocks: a high-speed serial recovered clock that clocks the deserializer and a low-speed parallel recovered clock that clocks the receiver's digital logic. Figure 2–13 shows a block diagram of the receiver PLL and CRU circuits.
Figure 2–13. Receiver PLL and Clock Recovery Unit
/M
Dedicated REFCLK0
rx_pll_locked
/2
Dedicated /2 REFCLK1 Inter-Transceiver Lines [2:0] Global Clock (2)
PFD rx_cruclk
up dn up dn
CP+ LF
VCO
/L
rx_locktorefclk rx_locktodata rx_datain
rx_freqlocked
Clock Recov ery Unit (CRU) Control
High-speed serial recovered clk Low-speed parallel recovered clk
Notes to Figure 2–13:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your selections, the ALTGXB MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers. (2) The global clock line must be driven from an input pin only.
The reference clock input to the receiver PLL can be derived from:
■
One of the two available dedicated reference clock input pins (REFCLK0 or REFCLK1) of the associated transceiver block PLD global clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL) Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
■
■
All the parameters listed are programmable in the Quartus II software. The receiver PLL has the following features:
■ ■ ■ ■
Operates from 600 Mbps to 3.125 Gbps. Uses a reference clock between 50 MHz and 622.08 MHz. Programmable bandwidth settings: low, medium, and high. Programmable rx_locktorefclk (forces the receiver PLL to lock to reference clock) and rx_locktodata (forces the receiver PLL to lock to data).
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■ ■
The voltage-controlled oscillator (VCO) operates at half rate. Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and 25. Not all settings are supported for any particular frequency. Two lock indication signals are provided. They are found in PFD mode (lock-to-reference clock), and PD (lock-to-data).
■
The CRU controls whether the receiver PLL locks to the input reference clock (lock-to-reference mode) or the incoming serial data (lock-to data mode). You can set the CRU to switch between lock-to-data and lock-to-reference modes automatically or manually. In automatic lock mode, the phase detector and dedicated parts per million (PPM) detector within each receiver channel control the switch between lock-to-data and lock-to-reference modes based on some pre-set conditions. In manual lock mode, you can control the switch manually using the rx_locktorefclk and rx_locktodata signals. f For more information, refer to the “Clock Recovery Unit” section in the Arria GX Transceiver Protocol Support and Additional Features chapter. Table 2–4 lists the behavior of the CRU block with respect to the rx_locktorefclk and rx_locktodata signals.
Table 2–4. CRU Manual Lock Signals rx_locktorefclk 1 x 0 rx_locktodata 0 1 0 Lock-to-data Automatic CRU Mode Lock-to-reference clock
If the rx_locktorefclk and rx_locktodata ports are not used, the default setting is automatic lock mode.
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes into 8- or 10-bit parallel data using the low-speed parallel recovered clock. The serial data is assumed to be received with LSB first, followed by MSB. It feeds the deserialized 8- or 10-bit data to the word aligner, as shown in Figure 2–14.
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Figure 2–14. Deserializer ( Note 1)
Receiv ed Data
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D9 D8 D7 D6
10
D5 D4 D3 D2 D1 D0
To Word Aligner
Clock High-speed serial recovered clock Recov ery Unit Low -speed parallel recovered clock
Note to Figure 2–14:
(1) This is a 10-bit deserializer. The deserializer can also convert 8 bits of data.
Word Aligner
The deserializer block creates 8- or 10-bit parallel data. The deserializer ignores protocol symbol boundaries when converting this data. Therefore, the boundaries of the transferred words are arbitrary. The word aligner aligns the incoming data based on specific byte or word boundaries. The word alignment module is clocked by the local receiver recovered clock during normal operation. All the data and programmed patterns are defined as “big-endian” (most significant word followed by least significant word). Most-significant-bit-first protocols should reverse the bit order of word align patterns programmed. This module detects word boundaries for 8B/10B-based protocols. This module is also used to align to specific programmable patterns in PRBS7/23 test mode. Pattern Detection The programmable pattern detection logic can be programmed to align word boundaries using a single 7- or 10-bit pattern. The pattern detector can either do an exact match, or match the exact pattern and the complement of a given pattern. Once the programmed pattern is found, the data stream is aligned to have the pattern on the LSB portion of the data output bus. XAUI, GIGE, PCI Express (PIPE), and Serial RapidIO standards have embedded state machines for symbol boundary synchronization. These standards use K28.5 as their 10-bit programmed comma pattern. Each of these standards uses different algorithms before signaling symbol boundary acquisition to the FPGA. Pattern detection logic searches from the LSB to the MSB. If multiple patterns are found within the search window, the pattern in the lower portion of the data stream (corresponding to the pattern received earlier) is aligned and the rest of the matching patterns are ignored.
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Once a pattern is detected and the data bus is aligned, the word boundary is locked. The two detection status signals (rx_syncstatus and rx_patterndetect) indicate that an alignment is complete. Figure 2–15 is a block diagram of the word aligner.
Figure 2–15. Word Aligner
datain bitslip
Word Aligner
dataout syncstatus patterndetect
enapatternalign clock
Control and Status Signals The rx_enapatternalign signal is the FPGA control signal that enables word alignment in non-automatic modes. The rx_enapatternalign signal is not used in automatic modes (PCI Express [PIPE], XAUI, GIGE, and Serial RapidIO). In manual alignment mode, after the rx_enapatternalign signal is activated, the rx_syncstatus signal goes high for one parallel clock cycle to indicate that the alignment pattern has been detected and the word boundary has been locked. If rx_enapatternalign is deactivated, the rx_syncstatus signal acts as a re-synchronization signal to signify that the alignment pattern has been detected but not locked on a different word boundary. When using the synchronization state machine, the rx_syncstatus signal indicates the link status. If the rx_syncstatus signal is high, link synchronization is achieved. If the rx_syncstatus signal is low, link synchronization has not yet been achieved, or there were enough code group errors to lose synchronization. f For more information about manual alignment modes, refer to the Arria GX Device Handbook. The rx_patterndetect signal pulses high during a new alignment and whenever the alignment pattern occurs on the current word boundary. Programmable Run Length Violation The word aligner supports a programmable run length violation counter. Whenever the number of the continuous ‘0’ (or ‘1’) exceeds a user programmable value, the rx_rlv signal goes high for a minimum pulse width of two recovered clock cycles. The maximum run values supported are 128 UI for 8-bit serialization or 160 UI for 10-bit serialization. Running Disparity Check The running disparity error rx_disperr and running disparity value rx_runningdisp are sent along with aligned data from the 8B/10B decoder to the FPGA. You can ignore or act on the reported running disparity value and running disparity error signals.
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Bit-Slip Mode The word aligner can operate in either pattern detection mode or in bit-slip mode. The bit-slip mode provides the option to manually shift the word boundary through the FPGA. This feature is useful for:
■ ■ ■
Longer synchronization patterns than the pattern detector can accommodate Scrambled data stream Input stream consisting of over-sampled data
The word aligner outputs a word boundary as it is received from the analog receiver after reset. You can examine the word and search its boundary in the FPGA. To do so, assert the rx_bitslip signal. The rx_bitslip signal should be toggled and held constant for at least two FPGA clock cycles. For every rising edge of the rx_bitslip signal, the current word boundary is slipped by one bit. Every time a bit is slipped, the bit received earliest is lost. If bit slipping shifts a complete round of bus width, the word boundary is back to the original boundary. The rx_syncstatus signal is not available in bit-slipping mode.
Channel Aligner
The channel aligner is available only in XAUI mode and aligns the signals of all four channels within a transceiver. The channel aligner follows the IEEE 802.3ae, clause 48 specification for channel bonding. The channel aligner is a 16-word FIFO buffer with a state machine controlling the channel bonding process. The state machine looks for an /A/ (/K28.3/) in each channel and aligns all the /A/ code groups in the transceiver. When four columns of /A/ (denoted by //A//) are detected, the rx_channelaligned signal goes high, signifying that all the channels in the transceiver have been aligned. The reception of four consecutive misaligned /A/ code groups restarts the channel alignment sequence and sends the rx_channelaligned signal low.
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Figure 2–16 shows misaligned channels before the channel aligner and the aligned channels after the channel aligner.
Figure 2–16. Before and After the Channel Aligner
Lane 3 K Lane 2 K R A K R R K K R K R
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K
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Rate Matcher
In asynchronous systems, the upstream transmitter and local receiver can be clocked with independent reference clock sources. Frequency differences in the order of a few hundred PPM can potentially corrupt the data at the receiver. The rate matcher compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing skip characters from the inter packet gap (IPG) or idle streams. It inserts a skip character if the local receiver is running a faster clock than the upstream transmitter. It deletes a skip character if the local receiver is running a slower clock than the upstream transmitter. The Quartus II software automatically configures the appropriate skip character as specified in the IEEE 802.3 for GIGE mode and PCI-Express Base Specification for PCI Express (PIPE) mode. The rate matcher is bypassed in Serial RapidIO and must be implemented in the PLD logic array or external circuits depending on your system design. Table 2–5 lists the maximum frequency difference that the rate matcher can tolerate in XAUI, PCI Express (PIPE), GIGE, and Basic functional modes.
Table 2–5. Rate Matcher PPM Tolerance Function Mode XAUI PCI Express (PIPE) GIGE Basic PPM ± 100 ± 300 ± 100 ± 300
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XAUI Mode In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae specification for clock rate compensation. The rate matcher performs clock compensation on columns of /R/ (/K28.0/), denoted by //R//. An //R// is added or deleted automatically based on the number of words in the FIFO buffer. PCI Express (PIPE) Mode Rate Matcher In PCI Express (PIPE) mode, the rate matcher can compensate up to ± 300 PPM (600 PPM total) frequency difference between the upstream transmitter and the receiver. The rate matcher logic looks for skip ordered sets (SOS), which contains a /K28.5/ comma followed by three /K28.0/ skip characters. The rate matcher logic deletes or inserts /K28.0/ skip characters as necessary from/to the rate matcher FIFO. The rate matcher in PCI Express (PIPE) mode has a FIFO buffer overflow and underflow protection. In the event of a FIFO buffer overflow, the rate matcher deletes any data after detecting the overflow condition to prevent FIFO pointer corruption until the rate matcher is not full. In an underflow condition, the rate matcher inserts 9'h1FE (/K30.7/) until the FIFO buffer is not empty. These measures ensure that the FIFO buffer can gracefully exit the overflow and underflow condition without requiring a FIFO reset. The rate matcher FIFO overflow and underflow condition is indicated on the pipestatus port. You can bypass the rate matcher in PCI Express (PIPE) mode if you have a synchronous system where the upstream transmitter and local receiver derive their reference clocks from the same source. GIGE Mode Rate Matcher In GIGE mode, the rate matcher can compensate up to ± 100 PPM (200 PPM total) frequency difference between the upstream transmitter and the receiver. The rate matcher logic inserts or deletes /I2/ idle ordered sets to/from the rate matcher FIFO during the inter-frame or inter-packet gap (IFG or IPG). /I2/ is selected as the rate matching ordered set because it maintains the running disparity, unlike /I1/ that alters the running disparity. Because the /I2/ ordered-set contains two 10-bit code groups (/K28.5/, /D16.2/), 20 bits are inserted or deleted at a time for rate matching. 1 The rate matcher logic has the capability to insert or delete /C1/ or /C2/ configuration ordered sets when ‘GIGE Enhanced’ mode is chosen as the sub-protocol in the MegaWizard Plug-In Manager. If the frequency PPM difference between the upstream transmitter and the local receiver is high, or if the packet size is too large, the rate matcher FIFO buffer can face an overflow or underflow situation. Basic Mode In basic mode, you can program the skip and control pattern for rate matching. There is no restriction on the deletion of a skip character in a cluster. The rate matcher deletes the skip characters as long as they are available. For insertion, the rate matcher inserts skip characters such that the number of skip characters at the output of rate matcher does not exceed five.
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8B/10B Decoder
The 8B/10B decoder is used in all supported functional modes. The 8B/10B decoder takes in 10-bit data from the rate matcher and decodes it into 8-bit data + 1-bit control identifier, thereby restoring the original transmitted data at the receiver. The 8B/10B decoder indicates whether the received 10-bit character is a data or control code through the rx_ctrldetect port. If the received 10-bit code group is a control character (Kx.y), the rx_ctrldetect signal is driven high and if it is a data character (Dx.y), the rx_ctrldetect signal is driven low. Figure 2–17 shows a 10-bit code group decoded to an 8-bit data and a 1-bit control indicator.
Figure 2–17. 10-Bit to 8-Bit Conversion
j 9 h 8 g 7 f 6 i 5 e 4 d 3 c 2 b 1 a 0
MSB Received Last 8B/10B Conversion
LSB Received First
ctrl
7 H
6 G
5 F
4 E
3 D
2 C
1 B
0 A
Parallel Data
If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups, the 8B/10B decoder block asserts an error flag on the rx_errdetect port. If the received 10-bit code is detected with incorrect running disparity, the 8B/10B decoder block asserts an error flag on the rx_disperr and rx_errdetect ports. The error flag signals (rx_errdetect and rx_disperr) have the same data path delay from the 8B/10B decoder to the PLD-transceiver interface as the bad code group.
Receiver State Machine
The receiver state machine operates in Basic, GIGE, PCI Express (PIPE), and XAUI modes. In GIGE mode, the receiver state machine replaces invalid code groups with K30.7. In XAUI mode, the receiver state machine translates the XAUI PCS code group to the XAUI XGMII code group.
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Byte Deserializer
Byte deserializer takes in one-byte wide data from the 8B/10B decoder and deserializes it into a two-byte wide data at half the speed. This allows clocking the PLD-receiver interface at half the speed as compared to the receiver PCS logic. The byte deserializer is bypassed in GIGE mode. The byte ordering at the receiver output might be different than what was transmitted. This is a non-deterministic swap, because it depends on PLL lock times and link delay. If required, you must implement byte ordering logic in the PLD to correct this situation. f For more information about byte serializer, refer to the Arria GX Transceiver Architecture chapter.
Receiver Phase Compensation FIFO Buffer
A receiver phase compensation FIFO buffer is located at each receiver channel’s logic array interface. It compensates for the phase difference between the receiver PCS clock and the local PLD receiver clock. The receiver phase compensation FIFO is used in all supported functional modes. The receiver phase compensation FIFO buffer is eight words deep in PCI Express (PIPE) mode and four words deep in all other modes. f For more information about architecture and clocking, refer to the Arria GX Transceiver Architecture chapter.
Loopback Modes
Arria GX transceivers support the following loopback configurations for diagnostic purposes:
■ ■ ■ ■
Serial loopback Reverse serial loopback Reverse serial loopback (pre-CDR) PCI Express (PIPE) reverse parallel loopback (available only in [PIPE] mode)
Serial Loopback
Figure 2–18 shows the transceiver data path in serial loopback.
Figure 2–18. Transceiver Data Path in Serial Loopback
Transmitter PCS
TX Phase Compensation FIFO Byte Serializer 8B/10B Encoder
Transmitter PMA
Serializer
PLD Logic Array Receiver PCS
RX Phase Compensation FIFO Byte DeSerializer 8B/10B Decoder Rate Match FIFO Word Aligner
Serial Loopback
Receiver PMA
DeSerializer Clock Recovery Unit
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In GIGE and Serial RapidIO modes, you can dynamically put each transceiver channel individually in serial loopback by controlling the rx_seriallpbken port. A high on the rx_seriallpbken port puts the transceiver into serial loopback and a low takes the transceiver out of serial loopback. As seen in Figure 2–18, the serial data output from the transmitter serializer is looped back to the receiver CRU in serial loopback. The transmitter data path from the PLD interface to the serializer in serial loopback is the same as in non-loopback mode. The receiver data path from the clock recovery unit to the PLD interface in serial loopback is the same as in non-loopback mode. Because the entire transceiver data path is available in serial loopback, this option is often used to diagnose the data path as a probable cause of link errors. 1 When serial loopback is enabled, the transmitter output buffer is still active and drives the serial data out on the tx_dataout port.
Reverse Serial Loopback
Reverse serial loopback mode uses the analog portion of the transceiver. An external source (pattern generator or transceiver) generates the source data. The high-speed serial source data arrives at the high-speed differential receiver input buffer, passes through the CRU unit and the retimed serial data is looped back, and is transmitted though the high-speed differential transmitter output buffer. Figure 2–19 shows the data path in reverse serial loopback mode.
Figure 2–19. Arria GX Block in Reverse Serial Loopback Mode
Transmitter Digital Logic
BIST Incremental Generator BIST PRBS Generator
Analog Receiver and Transmitter Logic
TX Phase Compensation FIFO FPGA Logic Array BIST Incremental Verify RX Phase Compensation FIFO
Byte Serializer
8B/10B 20 Encoder
Serializer
Reverse Serial Loopback BIST PRBS Verify Byte Deserializer 8B/10B Decoder Rate Match FIFO Deskew FIFO Word Aligner Deserializer Clock Recovery Unit
Receiver Digital Logic
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Reverse Serial Pre-CDR Loopback
Reverse serial pre-CDR loopback mode uses the analog portion of the transceiver. An external source (pattern generator or transceiver) generates the source data. The high-speed serial source data arrives at the high-speed differential receiver input buffer, loops back before the CRU unit, and is transmitted though the high-speed differential transmitter output buffer. It is for test or verification use only to verify the signal being received after the gain and equalization improvements of the input buffer. The signal at the output is not exactly what is received because the signal goes through the output buffer and the VO D is changed to the VOD setting level. Pre-emphasis settings have no effect. Figure 2–20 shows the Arria GX block in reverse serial pre-CDR loopback mode.
Figure 2–20. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Transmitter Digital Logic
BIST Incremental Generator BIST PRBS Generator
Analog Receiver and Transmitter Logic
TX Phase Compensation FIFO FPGA Logic Array BIST Incremental Verify RX Phase Compensation FIFO
Byte Serializer
8B/10B 20 Encoder
Serializer
BIST PRBS Verify Byte Deserializer 8B/10B Decoder Rate Match FIFO Deskew FIFO Word Aligner Deserializer
Reverse Serial Pre-CDR Loopback
Clock Recovery Unit
Receiver Digital Logic
PCI Express (PIPE) Reverse Parallel Loopback
Figure 2–21 shows the data path for PCI Express (PIPE) reverse parallel loopback. The reverse parallel loopback configuration is compliant with the PCI Express (PIPE) specification and is available only on PCI Express (PIPE) mode.
Figure 2–21. PCI Express (PIPE) Reverse Parallel Loopback
Transmitter PCS
TX Phase Compensation FIFO Byte Serializer 8B/10B Encoder
Transmitter PMA
Serializer
PIPE Interface
PIPE Reverse Parallel Loopback
Receiver PCS
RX Phase Compensation FIFO
Receiver PMA
DeSerializer Clock Recovery Unit
Byte DeSerializer
8B/10B Decoder
Rate Match FIFO
Word Aligner
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You can dynamically put the PCI Express (PIPE) mode transceiver in reverse parallel loopback by controlling the tx_detectrxloopback port instantiated in the MegaWizard Plug-In Manager. A high on the tx_detectrxloopback port in P0 power state puts the transceiver in reverse parallel loopback. A high on the tx_detectrxloopback port in any other power state does not put the transceiver in reverse parallel loopback. As seen in Figure 2–21, the serial data received on the rx_datain port in reverse parallel loopback goes through the CRU, deserializer, word aligner, and the rate matcher blocks. The parallel data at the output of the receiver rate matcher block is looped back to the input of the transmitter serializer block. The serializer converts the parallel data to serial data and feeds it to the transmitter output buffer that drives the data out on the tx_dataout port. The data at the output of the rate matcher also goes through the 8B/10B decoder, byte deserializer, and receiver phase compensation FIFO before being fed to the PLD on the rx_dataout port.
Reset and Powerdown
Arria GX transceivers offer a power saving advantage with their ability to shut off functions that are not needed. The following three reset signals are available per transceiver channel and can be used to individually reset the digital and analog portions within each channel:
■ ■ ■
tx_digitalreset rx_analogreset rx_digitalreset
The following two powerdown signals are available per transceiver block and can be used to shut down an entire transceiver block that is not being used:
■ ■
gxb_powerdown gxb_enable
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Table 2–6 lists the reset signals available in Arria GX devices and the transceiver circuitry affected by each signal.
Table 2–6. Reset Signal Map to Arria GX Blocks Transmitter Phase Compensation FIFO Module/ Byte Serializer
Receiver Deskew FIFO Module
Reset Signal
Receiver Phase Comp FIFO Module/ Byte Deserializer
Transmitter XAUI State Machine
Receiver XAUI State Machine
Transmitter 8B/10B Encoder
Transmitter Analog Circuits
Receiver 8B/10B Decoder
rx_digitalreset rx_analogreset tx_digitalreset gxb_powerdown gxb_enable
— — v v v
— — v v v
— — — v v
— — — v v
— — — v v
— — v v v
— — v v v
— v — v v
v — — v v
— — — — —
v — — v v
v — — v v
v — — v v
— v — v v
v — — v v
v — — v v
— v — v v
Calibration Block
Arria GX devices use the calibration block to calibrate OCT for the PLLs, and their associated output buffers, and the terminating resistors on the transceivers. The calibration block counters the effects of process, voltage, and temperature (PVT). The calibration block references a derived voltage across an external reference resistor to calibrate the OCT resistors on Arria GX devices. You can power down the calibration block. However, powering down the calibration block during operations can yield transmit and receive data errors.
Transceiver Clocking
This section describes the clock distribution in an Arria GX transceiver channel and the PLD clock resource utilization by the transceiver blocks.
Transceiver Channel Clock Distribution
Each transceiver block has one transmitter PLL and four receiver PLLs.
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Receiver Analog Circuits
Receiver Rate Matcher
Receiver Word Aligner
Transmitter Serializer
Receiver Deserializer
Receiver PLL / CRU
BIST Generators
Transmitter PLL
BIST Verifiers
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The transmitter PLL multiplies the input reference clock to generate a high-speed serial clock at a frequency that is half the data rate of the configured functional mode. This high-speed serial clock (or its divide-by-two version if the functional mode uses byte serializer) is fed to the CMU clock divider block. Depending on the configured functional mode, the CMU clock divider block divides the high-speed serial clock to generate the low-speed parallel clock that clocks the transceiver PCS logic in the associated channel. The low-speed parallel clock is also forwarded to the PLD logic array on the tx_clkout or coreclkout ports. The receiver PLL in each channel is also fed by an input reference clock. The receiver PLL along with the clock recovery unit generates a high-speed serial recovered clock and a low-speed parallel recovered clock. The low-speed parallel recovered clock feeds the receiver PCS logic until the rate matcher. The CMU low-speed parallel clock clocks the rest of the logic from the rate matcher until the receiver phase compensation FIFO. In modes that do not use a rate matcher, the receiver PCS logic is clocked by the recovered clock until the receiver phase compensation FIFO. The input reference clock to the transmitter and receiver PLLs can be derived from:
■
One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1) of the associated transceiver block PLD clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL) Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
■
■
Figure 2–22 shows the input reference clock sources for the transmitter and receiver PLL.
Figure 2–22. Input Reference Clock Sources
Inter-Transceiver Lines [2]
Transceiver Block 2 Transceiver Block 1 Transceiver Block 0
Inter-Transceiver Lines [1]
Inter-Transceiver Lines [0]
Dedicated REFCLK0 Dedicated REFCLK1
/2 /2
Transmitter PLL
Inter-Transceiver Lines [2:0] Global Clock (1)
Four Receiver PLLs
Global Clock (1)
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f
For more information about transceiver clocking in all supported functional modes, refer to the Arria GX Transceiver Architecture chapter.
PLD Clock Utilization by Transceiver Blocks
Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional clock (RCLK) lines that are used to route the transceiver clocks. The following transceiver clocks use the available global and regional clock resources:
■ ■ ■ ■ ■ ■
pll_inclk (if driven from an FPGA input pin) rx_cruclk (if driven from an FPGA input pin) tx_clkout/coreclkout (CMU low-speed parallel clock forwarded to the PLD) Recovered clock from each channel (rx_clkout) in non-rate matcher mode Calibration clock (cal_blk_clk) Fixed clock (fixedclk used for receiver detect circuitry in PCI Express [PIPE] mode only)
Figure 2–23 and Figure 2–24 show the available GCLK and RCLK resources in Arria GX devices.
Figure 2–23. Global Clock Resources in Arria GX Devices
CLK[15..12] 11 5 7
GCLK[15..12]
Arria GX Transceiver Block
CLK[3..0]
1 2
GCLK[3..0]
GCLK[11..8]
GCLK[4..7]
Arria GX Transceiver Block
8 12 6 CLK[7..4]
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Figure 2–24. Regional Clock Resources in Arria GX Devices
CLK[15..12] 11 5 7 RCLK [31..28] RCLK [27..24] Arria GX Transceiver Block
RCLK [3..0] 1 2 RCLK [7..4]
RCLK [23..20]
CLK[3..0]
RCLK [19..16]
Arria GX Transceiver Block
8
RCLK [11..8] 12 6 CLK[7..4]
RCLK [15..12]
For the RCLK or GCLK network to route into the transceiver, a local route input output (LRIO) channel is required. Each LRIO clock region has up to eight clock paths and each transceiver block has a maximum of eight clock paths for connecting with LRIO clocks. These resources are limited and determine the number of clocks that can be used between the PLD and transceiver blocks. Table 2–7 and Table 2–8 list the number of LRIO resources available for Arria GX devices with different numbers of transceiver blocks.
Table 2–7. Available Clocking Connections for Transceivers in EP1AGX35D, EP1AGX50D, and EP1AGX60D Clock Resource Source Global Clock Region0 8 LRIO clock Region1 8 LRIO clock v v Regional Clock RCLK 20-27 RCLK 12-19 Transceiver Bank13 8 Clock I/O v — Bank14 8 Clock I/O — v
Table 2–8. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E Clock Resource Source Global Clock Region0 8 LRIO clock Region1 8 LRIO clock Region2 8 LRIO clock Region3 8 LRIO clock v v v v Regional Clock RCLK 20-27 RCLK 20-27 RCLK 12-19 RCLK 12-19 Bank13 8 Clock I/O v v — — Transceiver Bank14 8 Clock I/O — v v — Bank15 8 Clock I/O — — v v
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Logic Array Blocks
Each logic array block (LAB) consists of eight adaptive logic modules (ALMs), carry chains, shared arithmetic chains, LAB control signals, local interconnects, and register chain connection lines. The local interconnect transfers signals between ALMs in the same LAB. Register chain connections transfer the output of an ALM register to the adjacent ALM register in a LAB. The Quartus II Compiler places associated logic in a LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. Table 2–9 lists Arria GX device resources. Figure 2–25 shows the Arria GX LAB structure.
Table 2–9. Arria GX Device Resources Device EP1AGX20 EP1AGX35 EP1AGX50 EP1AGX60 EP1AGX90 M512 RAM Columns/Blocks 166 197 313 326 478 M4K RAM Columns/Blocks 118 140 242 252 400 M-RAM Blocks 1 1 2 2 4 DSP Block Columns/Blocks 10 14 26 32 44
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Figure 2–25. Arria GX LAB Structure
Row Interconnects of Variable Speed & Length
ALMs
Direct link interconnect from adjacent block Direct link interconnect from adjacent block
Direct link interconnect to adjacent block
Direct link interconnect to adjacent block
Local Interconnect
LAB
Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows
Column Interconnects of Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive all eight ALMs in the same LAB. It is driven by column and row interconnects and ALM outputs in the same LAB. Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM blocks, or digital signal processing (DSP) blocks from the left and right can also drive the local interconnect of a LAB through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each ALM can drive 24 ALMs through fast local and direct link interconnects.
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Figure 2–26 shows the direct link connection.
Figure 2–26. Direct Link Connection
Direct link interconnect from left LAB, TriMatrixTM memory block, DSP block, or input/output element (IOE) Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output
ALMs
Direct link interconnect to left Local Interconnect
Direct link interconnect to right
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs. The control signals include three clocks, three clock enables, two asynchronous clears, synchronous clear, asynchronous preset or load, and synchronous load control signals, providing a maximum of 11 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use three clocks and three clock enable signals. However, there can only be up to two unique clocks per LAB, as shown in the LAB control signal generation circuit in Figure 2–27. Each LAB’s clock and clock enable signals are linked. For example, any ALM in a particular LAB using the labclk1 signal also uses labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses two LAB-wide clock signals. De-asserting the clock enable signal turns off the corresponding LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high. When the asynchronous load/preset signal is used, the labclkena0 signal is no longer available. The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrack interconnects have inherently low skew. This low skew allows the MultiTrack interconnects to distribute clock and control signals in addition to data.
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Figure 2–27 shows the LAB control signal generation circuit.
Figure 2–27. LAB-Wide Control Signals
There are two unique clock signals per LAB. 6 Dedicated Row LAB Clocks 6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0 labclkena0 or asyncload or labpreset
labclk1 labclkena1
labclk2 labclkena2
syncload labclr0
labclr1 synclr
Adaptive Logic Modules
The basic building block of logic in the Arria GX architecture is the ALM. The ALM provides advanced features with efficient logic utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided between two adaptive LUTs (ALUTs). With up to eight inputs to the two ALUTs, one ALM can implement various combinations of two functions. This adaptability allows the ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function of up to six inputs and certain seven-input functions. In addition to the adaptive LUT-based resources, each ALM contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. Through these dedicated resources, the ALM can efficiently implement various arithmetic functions and shift registers. Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. Figure 2–28 shows a high-level block diagram of the Arria GX ALM while Figure 2–29 shows a detailed view of all the connections in the ALM.
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Figure 2–28. High-Level Block Diagram of the Arria GX ALM
carry_in shared_arith_in reg_chain_in To general or local routing adder0
D Q
dataf0 datae0 dataa datab datac datad datae1 dataf1 reg1 Combinational Logic adder1
D Q
To general or local routing
reg0
To general or local routing
To general or local routing carry_out shared_arith_out reg_chain_out
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shared_arith_in carry_in syncload ena[2..0] reg_chain_in sclr asyncload dataf0 datae0 4-Input LUT Row, column & direct link routing
PRN/ALD D Q ADATA ENA CLRN
Chapter 2: Arria GX Architecture Adaptive Logic Modules
Figure 2–29. Arria GX ALM Details
Altera Corporation
datac 3-Input LUT dataa 3-Input LUT datab 4-Input LUT datad 3-Input LUT
PRN/ALD D Q ADATA ENA CLRN
Local Interconnect
Local Interconnect
Local Interconnect
Row, column & direct link routing Local Interconnect
Local Interconnect
Local
Interconnect
Local Interconnect
Row, column & direct link routing Row, column & direct link routing Local Interconnect VCC
3-Input LUT
Local Interconnect dataf1
datae1
Local Interconnect
carry_out shared_arith_out
reg_chain_out
clk[2..0] aclr[1..0]
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One ALM contains two programmable registers. Each register has data, clock, clock enable, synchronous and asynchronous clear, asynchronous load data, and synchronous and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous load data. The asynchronous load data input comes from the datae or dataf input of the ALM, which are the same inputs that can be used for register packing. For combinational functions, the register is bypassed and the output of the LUT drives directly to the outputs of the ALM. Each ALM has two sets of outputs that drive the local, row, and column routing resources. The LUT, adder, or register output can drive these output drivers independently (refer to Figure 2–29). For each set of output drivers, two ALM outputs can drive column, row, or direct link routing connections. One of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and combinational logic for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. This feature provides another mechanism for improved fitting. The ALM can also drive out registered and unregistered versions of the LUT or adder output.
ALM Operating Modes
The Arria GX ALM can operate in one of the following modes:
■ ■ ■ ■
Normal mode Extended LUT mode Arithmetic mode Shared arithmetic mode
Each mode uses ALM resources differently. Each mode has 11 available inputs to the ALM (refer to Figure 2–28)the eight data inputs from the LAB local interconnect; carry-in from the previous ALM or LAB; the shared arithmetic chain connection from the previous ALM or LAB; and the register chain connectionare directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all ALM modes. For more information about LAB-wide control signals, refer to “LAB Control Signals” on page 2–30. The Quartus II software and supported third-party synthesis tools, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, you can also create special-purpose functions that specify which ALM operating mode to use for optimal performance.
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Normal Mode
Normal mode is suitable for general logic applications and combinational functions. In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. Normal mode allows two functions to be implemented in one Arria GX ALM, or an ALM to implement a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions which have common inputs. Figure 2–30 shows the supported LUT combinations in normal mode.
Figure 2–30. ALM in Normal Mode ( Note 1)
dataf0 datae0 datac dataa datab datad datae1 dataf1
4-Input LUT
combout0
dataf0 datae0 datac dataa datab
5-Input LUT
combout0
4-Input LUT
combout1 datad datae1 dataf1
5-Input LUT
combout1
dataf0 datae0 datac dataa datab
5-Input LUT
combout0
datad datae1 dataf1
dataf0 datae0 dataa datab datac datad
6-Input LUT
combout0
3-Input LUT
combout1
dataf0 datae0 datac dataa datab
5-Input LUT
combout0
dataf0 datae0 dataa datab datac datad
6-Input LUT
combout0
datad datae1 dataf1
4-Input LUT
combout1
datae1 dataf1
6-Input LUT
combout1
Note to Figure 2–30:
(1) Combinations of functions with less inputs than those shown are also supported. For example, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, and so on.
Normal mode provides complete backward compatibility with four-input LUT architectures. Two independent functions of four inputs or less can be implemented in one Arria GX ALM. In addition, a five-input function and an independent three-input function can be implemented without sharing inputs.
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To pack two five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab). To implement two six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. For example, a 4 × 2 crossbar switch (two 4-to-1 multiplexers with common inputs and unique select lines) can be implemented in one ALM, as shown in Figure 2–31. The shared inputs are dataa, datab, datac, and datad, while the unique select lines are datae0 and dataf0 for function0, and datae1 and dataf1 for function1. This crossbar switch consumes four LUTs in a four-input LUT-based architecture.
Figure 2–31. 4 × 2 Crossbar Switch Example
4 ´ 2 Crossbar Switch sel0[1..0] inputa inputb inputc inputd out1 sel1[1..0] datae1 dataf1 Six-Input LUT (Function1) out0 dataf0 datae0 dataa datab datac datad Implementation in 1 ALM
Six-Input LUT (Function0)
combout0
combout1
In a sparsely used device, functions that can be placed into one ALM can be implemented in separate ALMs. The Quartus II Compiler spreads a design out to achieve the best possible performance. As a device begins to fill up, the Quartus II software automatically uses the full potential of the Arria GX ALM. The Quartus II Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. In addition, you can manually control resource usage by setting location assignments. Any six-input function can be implemented utilizing inputs dataa, datab, datac, datad, and either datae0 and dataf0 or datae1 and dataf1. If datae0 and dataf0 are used, the output is driven to register0, and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (refer to Figure 2–32). If datae1 and dataf1 are used, the output drives to register1 and/or bypasses register1 and drives to the interconnect using the bottom set of output drivers. The Quartus II Compiler automatically selects the inputs to the LUT. Asynchronous load data for the register comes from the datae or dataf input of the ALM. ALMs in normal mode support register packing.
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Figure 2–32. Six-Input Function in Normal Mode Note (1), (2)
dataf0 datae0 dataa datab datac datad datae1 dataf1 (2) These inputs are available for register packing. To general or local routing 6-Input LUT
D Q
To general or local routing
reg0
D
Q
To general or local routing
reg1
Notes to Figure 2–32:
(1) If datae1 and dataf1 are used as inputs to the six-input function, datae0 a nd dataf0 are available for register packing. (2) The dataf1 input is available for register packing only if the six-input function is un-registered.
Extended LUT Mode
Extended LUT mode is used to implement a specific set of seven-input functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs. Figure 2–33 shows the template of supported seven-input functions utilizing extended LUT mode. In this mode, if the seven-input function is unregistered, the unused eighth input is available for register packing. Functions that fit into the template shown in Figure 2–33 occur naturally in designs. These functions often appear in designs as “if-else” statements in Verilog HDL or VHDL code.
Figure 2–33. Template for Supported Seven-Input Functions in Extended LUT Mode
datae0 datac dataa datab datad dataf0 5-Input LUT combout0
D Q
To general or local routing To general or local routing
5-Input LUT datae1 dataf1 (1) This input is available for register packing.
reg0
Note to Figure 2–33:
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available.
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Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An ALM in arithmetic mode uses two sets of 2 four-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of two four-input functions. The four LUTs share the dataa and datab inputs. As shown in Figure 2–34, the carry-in signal feeds to adder0, and the carry-out from adder0 feeds to carry-in of adder1. The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs.
Figure 2–34. ALM in Arithmetic Mode
carry_in
datae0 4-Input LUT
adder0 To general or local routing
D Q
dataf0 datac datab dataa
To general or local routing
4-Input LUT
reg0
adder1 datad datae1 4-Input LUT
D Q
To general or local routing To general or local routing
4-Input LUT dataf1 carry_out
reg1
While operating in arithmetic mode, the ALM can support simultaneous use of the adder’s carry output along with combinational logic outputs. In this operation, adder output is ignored. This usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. An example of such functionality is a conditional operation, such as the one shown in Figure 2–35. The equation for this example is:
Equation 2–1.
R = (X < Y) ? Y : X To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If ‘X’ is less than ‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is fed to an adder where it drives out to the LAB local interconnect. It then feeds to the LAB-wide syncload signal. When asserted, syncload selects the syncdata input. In this case, the data ‘Y’ drives the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the syncload signal is deasserted and ‘X’ drives the data port of the registers.
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Figure 2–35. Conditional Operation Example
Adder output is not used. ALM 1 X[0] Y[0] syncdata X[1] Y[1] Comb & Adder Logic X[1] R[1]
D Q
Comb & Adder Logic
X[0] R[0]
D Q
To general or local routing
reg0 syncload
To general or local routing
reg1 Carry Chain ALM 2 X[2] Y[2] Comb & Adder Logic syncload
X[2]
D Q
R[2] reg0 syncload
To general or local routing
Comb & Adder Logic
carry_out
To local routing & then to LAB-wide syncload
Arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchronous clear, and synchronous load. The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up/down and add/subtract control signals. These control signals can be used for the inputs that are shared between the four LUTs in the ALM. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs.
Carry Chain
Carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects. The Quartus II Compiler automatically creates carry chain logic during compilation, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column. To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB before connecting to the next LAB.
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The other half of the ALMs in the LAB is available for implementing narrower fan-in functions in normal mode. Carry chains that use the top four ALMs in the first LAB carries into the top half of the ALMs in the next LAB within the column. Carry chains that use the bottom four ALMs in the first LAB carries into the bottom half of the ALMs in the next LAB within the column. Every other column of the LABs are top-half bypassable, while the other LAB columns are bottom-half bypassable. For more information about carry chain interconnect, refer to “MultiTrack Interconnect” on page 2–44.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In this mode, the ALM is configured with four 4-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder (either to adder1 in the same ALM or to adder0 of the next ALM in the LAB) using a dedicated connection called the shared arithmetic chain. This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree. Figure 2–36 shows the ALM in shared arithmetic mode.
Figure 2–36. ALM in Shared Arithmetic Mode
shared_arith_in carry_in
4-Input LUT
D Q
To general or local routing To general or local routing
datae0 datac datab dataa
4-Input LUT
reg0
datad datae1
4-Input LUT
D Q
To general or local routing To general or local routing
4-Input LUT
reg1
carry_out shared_arith_out
Note to Figure 2–36:
(1) Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
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Adder trees are used in many different applications. For example, the summation of partial products in a logic-based multiplier can be implemented in a tree structure. Another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de-spread data which was transmitted utilizing spread spectrum technology. An example of a three-bit add operation utilizing the shared arithmetic mode is shown in Figure 2–37. The partial sum (S[2..0]) and the partial carry (C[2..0]) is obtained using LUTs, while the result (R[2..0]) is computed using dedicated adders.
Figure 2–37. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
shared_arith_in = '0' carry_in = '0' 3-Bit Add Example X2 X1 X0 Y2 Y1 Y0 + Z2 Z1 Z0 S2 S1 S0 + C2 C1 C0 R3 R2 R1 R0 X0 Y0 Z0 X1 Y1 Z1 ALM Implementation ALM 1 1st stage add is implemented in LUTs. 2nd stage add is implemented in adders. 3-Input LUT S0 R0 3-Input LUT C0
Binary Add 110 101 +010 001 +110 1101
Decimal Equivalents 6 5 +2 1 + 2x6 13
3-Input LUT
S1
R1 3-Input LUT ALM 2 3-Input LUT S2 R2 X2 Y2 Z2 3-Input LUT C2 C1
3-Input LUT
'0' R3
3-Input LUT
Shared Arithmetic Chain
In addition to dedicated carry chain routing, the shared arithmetic chain available in shared arithmetic mode allows the ALM to implement a three-input add, which significantly reduces the resources necessary to implement large adder trees or correlator functions. Shared arithmetic chains can begin in either the first or fifth ALM in a LAB. The Quartus II Compiler automatically links LABs to create shared arithmetic chains longer than 16 (eight ALMs in arithmetic or shared arithmetic mode). For enhanced fitting, a long shared arithmetic chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column. Similar to carry chains, shared arithmetic
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chains are also top- or bottom-half bypassable. This capability allows the shared arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other half available for narrower fan-in functionality. Every other LAB column is top-half bypassable, while the other LAB columns are bottom-half bypassable. For more information about shared arithmetic chain interconnect, refer to “MultiTrack Interconnect” on page 2–44.
Register Chain
In addition to the general routing outputs, the ALMs in a LAB have register chain outputs. Register chain routing allows registers in the same LAB to be cascaded together. The register chain interconnect allows a LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between ALMs while saving local interconnect resources (refer to Figure 2–38). The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. For more information about register chain interconnect, refer to “MultiTrack Interconnect” on page 2–44.
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Figure 2–38. Register Chain within a LAB
(Note 1)
From Previous ALM Within The LAB reg_chain_in To general or local routing adder0
D Q
To general or local routing
reg0 Combinational Logic adder1
D Q
To general or local routing
reg1 To general or local routing
To general or local routing adder0
D Q
To general or local routing
reg0 Combinational Logic adder1
D Q
To general or local routing
reg1 To general or local routing
reg_chain_out To Next ALM within the LAB
Note to Figure 2–38:
(1) The combinational or adder logic can be used to implement an unrelated, unregistered function.
Clear and Preset Logic Control
LAB-wide signals control the logic for the register ’s clear and load/preset signals. The ALM directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOT gate push-back technique. Arria GX devices support simultaneous asynchronous load/preset and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one load/preset signal.
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In addition to the clear and load/preset ports, Arria GX devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This device-wide reset overrides all other control signals.
MultiTrack Interconnect
In Arria GX architecture, the MultiTrack interconnect structure with DirectDrive technology provides connections between ALMs, TriMatrix memory, DSP blocks, and device I/O pins. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for interand intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory in the same row. These row resources include:
■ ■ ■
Direct link interconnects between LABs and adjacent blocks R4 interconnects traversing four blocks to the right or left R24 row interconnects for high-speed access across the length of the device
The direct link interconnect allows a LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself, providing fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, three LABs and one M512 RAM block, two LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of a source LAB. These resources are used for fast row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2–39 shows R4 interconnect connections from a LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive onto the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive onto the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects.
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Figure 2–39. R4 Interconnect Connections
(Note 1) , (2), ( 3)
Adjacent LAB can Drive onto Another LAB's R4 Interconnect C4 and C16 Column Interconnects (1) R4 Interconnect Driving Right
R4 Interconnect Driving Left
LAB Neighbor
Primary LAB (2)
LAB Neighbor
Notes to Figure 2–39:
(1) C4 and C16 interconnects can drive R4 interconnects. (2) This pattern is repeated for every LAB in the LAB row. (3) The LABs in Figure 2–39 show the 16 possible logical outputs per LAB.
R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect. These column resources include:
■ ■ ■ ■ ■
Shared arithmetic chain interconnects in a LAB Carry chain interconnects in a LAB and from LAB to LAB Register chain interconnects in a LAB C4 interconnects traversing a distance of four blocks in up and down direction C16 column interconnects for high-speed vertical routing through the device
Arria GX devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers. These ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2–40 shows shared arithmetic chain, carry chain, and register chain interconnects.
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Figure 2–40. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects
Local Interconnect Routing Among ALMs in the LAB Carry Chain & Shared Arithmetic Chain Routing to Adjacent ALM ALM 1
Register Chain Routing to Adjacent ALM's Register Input
ALM 2 Local Interconnect ALM 3 ALM 4 ALM 5 ALM 6 ALM 7
ALM 8
C4 interconnects span four LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2–41 shows the C4 interconnect connections from a LAB in a column. C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections.
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Figure 2–41. C4 Interconnect Connections
(Note 1)
C4 Interconnect Drives Local and R4 Interconnects up to Four Rows
C4 Interconnect Driving Up
LAB
Row Interconnect
Adjacent LAB can drive onto neighboring LAB's C4 interconnect
Local Interconnect
C4 Interconnect Driving Down
Note to Figure 2–41:
(1) Each C4 interconnect can drive either up or down four rows.
C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross M-RAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar to LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[5..0].
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Table 2–10 lists the routing scheme for Arria GX device.
Table 2–10. Arria GX Device Routing Scheme Destination Shared Arithmetic Chain Direct Link Interconnect
Local Interconnect
R24 Interconnect
C16 Interconnect
M512 RAM Block
R4 Interconnect
C4 Interconnect
Register Chain
M-RAM Block
Source
M4K RAM Block
Carry Chain
Column IOE — — — v — — — — — — — — — — — — v v v —
DSP Blocks
Shared arithmetic chain Carry chain Register chain Local interconnect Direct link interconnect R4 interconnect R24 interconnect C4 interconnect C16 interconnect ALM M512 RAM block M4K RAM block M-RAM block DSP blocks Column IOE Row IOE
— — — — — — — — — v — — — — — —
— — — — — — — — — v — — — — — —
— — — — — — — — — v — — — — — —
— — — — v v — v — v v v — — — —
— — — — — — — — — v v v v v v v
— — — — — v v v v v v v v v — v
— — — — — v v — v — — — v — — v
— — — — — v v v v v v v v v v v
— — — — — v v — v — — — — — v —
v v v v — — — — — — — — — — — —
— — — v — — — — — — — — — — — —
— — — v — — — — — — — — — — — —
— — — v — — — — — — — — — — — —
— — — v — — — — — — — — — — — —
— — — v — — — — — — — — — — — —
TriMatrix Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 2–11 lists the size and features of the different RAM blocks.
Table 2–11. TriMatrix Memory Features (Part 1 of 2) Memory Feature Maximum performance True dual-port memory Simple dual-port memory Single-port memory Shift register M512 RAM Block (32 × 18 Bits) 345 MHz — v v v M4K RAM Block (128 × 36 Bits) 380 MHz v v v v M-RAM Block (4K × 144 Bits) 290 MHz
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Table 2–11. TriMatrix Memory Features (Part 2 of 2) Memory Feature ROM FIFO buffer Pack mode Byte enable Address clock enable Parity bits Mixed clock mode Memory initialization file (.mif) Simple dual-port memory mixed width support True dual-port memory mixed width support Power-up conditions Register clears Mixed-port read-during-write M512 RAM Block (32 × 18 Bits) v v — v — v v v v — Outputs cleared Output registers Unknown output/old data M4K RAM Block (128 × 36 Bits) v v v v v v v v v v Outputs cleared Output registers Unknown output/old data 4K × 1 512 × 1 256 × 2 128 × 4 Configurations 64 × 8 64 × 9 32 × 16 32 × 18 2K × 2 1K × 4 512 × 8 512 × 9 256 × 16 256 × 18 128 × 32 128 × 36 M-RAM Block (4K × 144 Bits) — v v v v v v — v v Outputs unknown Output registers Unknown output 64K × 8 64K × 9 32K × 16 32K × 18 16K × 32 16K × 36 8K × 64 8K × 72 4K × 128 4K × 144
TriMatrix memory provides three different memory sizes for efficient application support. The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. You can also manually assign the memory to a specific block size or a mixture of block sizes.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes:
■ ■ ■ ■ ■
Simple dual-port RAM Single-port RAM FIFO ROM Shift register
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When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block, allowing the RAM block to operate in read and write or input and output clock modes. Only the output register can be bypassed. The six labclk signals or local interconnect can drive the inclock, outclock, wren, rden, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, ALMs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2–42 shows the M512 RAM block control signal generation logic.
Figure 2–42. M512 RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect 6
Local Interconnect
Local Interconnect Local Interconnect
Local Interconnect Local Interconnect Local Interconnect Local Interconnect inclock
inclocken
outclocken
wren outclr
outclock
rden
The RAM blocks in Arria GX devices have local interconnects to allow ALMs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. The M512 RAM block has up to 16 direct link input connections from the left adjacent LABs and another 16 from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through direct link interconnect. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 2–43 shows the M512 RAM block to logic array interface.
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Figure 2–43. M512 RAM Block LAB Row Interface
C4 Interconnect R4 Interconnect
Direct link interconnect to adjacent LAB
16 36 dataout
Direct link interconnect to adjacent LAB
Direct link interconnect from adjacent LAB
M4K RAM Block datain control signals clocks byte enable
Direct link interconnect from adjacent LAB
address
6 M4K RAM Block Local Interconnect Region LAB Row Clocks
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes:
■ ■ ■ ■ ■ ■
True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register
When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a , and clocken_b signals, as shown in Figure 2–44.
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Figure 2–44. M4K RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect 6
clock_b
clocken_b renwe_a
renwe_b aclr_a
aclr_b
clock_a
clocken_a
The R4, C4, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 16 direct link input connections to the M4K RAM block are possible from the left adjacent LABs and another 16 are possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 2–45 shows the M4K RAM block to logic array interface.
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Figure 2–45. M4K RAM Block LAB Row Interface
C4 Interconnect R4 Interconnect
Direct link interconnect to adjacent LAB
16 36 dataout
Direct link interconnect to adjacent LAB
Direct link interconnect from adjacent LAB
M4K RAM Block datain control signals clocks byte enable
Direct link interconnect from adjacent LAB
address
6 M4K RAM Block Local Interconnect Region LAB Row Clocks
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824 RAM bits (including parity bits). The M-RAM block can be configured in the following modes:
■ ■ ■ ■
True dual-port RAM Simple dual-port RAM Single-port RAM FIFO
You cannot use an initialization file to initialize the contents of a M-RAM block. All M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed. Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M-RAM block registers (renwe, address, byte enable, datain, and output registers). You can bypass the output register. The six labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2–46.
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Figure 2–46. M-RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect clock_a clocken_a renwe_a aclr_b renwe_b clocken_b clock_b 6
Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect
aclr_a
The R4, R24, C4, and direct link interconnects from adjacent LABs on either the right or left side drive the M-RAM block local interconnect. Up to 16 direct link input connections to the M-RAM block are possible from the left adjacent LABs and another 16 are possible from the right adjacent LAB. M-RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 2–47 shows an example floorplan for the EP1AGX90 device and the location of the M-RAM interfaces. Figure 2–48 and Figure 2–49 show the interface between the M-RAM block and the logic array.
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Figure 2–47. EP1AGX90 Device with M-RAM Interface Locations
M-RAM blocks interface to LABs on right and left sides for easy access to horizontal I/O pins
(Note 1)
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
M4K Blocks
M512 Blocks
DSP Blocks
LABs
DSP Blocks
Note to Figure 2–47:
(1) The device shown is an EP1AGX90 device. The number and position of M-RAM blocks vary in other devices.
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Figure 2–48. M-RAM Block LAB Row Interface (Note 1)
Row Unit Interface Allows LAB Rows to Drive Port A Datain, Dataout, Address and Control Signals to and from M-RAM Block Row Unit Interface Allows LAB Rows to Drive Port B Datain, Dataout, Address and Control Signals to and from M-RAM Block
L0 L1 M-RAM Block L2 Port A
R0 R1
Port B R2 R3 R4 R5
L3 L4 L5
LAB Interface Blocks LABs in Row M-RAM Boundary LABs in Row M-RAM Boundary
Note to Figure 2–48:
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
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Figure 2–49. M-RAM Row Unit Interface to Interconnect
C4 Interconnect R4 and R24 Interconnects M-RAM Block
LAB
Up to 16 dataout_a[ ]
16
Direct Link Interconnects
Up to 28
datain_a[ ] addressa[ ] addr_ena_a renwe_a byteenaA[ ] clocken_a clock_a aclr_a
Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region
Table 2–12 lists the input and output data signal connections along with the address and control signal input connections to the row unit interfaces (L0 to L5 and R0 to R5).
Table 2–12. M-RAM Row Interface Unit Signals (Part 1 of 2) Unit Interface Block L0 L1 Input Signals datain_a[14..0] byteena_a[1..0] datain_a[29..15] byteena_a[3..2] datain_a[35..30] addressa[4..0] addr_ena_a L2 clock_a clocken_a renwe_a aclr_a L3 addressa[15..5] datain_a[41..36] dataout_a[47..36] dataout_a[35..24] dataout_a[23..12] Output Signals dataout_a[11..0]
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Table 2–12. M-RAM Row Interface Unit Signals (Part 2 of 2) Unit Interface Block L4 L5 R0 R1 Input Signals datain_a[56..42] byteena_a[5..4] datain_a[71..57] byteena_a[7..6] datain_b[14..0] byteena_b[1..0] datain_b[29..15] byteena_b[3..2] datain_b[35..30] addressb[4..0] addr_ena_b R2 clock_b clocken_b renwe_b aclr_b R3 R4 R5 addressb[15..5] datain_b[41..36] datain_b[56..42] byteena_b[5..4] datain_b[71..57] byteena_b[7..6] dataout_b[71..60] dataout_b[59..48] dataout_b[47..36] dataout_b[35..24] dataout_b[23..12] dataout_b[11..0] dataout_a[71..60] Output Signals dataout_a[59..48]
f
For more information about TriMatrix memory, refer to the TriMatrix Embedded Memory Blocks in Arria GX Devices chapter.
Digital Signal Processing Block
The most commonly used DSP functions are finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these use the multiplier as the fundamental building block. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Arria GX devices provide DSP blocks to meet the arithmetic requirements of these functions. Each Arria GX device has two to four columns of DSP blocks to efficiently implement DSP functions faster than ALM-based implementations. Each DSP block can be configured to support up to:
■ ■ ■
Eight 9 × 9-bit multipliers Four 18 × 18-bit multipliers One 36 × 36-bit multiplier
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As indicated, the Arria GX DSP block can support one 36 × 36-bit multiplier in a single DSP block and is true for any combination of signed, unsigned, or mixed sign multiplications. Figure 2–50 shows one of the columns with surrounding LAB rows.
Figure 2–50. DSP Blocks Arranged in Columns
DSP Block Column
4 LAB Rows
DSP Block
Table 2–13 lists the number of DSP blocks in each Arria GX device. DSP block multipliers can optionally feed an adder/subtractor or accumulator in the block depending on the configuration, which makes routing to ALMs easier, saves ALM routing resources, and increases performance because all connections and blocks are in the DSP block.
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Table 2–13. DSP Blocks in Arria GX Devices (Note 1) Device EP1AGX20 EP1AGX35 EP1AGX50 EP1AGX60 EP1AGX90
Note to Table 2–13:
(1) This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions.
DSP Blocks 10 14 26 32 44
Total 9 × 9 Multipliers 80 112 208 256 352
Total 18 × 18 Multipliers 40 56 104 128 176
Total 36 × 36 Multipliers 10 14 26 32 44
Additionally, DSP block input registers can efficiently implement shift registers for FIR filter applications. DSP blocks support Q1.15 format rounding and saturation. Figure 2–51 shows a top-level diagram of the DSP block configured for 18 × 18-bit multiplier mode.
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Figure 2–51. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift Register Inputs from Previous DSP Block
Multiplier Stage Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor
D Q
D
Q
Output Selection Multiplexer
ENA CLRN
D
Q
ENA CLRN
ENA CLRN
Adder/ Subtractor/ Accumulator 1
D
Q
ENA CLRN
D
Q
D
Q
ENA CLRN
ENA CLRN
Summation
D
Q
ENA CLRN
D
Q
D
Q
ENA CLRN
Summation Stage for Adding Four Multipliers Together
Optional Output Register Stage
ENA CLRN
Adder/ Subtractor/ Accumulator 2
D
Q
Optional Serial Shift Register Outputs to Next DSP Block in the Column
ENA CLRN
D
Q
D
Q
ENA CLRN
Optional Pipeline Register Stage
ENA CLRN
Optional Input Register Stage with Parallel Input or Shift Register Configuration
to MultiTrack Interconnect
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Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four modes of operation:
■ ■ ■ ■
Simple multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder
Table 2–14 shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, 2D FIR filters, equalizers, IIR, correlators, matrix multiplication, and many other functions. DSP blocks also support mixed modes and mixed multiplier sizes in the same block. For example, half of one DSP block can implement one 18 × 18-bit multiplier in multiply-accumulator mode, while the other half of the DSP block implements four 9 × 9-bit multipliers in simple multiplier mode.
Table 2–14. Multiplier Size and Configurations per DSP Block DSP Block Mode Multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder 9×9 Eight multipliers with eight product outputs — Four two-multiplier adder (two 9 × 9 complex multiply) Two four-multiplier adder 18 × 18 Four multipliers with four product outputs Two 52-bit multiply-accumulate blocks Two two-multiplier adder (one 18 × 18 complex multiply) One four-multiplier adder 36 × 36 One multiplier with one product output — — —
DSP Block Interface
The Arria GX device DSP block input registers can generate a shift register that can cascade down in the same DSP block column. Dedicated connections between DSP blocks provide fast connections between shift register inputs to cascade shift register chains. You can cascade registers within multiple DSP blocks for 9 × 9- or 18 × 18-bit FIR filters larger than four taps, with additional adder stages implemented in ALMs. If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or accumulator stages are implemented in ALMs. Each DSP block can route the shift register chain out of the block to cascade multiple columns of DSP blocks. The DSP block is divided into four block units that interface with four LAB rows on the left and right. Each block unit can be considered one complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local interconnect region is associated with each DSP block. Like an LAB, this interconnect region can be fed with 16 direct link interconnects from the LAB to the left or right of the DSP block in the same row. R4 and C4 routing resources can access the DSP block’s local interconnect region. The outputs also work similarly to LAB outputs. Eighteen outputs from the DSP block can drive to the left LAB through direct link interconnects and 18 can drive to the right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4 routing interconnects. Outputs can drive right- or left-column routing.
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Figure 2–52 and Figure 2–53 show the DSP block interfaces to LAB rows.
Figure 2–52. DSP Block Interconnect Interface
DSP Block
R4, C4 & Direct Link Interconnects
OA[17..0] OB[17..0] A1[17..0] B1[17..0]
R4, C4 & Direct Link Interconnects
OC[17..0] OD[17..0] A2[17..0] B2[17..0]
OE[17..0] OF[17..0]
A3[17..0] B3[17..0]
OG[17..0] OH[17..0]
A4[17..0] B4[17..0]
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Figure 2–53. DSP Block Interface to Interconnect
C4 Interconnect Direct Link Interconnect from Adjacent LAB R4 Interconnect Direct Link Outputs to Adjacent LABs Direct Link Interconnect from Adjacent LAB
36 DSP Block Row Structure
LAB 18
36
LAB
16
16
12 Control 36 A[17..0] B[17..0] OA[17..0] OB[17..0] 36
Row Interface Block DSP Block to LAB Row Interface Block Interconnect Region 36 Inputs per Row 36 Outputs per Row
A bus of 44 control signals feeds the entire DSP block. These signals include clocks, asynchronous clears, clock enables, signed and unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. The clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table 2–15. f For more information about DSP blocks, refer to the DSP Blocks in Arria GX Devices chapter.
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Table 2–15. DSP Block Signal Sources and Destinations LAB Row at Interface Control Signals Generated clock0 aclr0 ena0 mult01_saturate 0 addnsub1_round/ accum_round addnsub1 signa sourcea sourceb clock1 aclr1 ena1 accum_saturate 1 A2[17..0] mult01_round B2[17..0] accum_sload sourcea sourceb mode0 clock2 aclr2 ena2 mult23_saturate 2 addnsub3_round/ accum_round addnsub3 sign_b sourcea sourceb clock3 aclr3 ena3 accum_saturate 3 A4[17..0] mult23_round B4[17..0] accum_sload sourcea sourceb mode1 OH[17..0] OG[17..0] A3[17..0] B3[17..0] OE[17..0] OF[17..0] OD[17..0] OC[17..0] A1[17..0] B1[17..0] OA[17..0] OB[17..0] Data Inputs Data Outputs
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PLLs and Clock Networks
Arria GX devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution.
Global and Hierarchical Clocking
Arria GX devices provide 16 dedicated global clock networks and 32 regional clock networks (eight per device quadrant). These clocks are organized into a hierarchical clock structure that allows for up to 24 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains in Arria GX devices. There are 12 dedicated clock pins (CLK[15..12] and CLK[7..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device except the right side, as shown in Figure 2–54 and Figure 2–55. Internal logic and enhanced and fast PLL outputs can also drive the global and regional clock networks. Each global and regional clock has a clock control block, which controls the selection of the clock source and dynamically enables or disables the clock to reduce power consumption. Table 2–16 lists the global and regional clock features.
Table 2–16. Global and Regional Clock Features Feature Number per device Number available per quadrant Sources Dynamic clock source selection Dynamic enable/disable Global Clocks 16 16 Clock pins, PLL outputs, core routings, inter-transceiver clocks v v Regional Clocks 32 8 Clock pins, PLL outputs, core routings, inter-transceiver clocks — v
Global Clock Network
These clocks drive throughout the entire device, feeding all device quadrants. GCLK networks can be used as clock sources for all resources in the device IOEs, ALMs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2–54 shows the 12 dedicated CLK pins driving global clock networks.
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Figure 2–54. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0]
CLK[7..4]
Regional Clock Network
There are eight RCLK networks (RCLK[7..0]) in each quadrant of the Arria GX device that are driven by the dedicated CLK[15..12]and CLK[7..0] input pins, by PLL outputs, or by internal logic. The regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant. The CLK pins symmetrically drive the RCLK networks in a particular quadrant, as shown in Figure 2–55.
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Figure 2–55. Regional Clocks
CLK[15..12] 11 5 7 RCLK [31..28] RCLK [27..24] Arria GX Transceiver Block
RCLK [3..0] 1 2 RCLK [7..4]
RCLK [23..20]
CLK[3..0]
RCLK [19..16]
Arria GX Transceiver Block
8
RCLK [11..8] 12 6 CLK[7..4]
RCLK [15..12]
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-RCLK by driving two RCLK network lines in adjacent quadrants (one from each quadrant), which allows logic that spans multiple quadrants to use the same low skew clock. The routing of this clock signal on an entire side has approximately the same speed but slightly higher clock skew when compared with a clock signal that drives a single quadrant. Internal logic-array routing can also drive a dual-regional clock. Clock pins and enhanced PLL outputs on the top and bottom can drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on the left and right can drive vertical dual-regional clocks, as shown in Figure 2–56. Corner PLLs cannot drive dual-regional clocks.
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Figure 2–56. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs Can Drive Dual-Regional Network Clock Pins or PLL Clock Outputs Can Drive Dual-Regional Network
CLK[15..12]
CLK[15..12]
CLK[3..0]
CLK[3..0]
PLLs
PLLs
CLK[7..4]
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources consisting of 16 global clock lines and eight regional clock lines. Multiplexers are used with these clocks to form buses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB level to select three of the six row clocks to feed the ALM registers in the LAB (refer to Figure 2–57).
Figure 2–57. Hierarchical Clock Networks Per Quadrant
Clocks Available to a Quadrant or Half-Quadrant Global Clock Network [15..0] Clock [23..0] Lab Row Clock [5..0] Regional Clock Network [7..0] Row I/O Cell IO_CLK[7..0] Column I/O Cell IO_CLK[7..0]
You can use the Quartus II software to control whether a clock input pin drives either a GCLK, RCLK, or dual-RCLK network. The Quartus II software automatically selects the clocking resources if not specified.
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Clock Control Block
Each GCLK, RCLK, and PLL external clock output has its own clock control block. The control block has two functions:
■ ■
Clock source selection (dynamic selection for global clocks) Clock power-down (dynamic clock enable or disable)
Figure 2–58 through Figure 2–60 show the clock control block for the global clock, regional clock, and PLL external clock output, respectively.
Figure 2–58. Global Clock Control Blocks
CLKp Pins PLL Counter Outputs CLKSELECT[1..0] (1) 2 2 CLKn Pin 2 Internal Logic
This multiplexer supports User-Controllable Dynamic Switching
Static Clock Select (2)
Enable/ Disable Internal Logic GCLK
Notes to Figure 2–58:
(1) These clock select signals can be dynamically controlled through internal logic when the device is operating in user mode. (2) These clock select signals can only be set through a configuration file (SRAM Object File [ .sof ] or Programmer Object File [.pof]) and cannot be dynamically controlled during user mode operation.
Figure 2–59. Regional Clock Control Blocks
CLKp Pin PLL Counter Outputs 2 CLKn Pin (2) Internal Logic Static Clock Select (1)
Enable/ Disable Internal Logic RCLK
Notes to Figure 2–59:
(1) These clock select signals can only be set through a configuration file ( .sof or .pof ) and cannot be dynamically controlled during user mode operation. (2) Only the CLKn pins on the top and bottom of the device feed to regional clock select.
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Figure 2–60. External PLL Output Clock Control Blocks
PLL Counter Outputs (c[5..0]) 6 Static Clock Select (1)
Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1)
PLL_OUT Pin
Notes to Figure 2–60:
(1) These clock select signals can only be set through a configuration file ( .sof or .pof ) and cannot be dynamically controlled during user mode operation. (2) The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.
For the global clock control block, clock source selection can be controlled either statically or dynamically. You have the option of statically selecting the clock source by using the Quartus II software to set specific configuration bits in the configuration file (.sof or .pof) or controlling the selection dynamically by using internal logic to drive the multiplexer select inputs. When selecting statically, the clock source can be set to any of the inputs to the select multiplexer. When selecting the clock source dynamically, you can either select between two PLL outputs (such as the C0 or C1 outputs from one PLL), between two PLLs (such as the C0/C1 clock output of one PLL or the C0/C1 c1ock output of the other PLL), between two clock pins (such as CLK0 or CLK1), or between a combination of clock pins or PLL outputs. For the regional and PLL_OUT clock control block, clock source selection can only be controlled statically using configuration bits. Any of the inputs to the clock select multiplexer can be set as the clock source. Arria GX clock networks can be disabled (powered down) by both static and dynamic approaches. When a clock net is powered down, all logic fed by the clock net is in an off-state thereby reducing the overall power consumption of the device. GCLK and RCLK networks can be powered down statically through a setting in the configuration file (.sof or .pof). Clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by the Quartus II software. The dynamic clock enable or disable feature allows the internal logic to control power up/down synchronously on GCLK and RCLK nets and PLL_OUT pins. This function is independent of the PLL and is applied directly on the clock network or PLL_OUT pin, as shown in Figure 2–58 through Figure 2–60.
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Enhanced and Fast PLLs
Arria GX devices provide robust clock management and synthesis using up to four enhanced PLLs and four fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clock frequency synthesis. With features such as clock switchover, spread spectrum clocking, reconfigurable bandwidth, phase control, and reconfigurable phase shifting, the Arria GX device’s enhanced PLLs provide you with complete control of your clocks and system timing. The fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the Arria GX high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth. The Quartus II software enables the PLLs and their features without requiring any external devices. Table 2–17 lists the PLLs available for each Arria GX device and their type.
Table 2–17. Arria GX Device PLL Availability (Note 1) , ( 2) Fast PLLs Device 1 EP1AGX20 EP1AGX35 EP1AGX50 ( 4) EP1AGX60 (5) EP1AGX90
Notes to Table 2–17:
(1) The global or regional clocks in a fast PLL's transceiver block can drive the fast PLL input. A pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. (2) EP1AGX20C, EP1AGX35C/D, EP1AGX50C and EP1AGX60C/D devices only have two fast PLLs (PLLs 1 and 2), but the connectivity from these two PLLs to the global and regional clock networks remains the same as shown in this table. (3) PLLs 3, 4, 9, and 10 are not available in Arria GX devices. (4) 4 or 8 PLLs are available depending on C or D device and the package option. (5) 4or 8 PLLs are available depending on C, D, or E device option.
Enhanced PLLs 8 — —
v v v
2
v v v v v
3 (3) — — — — —
4 ( 3) — — — — —
7 — —
v v v
9 ( 3) — — — — —
10 ( 3) — — — — —
5
v v v v v
6
v v v v v
11 — —
v v v
12 — —
v v v
v v v v v
Table 2–18 lists the enhanced PLL and fast PLL features in Arria GX devices.
Table 2–18. Arria GX PLL Features (Part 1 of 2) Feature Clock multiplication and division Phase shift Clock switchover PLL reconfiguration Reconfigurable bandwidth Spread spectrum clocking Programmable duty cycle Number of internal clock outputs Number of external clock outputs Enhanced PLL m/( n × post-scale counter) ( 1) Down to 125-ps increments (3), ( 4) v v v v v 6 Three differential/six single-ended Fast PLL m/(n × post-scale counter) (2) Down to 125-ps increments ( 3), (4) v (5) v v — v 4 (6)
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Table 2–18. Arria GX PLL Features (Part 2 of 2) Feature Number of feedback clock inputs
Notes to Table 2–18:
(1) (2) (3) (4) (5) (6) (7) (8) For enhanced PLLs, m, n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle. For fast PLLs, m , and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4. The smallest phase shift is determined by the voltage controlled oscillator (VCO ) period divided by 8. For degree increments, Arria GX devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters. Arria GX fast PLLs only support manual clock switchover. Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. If the feedback input is used, you lose one (or two, if fBIN is differential) external clock output pin. Every Arria GX device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Enhanced PLL One single-ended or differential (7) , (8)
Fast PLL —
Figure 2–61 shows a top-level diagram of the Arria GX device and PLL floorplan.
Figure 2–61. PLL Locations
CLK[15..12] 11 5
FPLL7CLK
7
CLK[3..0]
1 2
PLLs
FPLL8CLK
8
12
6
CLK[7..4]
Figure 2–62 and Figure 2–63 shows global and regional clocking from the fast PLL outputs and side clock pins. The connections to the global and regional clocks from the fast PLL outputs, internal drivers, and CLK pins on the left side of the device are shown in Table 2–19.
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Figure 2–62. Global and Regional Clock Connections from Center Clock Pins and Fast PLL Outputs (Note 1)
CLK0 CLK1 Fast PLL 1
C0 C1 C2 C3
Logic Array Signal Input To Clock Network
C0 CLK2 CLK3 Fast PLL 2 C1 C2 C3
RCLK0 RCLK1
RCLK2
RCLK4 RCLK5
RCLK6 RCLK7
GCLK0 GCLK1
GCLK2 GCLK3
RCLK3
Note to Figure 2–62:
(1) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
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Figure 2–63. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs
RCLK1 RCLK0 RCLK3 RCLK2
(Note 1)
C0 Fast PLL 7 C1 C2 C3
C0 Fast PLL 8 C1 C2 C3
RCLK4 RCLK5
RCLK6 RCLK7
GCLK0 GCLK1
GCLK2 GCLK3
Note to Figure 2–63:
(1) The GCLK or RCLK in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 1 of 2) RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 — — v — — — — — — — v — — — v CLK0 CLK1 CLK2 CLK3 Left Side Global & Regional Clock Network Connectivity Clock Pins CLK0p CLK1p CLK2p CLK3p Drivers from Internal Logic GCLKDRV0 GCLKDRV1 GCLKDRV2 GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 v v — — — — — — — — — v v — — — — — — — — — — — v v — — — — — — — — — v v — — — — — — — — — — — v — — — v — — — — — — — v — — — v — — — — — — — v — — — v — — — — — — — v — — — — — — — v — — — v — — — — — — — v — — — v — — — — — — — — v — — — v v — — v v — — — — v v — — v v v — — — — v — — — — v — — — — v v — — — — v — — — — — v RCLK7
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Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 2 of 2) RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 — v — v — — v — v — — — — v — v — CLK0 CLK1 CLK2 CLK3 Left Side Global & Regional Clock Network Connectivity RCLKDRV7 PLL 1 Outputs c0 c1 c2 c3 PLL 2 Outputs c0 c1 c2 c3 PLL 7 Outputs c0 c1 c2 c3 PLL 8 Outputs c0 c1 c2 c3 — — v v — — v v v v — — v v — — — — — — — — — — — — — — — — — — v — v — — v — v — v — v — — v v — — v v v v — — v v — — — v — v v — v — — v — v v — v — — — — — — — — — — — — — v v — — v v — — — — v v — — v v — v — v v — v — — v — v v — v — — v — v v — v — v — v — v v — — v v — — — — v v — — v v v — v — — v — v v — v — — v — v v — v — v — v — v — v RCLK7 v
—
—
—
—
—
—
—
v
—
—
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Figure 2–64 shows the global and regional clocking from enhanced PLL outputs and top and bottom CLK pins.
Figure 2–64. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL Outputs ( Note 1)
CLK13 CLK12 CLK15 CLK14
PLL11_FB
PLL5_FB
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5
PLL11_OUT[2..0]p PLL11_OUT[2..0]n
c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p PLL5_OUT[2..0]n RCLK31 RCLK30 RCLK29 RCLK28
Regional Clocks
RCLK27 RCLK26 RCLK25 RCLK24 G15 G14 G13 G12
Global Clocks
G4 G5 G6 G7
Regional Clocks
RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 PLL6_OUT[2..0]p PLL6_OUT[2..0]n
PLL12_OUT[2..0]p PLL12_OUT[2..0]n
c0 c1 c2 c3 c4 c5 PLL 12
c0 c1 c2 c3 c4 c5
PLL 6
PLL12_FB CLK4 CLK5 CLK6 CLK7
PLL6_FB
Note to Figure 2–64:
(1) If the design uses the feedback input, you might lose one (or two if FBIN is differential) external clock output pin.
The connections to the global and regional clocks from the top clock pins and enhanced PLL outputs are shown in Table 2–20. The connections to the clocks from the bottom clock pins are shown in Table 2–21.
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Table 2–20. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs RCLK24 RCLK25 RCLK26 RCLK27 RCLK28 RCLK29 RCLK30 — — v — — — v — — — — — — — v — — — v — — — v — v — — — v — v — RCLK31 — — — v — — — v — — — — — — — v — — — v — — — v — v — — — v — v DLLCLK CLK12 CLK13 CLK14 CLK15 Top Side Global and Regional Clock Network Connectivity Clock pins CLK12p CLK13p CLK14p CLK15p CLK12n CLK13n CLK14n CLK15n Drivers from internal logic GCLKDRV0 GCLKDRV1 GCLKDRV2 GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 RCLKDRV7 Enhanced PLL5 outputs c0 c1 c2 c3 c4 c5 Enhanced PLL 11 outputs c0 c1 c2 c3 c4 c5 — — — — — — v v — — — — v v — — — — — — v v — — — — v v — — v — — — v — — v — — — v — — v — v — — — — v — v v — — — v — — v — — — v v v v v v v v v — — — — v v — — — — — — v v — — — — v v — — v — — — v — — v — — — v — — v — v — — — — v — v v — — — v — — v — — — v — — — — — — — — — — — — v — — — — — — — — — — — — v — — — — — — — — — — — — v — — — — — — — — — — — — v — — — — — — — — — — — — v — — — v — — — — — — — — v — — — v — — — — — — — — v — — — v — — — — — — — — v — — — v — — — — v — — — v — — — — — — — — v — — — v — — v v v v — — — — v v — — v — — — v v — — — v — — — — v v — — v — — — v v — — — v v — — — v — — — — v — — — v — — — — v — — — v — — — — v — — — v v — — — v — — — — v — — — v — —
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Table 2–21. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 — — v — — — v — — — — — — — v — — — v — — — v — — v — v — v — v — — v — v — RCLK15 — — — v — — — v — — — — — — — v — — — v — — — — — v — v DLLCLK RCLK8 v — — — v — — — RCLK9 CLK4 CLK5 CLK6 CLK7 Bottom Side Global and Regional Clock Network Connectivity Clock pins CLK4p CLK5p CLK6p CLK7p CLK4n CLK5n CLK6n CLK7n Drivers from internal logic GCLKDRV0 GCLKDRV1 GCLKDRV2 GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 RCLKDRV7 Enhanced PLL 6 outputs c0 c1 c2 c3 c4 c5 Enhanced PLL 12 outputs c0 c1 c2 c3 c4 c5 — — — — — — v v — — — — v v — — — — — — v v — — — — v v — — v — — — v — — v — — — v — — v — v — — — — v — v v — — — v — — v — — — v v v v v v v v v — — — — v v — — — — — — v v — — — — v v — — v — — — v — — v — — — v — — v — v — — — — v — v v — — — v — — v — — — — — — — — — — — — v — — — — — — — — — — — — v — — — — — — — — — — — — v — — — — — — — — — — — — v — — — — — — — — — — — — v — — — v — — — — — — — — v — — — v — — — — — — — — v — — — v — — — — — — — — v — — — v — — — — v — — — v — — — — — — — — v — — — v — — v v v v — — — — v v — — v — — — v v — — — v — — — — v v — — v — — — v v — — — v — v — — — v — — — — v — — — v — — — — v — — — v v — — — v — — — — v — — — v — —
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Chapter 2: Arria GX Architecture PLLs and Clock Networks
Enhanced PLLs
Arria GX devices contain up to four enhanced PLLs with advanced clock management features. These features include support for external clock feedback mode, spread-spectrum clocking, and counter cascading. Figure 2–65 shows a diagram of the enhanced PLL.
Figure 2–65. Arria GX Enhanced PLL (Note 1)
VCO Phase Selection Selectable at Each PLL Output Port From Adjacent PLL Post-Scale Counters
Clock Switchover Circuitry INCLK[3..0] 4 /n
Phase Frequency Detector
Spread Spectrum
/c0
/c1 4 PFD Charge Pump Loop Filter 8 VCO /c2 6 /c3 6 /m (2) /c5 FBIN Lock Detect & Filter to I/O or general routing /c4 I/O Buffers (3) 8 Regional Clocks Global Clocks
Global or Regional Clock
Shaded Portions of the PLL are Reconfigurable
VCO Phase Selection Affecting All Outputs
Notes to Figure 2–65:
(1) (2) (3) (4) Each clock source can come from any of the four clock pins that are physically located on the same side of the device as the PLL. If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin. Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs. The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Fast PLLs
Arria GX devices contain up to four fast PLLs with high-speed serial interfacing ability. Fast PLLs offer high-speed outputs to manage the high-speed differential I/O interfaces. Figure 2–66 shows a diagram of the fast PLL.
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Figure 2–66. Arria GX Device Fast PLL
VCO Phase Selection Selectable at each PLL Output Port Post-Scale Counters
Global or regional clock (1)
Clock Switchover Circuitry (4)
Phase Frequency Detector
diffioclk0 (2) ÷c0 8 ÷c1 4 ÷c2 Global clocks 4 ÷c3 ÷m 8 to DPA block 8 Regional clocks load_en0 (3)
Clock Input
4
÷n
PFD
Charge Pump
Loop Filter
VCO
÷k
load_en1 (3) diffioclk1 (2)
Global or regional clock (1)
Shaded Portions of the PLL are Reconfigurable
Notes to Figure 2–66:
(1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL. (2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES) circuitry. Arria GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode. (3) This signal is a differential I/O SERDES control signal. (4) Arria GX fast PLLs only support manual clock switchover.
f
For more information about enhanced and fast PLLs, refer to the PLLs in Arria GX Devices chapter. For more information about high-speed differential I/O support, refer to “High-Speed Differential I/O with DPA Support” on page 2–99.
I/O Structure
Arria GX IOEs provide many features, including:
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
Dedicated differential and single-ended I/O buffers 3.3-V, 64-bit, 66-MHz PCI compliance 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance JTAG boundary-scan test (BST) support On-chip driver series termination OCT for differential standards Programmable pull-up during configuration Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins DDR registers
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Chapter 2: Arria GX Architecture I/O Structure
The IOE in Arria GX devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR transfer. Figure 2–67 shows the Arria GX IOE structure. The IOE contains two input registers (plus a latch), two output registers, and two output enable registers. The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs. Additionally, the design can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins.
Figure 2–67. Arria GX IOE Structure
Logic Array OE Register OE
D Q
OE Register
D Q
Output Register Output A
D Q
CLK
Output Register Output B
D Q
Input Register
D Q
Input A Input B Input Register
D Q
Input Latch
D Q ENA
The IOEs are located in I/O blocks around the periphery of the Arria GX device. There are up to four IOEs per row I/O block and four IOEs per column I/O block. Row I/O blocks drive row, column, or direct link interconnects. Column I/O blocks drive column interconnects.
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Figure 2–68 shows how a row I/O block connects to the logic array.
Figure 2–68. Row I/O Block Connection to the Interconnect
R4 & R24 Interconnects
C4 Interconnect I/O Block Local Interconnect
32 Data & Control Signals from Logic Array (1) 32 Horizontal I/O Block
LAB
io_dataina[3..0] io_datainb[3..0]
Direct Link Interconnect to Adjacent LAB LAB Local Interconnect
Direct Link Interconnect to Adjacent LAB io_clk[7:0]
Horizontal I/O Block Contains up to Four IOEs
Note to Figure 2–68:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0].
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Figure 2–69 shows how a column I/O block connects to the logic array.
Figure 2–69. Column I/O Block Connection to the Interconnect
32 Data & Control Signals from Logic Array (1)
Vertical I/O Block
Vertical I/O Block Contains up to Four IOEs
32
IO_dataina[3..0] IO_datainb[3..0]
io_clk[7..0]
I/O Block Local Interconnect
R4 & R24 Interconnects
LAB
LAB
LAB
LAB Local Interconnect
C4 & C16 Interconnects
Note to Figure 2–69:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0] .
There are 32 control and data signals that feed each row or column I/O block. These control and data signals are driven from the logic array. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from global or regional clocks (refer to “PLLs and Clock Networks” on page 2–66).
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Figure 2–70 shows the signal paths through the I/O block.
Figure 2–70. Signal Path Through the I/O Block
Row or Column io_clk[7..0] To Other IOEs
To Logic Array
io_dataina io_datainb oe ce_in ce_out io_ce_in io_ce_out io_aclr Control Signal Selection aclr/apreset sclr/spreset clk_in io_sclr clk_out io_clk io_dataouta io_dataoutb IOE
io_oe
From Logic Array
Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset , clk_in, and clk_out. Figure 2–71 shows the control signal selection.
Figure 2–71. Control Signal Selection per IOE (Note 1)
Dedicated I/O Clock [7..0] Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect io_oe
io_sclr
io_aclr
io_ce_out
io_ce_in
io_clk
clk_out
ce_out
sclr/spreset
clk_in
ce_in
aclr/apreset
oe
Notes to Figure 2–71:
(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive the I/O local interconnect, which then drives the control selection multiplexers.
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In normal bidirectional operation, you can use the input register for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. You can use the OE register for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from the local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. Figure 2–72 shows the IOE in bidirectional configuration.
Figure 2–72. Arria GX IOE in Bidirectional I/O Configuration (Note 1)
ioe_clk[7..0] Column, Row, or Local Interconnect
oe OE Register
D Q
clkout
ENA CLRN/PRN OE Register tCO Delay VCCIO
ce_out
PCI Clamp (2)
VCCIO
aclr/apreset Chip-Wide Reset Output Register
D Q
Programmable Pull-Up Resistor
Output Pin Delay
On-Chip Termination
sclr/spreset
Drive Strength Control ENA Open-Drain Output CLRN/PRN Input Pin to Logic Array Delay
Input Pin to Input Register Delay
Input Register clkin
D Q
Bus-Hold Circuit
ce_in
ENA CLRN/PRN
Notes to Figure 2–72:
(1) All input signals to the IOE can be inverted at the IOE. (2) The optional PCI clamp is only available on column I/O pins.
The Arria GX device IOE includes programmable delays that can be activated to ensure input IOE register-to-logic array register transfers, input pin-to-logic array register transfers, or output IOE register-to-pin transfers.
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A path in which a pin directly drives a register can require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinational logic may not require the delay. Programmable delays exist for decreasing input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output and/or output enable registers. Programmable delays are no longer required to ensure zero hold times for logic array register-to-IOE register transfers. The Quartus II Compiler can create zero hold time for these transfers. Table 2–22 shows the programmable delays for Arria GX devices.
Table 2–22. Arria GX Devices Programmable Delay Chain Programmable Delays Input pin to logic array delay Input pin to input register delay Output pin delay Output enable register t CO delay Quartus II Logic Option Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin Delay to output enable pin
IOE registers in Arria GX devices share the same source for clear or preset. You can program preset or clear for each individual IOE. You can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device’s active-low input upon power-up. If one register in an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available for the IOE registers.
Double Data Rate I/O Pins
Arria GX devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Arria GX devices support DDR inputs, DDR outputs, and bidirectional DDR modes. When using the IOE for DDR inputs, the two input registers clock double rate input data on alternating edges. An input latch is also used in the IOE for DDR input acquisition. The latch holds the data that is present during the clock high times, allowing both bits of data to be synchronous with the same clock edge (either rising or falling). Figure 2–73 shows an IOE configured for DDR input. Figure 2–74 shows the DDR input timing diagram.
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Figure 2–73. Arria GX IOE in DDR Input I/O Configuration
ioe_clk[7..0] Column, Row, or Local Interconnect
(Note 1)
VCCIO To DQS Logic Block (3) PCI Clamp (4) VCCIO
DQS Local Bus (2)
Programmable Pull-Up Resistor
Input Pin to Input RegisterDelay sclr/spreset Input Register
D Q
On-Chip Termination
clkin ce_in aclr/apreset
ENA CLRN/PRN
Bus-Hold Circuit
Chip-Wide Reset Input Register
D Q D
Latch
Q
ENA CLRN/PRN
ENA CLRN/PRN
Notes to Figure 2–73:
(1) (2) (3) (4) All input signals to the IOE can be inverted at the IOE. This signal connection is only allowed on dedicated DQ function pins. This signal is for dedicated DQS function pins only. The optional PCI clamp is only available on column I/O pins.
Figure 2–74. Input Timing Diagram in DDR Mode
Data at input pin B0 A0 B1 A1 B2 A2 B3 A3 B4
CLK
A0 Input To Logic Array B0
A1
A2
A3
B1
B2
B3
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When using the IOE for DDR outputs, the two output registers are configured to clock two data paths from ALMs on rising clock edges. These output registers are multiplexed by the clock to drive the output pin at a ×2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. Figure 2–75 shows the IOE configured for DDR output. Figure 2–76 shows the DDR output timing diagram.
Figure 2–75. Arria GX IOE in DDR Output I/O Configuration Notes ( 1), (2)
ioe_clk[7..0] Column, Row, or Local Interconnect
oe OE Register
D Q
clkout
ENA CLRN/PRN
ce_out
OE Register tCO Delay
aclr/apreset
VCCIO PCI Clamp (3) Chip-Wide Reset OE Register
D Q
VCCIO Used for DDR, DDR2 SDRAM
sclr/spreset
ENA CLRN/PRN
Programmable Pull-Up Resistor
Output Register
D Q
Output Pin Delay clk Drive Strength Control Open-Drain Output
On-Chip Termination
ENA CLRN/PRN
Output Register
D Q
ENA CLRN/PRN
Bus-Hold Circuit
Notes to Figure 2–75:
(1) All input signals to the IOE can be inverted at the IOE. (2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an inverter at the OE register data port. (3) The optional PCI clamp is only available on column I/O pins.
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Figure 2–76. Output Timing Diagram in DDR Mode
CLK
A1 From Internal Registers B1
A2
A3
A4
B2
B3
B4
DDR output
B1
A1
B2
A2
B3
A3
B4
A4
The Arria GX IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Arria GX devices also have dedicated phase-shift circuitry for interfacing with external memory interfaces, including DDR, DDR2 SDRAM, and SDR SDRAM. In every Arria GX device, the I/O banks at the top (Banks 3 and 4) and bottom (Banks 7 and 8) of the device support DQ and DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–23 shows the number of DQ and DQS buses that are supported per device.
Table 2–23. DQS and DQ Bus Mode Support (Note 1) Device EP1AGX20 EP1AGX35 Package 484-pin FineLine BGA 484-pin FineLine BGA 780-pin FineLine BGA 484-pin FineLine BGA EP1AGX50/60 780-pin FineLine BGA 1,152-pin FineLine BGA EP1AGX90
Note to Table 2–23:
(1) Numbers are preliminary until devices are available.
Number of ×4 Groups 2 2 18 2 18 36 36
Number of ×8/×9 Groups 0 0 8 0 8 18 18
Number of ×16/×18 Groups 0 0 4 0 4 8 8
Number of ×32/×36 Groups 0 0 0 0 0 4 4
1,152-pin FineLine BGA
A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal.
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The Arria GX device has two phase-shifting reference circuits, one on the top and one on the bottom of the device. The circuit on the top controls the compensated delay elements for all DQS pins on the top. The circuit on the bottom controls the compensated delay elements for all DQS pins on the bottom. Each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequency as the DQS signal. Clock pins CLK[15..12]p feed phase circuitry on the top of the device and clock pins CLK[7..4]p feed phase circuitry on the bottom of the device. In addition, PLL clock outputs can also feed the phase-shifting reference circuits. Figure 2–77 shows the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device.
Figure 2–77. DQS Phase-Shift Circuitry (Note 1) , (2)
From PLL 5 (4) DQS Pin DQS Pin CLK[15..12]p (3) DQS Pin DQS Pin
Dt
Dt
DQS Phase-Shift Circuitry
Dt
Dt
to IOE
to IOE
to IOE
to IOE
Notes to Figure 2–77:
(1) There are up to 18 pairs of DQS pins available on the top or bottom of the Arria GX device. There are up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry. (2) The “t” module represents the DQS logic block. (3) Clock pins CLK[15..12]p f eed phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to phase shift circuitry. (4) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS phase-shift circuitry on the bottom of the device.
These dedicated circuits combined with enhanced PLL clocking and phase-shift ability provide a complete hardware solution for interfacing to high-speed memory. f For more information about external memory interfaces, refer to the External Memory Interfaces in Arria GX Devices chapter.
Programmable Drive Strength
The output buffer for each Arria GX device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL, LVCMOS, SSTL, and HSTL standards have several levels of drive strength that you can control. The default setting used in the Quartus II software is the maximum current strength setting that is used to achieve maximum I/O performance. For all I/O standards, the minimum setting is the lowest drive strength that guarantees the IOH/IOL of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot.
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Table 2–24 shows the possible settings for I/O standards with drive strength control.
Table 2–24. Programmable Drive Strength (Note 1) I/O Standard 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II
Note to Table 2–24:
(1) The Quartus II software default current setting is the maximum setting for each I/O standard.
I OH / IOL Current Strength Setting (mA) for Column I/O Pins 24, 20, 16, 12, 8, 4 24, 20, 16, 12, 8, 4 16, 12, 8, 4 12, 10, 8, 6, 4, 2 8, 6, 4, 2 12, 8 24, 20, 16 12, 10, 8, 6, 4 20, 18, 16, 8 12, 10, 8, 6, 4 20, 18, 16 12, 10, 8, 6, 4 20, 18, 16
IOH / IOL Current Strength Setting (mA) for Row I/O Pins 12, 8, 4 8, 4 12, 8, 4 8, 6, 4, 2 4, 2 12, 8 16 10, 8, 6, 4 — 12, 10, 8, 6, 4 — 8, 6, 4 —
Open-Drain Output
Arria GX devices provide an optional open-drain (equivalent to an open collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (for example, interrupt and write enable signals) that can be asserted by any of several devices.
Bus Hold
Each Arria GX device I/O pin provides an optional bus-hold feature. Bus-hold circuitry can hold the signal on an I/O pin at its last-driven state. Because the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated. Bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output drives no higher than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when the I/O pin has been configured for differential signals. Bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 k to pull the signal level to the last-driven state. This information is provided for each VCCIO voltage level. Bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration.
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f
For the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level, refer to the DC & Switching Characteristics chapter.
Programmable Pull-Up Resistor
Each Arria GX device I/O pin provides an optional programmable pull-up resistor during user mode. If you enable this feature for an I/O pin, the pull-up resistor (typically 25 k ) holds the output to the VCCIO level of the output pin’s bank.
Advanced I/O Standard Support
Arria GX device IOEs support the following I/O standards:
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL (on input and output clocks only) Differential 1.5-V HSTL class I and II Differential 1.8-V HSTL class I and II Differential SSTL-18 class I and II Differential SSTL-2 class I and II 1.2-V HSTL class I and II 1.5-V HSTL class I and II 1.8-V HSTL class I and II SSTL-2 class I and II SSTL-18 class I and II
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Table 2–25 describes the I/O standards supported by Arria GX devices.
Table 2–25. Arria GX Devices Supported I/O Standards I /O Standard LVTTL LVCMOS 2.5 V 1.8 V 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL (1) HyperTransport technology Type Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Differential Differential Differential Input Reference Voltage (VREF ) (V) — — — — — — — — — — 0.75 0.90 0.90 1.25 0.6 0.75 0.9 0.90 1.25 Output Supply Voltage (VCCIO ) (V) 3.3 3.3 2.5 1.8 1.5 3.3 3.3 2.5 (3) 3.3 2.5 (3) 1.5 1.8 1.8 2.5 1.2 1.5 1.8 1.8 2.5 Board Termination Voltage (VTT ) (V) — — — — — — — — — — 0.75 0.90 0.90 1.25 0.6 0.75 0.9 0.90 1.25
Differential 1.5-V HSTL class I and II (2) Differential Differential 1.8-V HSTL class I and II (2) Differential Differential SSTL-18 class I and II (2) Differential SSTL-2 class I and II ( 2) 1.2-V HSTL (4) 1.5-V HSTL class I and II 1.8-V HSTL class I and II SSTL-18 class I and II SSTL-2 class I and II
Notes to Table 2–25:
Differential Differential Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced
(1) This I/O standard is only available on input and output column clock pins. (2) This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock pins in I/O banks 9, 10, 11, and 12. (3) VCCIO is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 3, 4, 7, 8, 9, 10, 11, and 12). (4) 1.2-V HSTL is only supported in I/O banks 4, 7, and 8.
f
For more information about the I/O standards supported by Arria GX I/O banks, refer to the Selectable I/O Standards in Arria GX Devices chapter. Arria GX devices contain six I/O banks and four enhanced PLL external clock output banks, as shown in Figure 2–78. The two I/O banks on the left of the device contain circuitry to support source-synchronous, high-speed differential I/O for LVDS inputs and outputs. These banks support all Arria GX I/O standards except PCI or PCI-X I/O pins, and SSTL-18 class II and HSTL outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, enhanced PLL external clock output banks allow clock output capabilities such as differential support for SSTL and HSTL.
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Figure 2–78. Arria GX I/O Banks
DQS ×8 PLL7
VREF3B2 VREF4B2
(Note 1), (2)
DQS ×8
DQS ×8
DQS ×8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3 Bank 3
PLL11
Bank 11
PLL5
Bank 9
DQS ×8
DQS ×8
DQS ×8 Bank 4
DQS ×8
DQS ×8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
VREF0B2 VREF1B2
This I/O bank supports LVDS and LVPECL standards for input clock operations. Differential HSTL and differential SSTL standards are supported for both input and output operations. (3) I/O Banks 3, 4, 9, and 11 support all single-ended I/O standards for both input and output operations. All differential I/O standards are supported for both input and output operations at I/O banks 9 and 11.
VREF2B2
Bank 2
This I/O bank supports LVDS and LVPECL standards for input clock operation. Differential HSTL and differential SSTL standards are supported for both input and output operations. (3)
Transmitter: Bank 13 Receiver: Bank 13 REFCLK: Bank 13
PLL1
PLL2
VREF3B1 VREF4B1
I/O banks 1 & 2 support LVTTL, LVCMOS, 2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I, LVDS, pseudo-differential SSTL-2 and pseudo-differential SSTL-18 class I standards for both input and output operations. HSTL, SSTL-18 class II, pseudo-differential HSTL and pseudo-differential SSTL-18 class II standards are only supported for input operations. (4)
Transmitter: Bank 14 Receiver: Bank 14 REFCLK: Bank 14
VREF0B1 VREF1B1
I/O banks 7, 8, 10 and 12 support all single-ended I/O standards for both input and output operations. All differential I/O standards are supported for both input and output operations at I/O banks 10 and 12. This I/O bank supports LVDS This I/O bank supports LVDS and LVPECL standards for input clock operation. and LVPECL standards for input clock Differential HSTL and differential operation. Differential HSTL and differential SSTL standards are supported SSTL standards are supported for both input and output operations. (3) for both input and output operations. (3)
VREF2B1
Bank 1
Transmitter: Bank 15 Receiver: Bank 15 REFCLK: Bank 15
Bank 8 PLL8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8 DQS ×8 DQS ×8 DQS ×8 DQS ×8
Bank 12
Bank 10
Bank 7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7 DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8
PLL12
PLL6
Notes to Figure 2–78:
(1) Figure 2–78 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only. (2) Depending on the size of the device, different device members have different numbers of VREF groups. For the exact locations, refer to the pin list and the Quartus II software. (3) Banks 9 through 12 are enhanced PLL external clock output banks. (4) Horizontal I/O banks feature SERDES and DPA circuitry for high-speed differential I/O standards. For more information about differential I/O standards, refer to the High-Speed Differ ential I/O Inter faces in Arria GX Device s chapter.
Each I/O bank has its own VCCIO pins. A single device can support 1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different VCCIO level independently. Each bank also has dedicated VREF pins to support the voltage-referenced standards (such as SSTL-2). Each I/O bank can support multiple standards with the same VCCIO for input and output pins. Each bank can support one VREF v oltage level. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs.
On-Chip Termination
Arria GX devices provide differential (for the LVDS technology I/O standard) and on-chip series termination to reduce reflections and maintain signal integrity. There is no calibration support for these on-chip termination resistors. On-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections.
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Arria GX devices provide two types of termination:
■ ■
On-chip differential termination (R D OCT) On-chip series termination (RS OCT)
Table 2–26 lists the Arria GX OCT support per I/O bank.
Table 2–26. On-Chip Termination Support by I/O Banks On-Chip Termination Support I/O Standard Support 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVTTL Series termination 1.5-V LVCMOS SSTL-2 class I and II SSTL-18 class I SSTL-18 class II 1.8-V HSTL class I 1.8-V HSTL class II 1.5-V HSTL class I 1.2-V HSTL LVDS Differential termination ( 1)
Note to Table 2–26:
(1) Clock pins CLK1 and CLK3, and pins FPLL[7..8]CLK do not support differential on-chip termination. Clock pins CLK0 and CLK2, do support differential on-chip termination. Clock pins in the top and bottom banks ( CLK[4..7, 12..15]) do not support differential on-chip termination.
Top and Bottom Banks (3, 4, 7, 8) v v v v v v v v v v v v v v v — —
Left Bank (1, 2) v v v v v v v v v v — v — v — v v
HyperTransport technology
On-Chip Differential Termination (RD OCT)
Arria GX devices support internal differential termination with a nominal resistance value of 100 for LVDS input receiver buffers. LVPECL input signals (supported on clock pins only) require an external termination resistor. RD OCT is supported across the full range of supported differential data rates as shown in the High-Speed I/O Specifications section of the DC & Switching Characteristics chapter. f f For more information about RD OCT, refer to the High-Speed Differential I/O Interfaces with DPA in Arria GX Devices chapter. For more information about tolerance specifications for R D OCT, refer to the DC & Switching Characteristics chapter.
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On-Chip Series Termination (R S O CT)
Arria GX devices support driver impedance matching to provide the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, reflections can be significantly reduced. Arria GX devices support RS OCT for single-ended I/O standards with typical R S values of 25 and 50 Once matching impedance is selected, current drive strength is no longer selectable. Table 2–26 shows the list of output standards that support RS OCT. f f For more information about RS OCT supported by Arria GX devices, refer to the Selectable I/O Standards in Arria GX Devices chapter. For more information about tolerance specifications for OCT without calibration, refer to the DC & Switching Characteristics chapter.
MultiVolt I/O Interface
The Arria GX architecture supports the MultiVolt I/O interface feature that allows Arria GX devices in all packages to interface with systems of different supply voltages. Arria GX VCCINT pins must always be connected to a 1.2-V power supply. With a 1.2-V VCCINT level, input pins are 1.2-, 1.5-, 1.8-, 2.5-, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.2-, 1.5-, 1.8-, 2.5-, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (for example, when VCCIO p ins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). Arria GX VCCPD power pins must be connected to a 3.3-V power supply. These power pins are used to supply the pre-driver power to the output buffers, which increases the performance of the output pins. The VCCPD pins also power configuration input pins and JTAG input pins. Table 2–27 lists Arria GX MultiVolt I/O support.
Table 2–27. Arria GX MultiVolt I/O Support VCCIO (V) 1.2 1.5 1.8 2.5 3.3 (Note 1) Output Signal (V) 2.5 v (2) v (2) v (2) v v 3.3 v (2) v (2) v (2) v v 1.2 v (4) v ( 3) v (3) v ( 3) v ( 3) 1.5 — v v ( 3) v ( 3) v (3) 1.8 — — v v (3) v (3) 2.5 — — — v v (3) 3.3 — — — — v 5.0 — — — — v
Input Signal (V) 1.2 (4) (4) (4) (4) (4) 1.5 v (2) v v — — 1.8 v ( 2) v v — —
Notes to Table 2–27:
(1) To drive inputs higher than VC C IO but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL and LVCMOS input levels to overdrive input buffer option in the Quartus II software. (2) The pin current may be slightly higher than the default value. You must verify that the driving device’s VO L maximum and VO H minimum voltages do not violate the applicable Arria GX V I L m aximum and V I H m inimum voltage specifications. (3) Although VCC I O specifies the voltage necessary for the Arria GX device to drive out, a receiving device powered at a different level can still interface with the Arria GX device if it has inputs that tolerate the VC C I O value. (4) Arria GX devices support 1.2-V HSTL. They do not support 1.2-V LVTTL and 1.2-V LVCMOS.
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The TDO and nCEO pins are powered by VCCIO of the bank that they reside. TDO is in I/O bank 4 and nCEO is in I/O Bank 7. Ideally, the VCC supplies for the I/O buffers of any two connected pins are at the same voltage level. This may not always be possible depending on the VCCIO level of TDO and nCEO pins on master devices and the configuration voltage level chosen by VCCSEL on slave devices. Master and slave devices can be in any position in the chain. The master device indicates that it is driving out TDO or nCEO to a slave device. For multi-device passive configuration schemes, the nCEO pin of the master device drives the nCE pin of the slave device. The VCCSEL pin on the slave device selects which input buffer is used for nCE. When VCCSEL is logic high, it selects the 1.8-V/1.5-V buffer powered by VCCIO. When VCCSEL is logic low, it selects the 3.3-V/2.5-V input buffer powered by VCCPD . The ideal case is to have the VCC IO of the nCEO bank in a master device match the VCCSEL settings for the nCE input buffer of the slave device it is connected to, but that may not be possible depending on the application. Table 2–28 contains board design recommendations to ensure that nCEO can successfully drive nCE for all power supply combinations.
Table 2–28. Board Design Recommendations for nCEO and nCE Input Buffer Power nCE Input Buffer Power in I/O Bank 3
VCCSEL high
Arria GX nCEO VCCIO Voltage Level in I/O Bank 7 VC C I O = 3.3 V v ( 1), (2) v (1), ( 2) v VC C I O = 2.5 V v (3) , ( 4) v (3), (4) v ( 4) VC C I O = 1.8 V v ( 5) v v ( 6) VC C I O = 1.5 V v v Level shifter required VC C I O = 1.2 V v Level shifter required Level shifter required
(VCC I O Bank 3 = 1.5 V)
VCCSEL high
(VCC I O Bank 3 = 1.8 V)
VCCSEL low (nCE
powered by VC C P D = 3.3 V)
Notes to Table 2–28:
(1) (2) (3) (4) (5) (6)
Input buffer is 3.3-V tolerant. The nCEO output buffer meets VO H ( MIN) = 2.4 V. Input buffer is 2.5-V tolerant. The nCEO output buffer meets VO H ( MIN) = 2.0 V. Input buffer is 1.8-V tolerant. An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
For JTAG chains, the TDO pin of the first device drives the TDI pin of the second device in the chain. The VCCSEL input on JTAG input I/O cells (TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the 3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have the VCCIO of the TDO bank from the first device to match the VCCSEL settings for TDI on the second device, but that may not be possible depending on the application. Table 2–29 contains board design recommendations to ensure proper JTAG chain operation.
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Table 2–29. Supported TDO/TDI Voltage Combinations TDI Input Buffer Power Always VC C P D (3.3 V) VCC = 3.3 V VCC = 2.5 V Non-Arria GX VCC = 1.8 V VCC = 1.5 V
Notes to Table 2–29:
(1) (2) (3) (4) (5) (6) The TDO output buffer meets VOH (MIN) = 2.4 V. The TDO output buffer meets VOH (MIN) = 2.0 V. An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal. Input buffer must be 3.3-V tolerant. Input buffer must be 2.5-V tolerant. Input buffer must be 1.8-V tolerant.
Arria GX TDO VC C I O Voltage Level in I/O Bank 4 VC C I O = 3.3 V v (1) v (1) v (1), ( 4) v (1), ( 4) v (1), ( 4) VC C I O = 2.5 V v (2) v (2) v (2) v ( 2) , (5) v ( 2) , (5) VC C I O = 1.8 V v ( 3) v ( 3) v ( 3) v v ( 6) VC C I O = 1.5 V Level shifter required Level shifter required Level shifter required Level shifter required v VC C I O = 1.2 V Level shifter required Level shifter required Level shifter required Level shifter required v
Device Arria GX
High-Speed Differential I/O with DPA Support
Arria GX devices contain dedicated circuitry for supporting differential standards at speeds up to 840 Mbps. LVDS differential I/O standards are supported in the Arria GX device. In addition, the LVPECL I/O standard is supported on input and output clock pins on the top and bottom I/O banks. The high-speed differential I/O circuitry supports the following high-speed I/O interconnect standards and applications:
■ ■ ■
SPI-4 Phase 2 (POS-PHY Level 4) SFI-4 Parallel RapidIO standard
There are two dedicated high-speed PLLs (PLL1 and PLL2) in the EP1AGX20 and EP1AGX35 devices and up to four dedicated high-speed PLLs (PLL1, PLL2, PLL7, and PLL8) in the EP1AGX50, EP1AGX60, and EP1AGX90 devices to multiply reference clocks and drive high-speed differential SERDES channels in I/O banks 1 and 2. Table 2–30 through Table 2–34 list the number of channels that each fast PLL can clock in each of the Arria GX devices. In Table 2–30 through Table 2–34 the first row for each transmitter or receiver provides the maximum number of channels that each fast PLL can drive in its adjacent I/O bank (I/O Bank 1 or I/O Bank 2). The second row shows the maximum number of channels that each fast PLL can drive in both I/O banks (I/O Bank 1 and I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20
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device, PLL 1 can drive a maximum of 16 transmitter channels in I/O Bank 2 or a maximum of 29 transmitter channels in I/O Banks 1 and 2. The Quartus II software can also merge receiver and transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. 1 For more information, refer to the “Differential Pin Placement Guidelines” section in the High-Speed Differential I/O Interfaces with DPA in Arria GX Devices chapter.
(Note 1) Center Fast PLLs Package Transmitter/Receiver Total Channels PLL1 Transmitter 484-pin FineLine BGA Receiver Transmitter 780-pin FineLine GBA Receiver
Note to Table 2–30:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
Table 2–30. EP1AGX20 Device Differential Channels
PLL2 13 16 14 17 13 16 14 17
29 31 29 31
16 13 17 14 16 13 17 14
Table 2–31. EP1AGX35 Device Differential Channels (Note 1) Center Fast PLLs Package Transmitter/Receiver Transmitter 484-pin FineLine BGA Receiver Transmitter 780-pin FineLine BGA Receiver Total Channels PLL1 29 31 29 31 16 13 17 14 16 13 17 14
Note to Table 2–31:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
PLL2 13 16 14 17 13 16 14 17
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Table 2–32. EP1AGX50 Device Differential Channels (Note 1) Package Transmitter/ Receiver Transmitter 484-pin FineLine BGA Receiver Transmitter 780-pin FineLine BGA Receiver Transmitter 1,152-pin FineLine BGA Receiver Center Fast PLLs Total Channels PLL1 29 31 29 31 42 42 16 13 17 14 16 13 17 14 21 21 21 21
Note to Table 2–32:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
Corner Fast PLLs PLL7 — — — — — — — — 21 — 21 — PLL8 — — — — — — — — 21 — 21 —
PLL2 13 16 14 17 13 16 14 17 21 21 21 21
Table 2–33. EP1AGX60 Device Differential Channels Package Transmitter/ Receiver Transmitter 484-pin FineLine BGA Receiver Transmitter 780-pin FineLine BGA Receiver Transmitter 1,152-pin FineLine BGA Receiver Total Channels
(Note 1) Center Fast PLLs PLL1 PLL2 13 16 14 17 13 16 14 17 21 21 21 21 Corner Fast PLLs PLL7 — — — — — — — — 21 — 21 — PLL8 — — — — — — — — 21 — 21 —
29 31 29 31 42 42
16 13 17 14 16 13 17 14 21 21 21 21
Note to Table 2–33:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
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Table 2–34. EP1AGX90 Device Differential Channels
(Note 1) Center Fast PLLs Corner Fast PLLs PLL7 23 — 23 —
Package
Transmitter/Receiver
Total Channels PLL1 PLL2 22 23 24 23 23 22 23 24
Transmitter 1,152-pin FineLine BGA Receiver
Note to Table 2–34:
45 47
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
Dedicated Circuitry with DPA Support
Arria GX devices support source-synchronous interfacing with LVDS signaling at up to 840 Mbps. Arria GX devices can transmit or receive serial channels along with a low-speed or high-speed clock. The receiving device PLL multiplies the clock by an integer factor W = 1 through 32. The SERDES factor J determines the parallel data width to deserialize from receivers or to serialize for transmitters. The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the PLL clock-multiplication W value. A design using the dynamic phase aligner also supports all of these J factor values. For a J factor of 1, the Arria GX device bypasses the SERDES block. For a J factor of 2, the Arria GX device bypasses the SERDES block, and the DDR input and output registers are used in the IOE. Figure 2–79 shows the block diagram of the Arria GX transmitter channel.
Figure 2–79. Arria GX Transmitter Channel
Data from R4, R24, C4, or direct link interconnect
+ – 10 10
Up to 840 Mbps
Local Interconnect
Dedicated Transmitter Interface
diffioclk refclk Fast PLL load_en Regional or global clock
Each Arria GX receiver channel features a DPA block for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel. In addition, you can dynamically switch between using the DPA block or bypassing the block via a control signal from the logic array.
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Figure 2–80 shows the block diagram of the Arria GX receiver channel.
Figure 2–80. GX Receiver Channel
Data to R4, R24, C4, or direct link interconnect Up to 840 Mbps
+ – D Q
Data Realignment Circuitry
10
data
retimed_data DPA DPA_clk Synchronizer
Dedicated Receiver Interface
Eight Phase Clocks
8
diffioclk refclk Fast PLL load_en Regional or global clock
An external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. In addition, eight phase-shifted clocks from the VCO can feed to the DPA circuitry. f For more information about fast PLL, refer to the PLLs in Arria GX Devices chapter. The eight phase-shifted clocks from the fast PLL feed to the DPA block. The DPA block selects the closest phase to the center of the serial data eye to sample the incoming data. This allows the source-synchronous circuitry to capture incoming data correctly regardless of channel-to-channel or clock-to-channel skew. The DPA block locks to a phase closest to the serial data phase. The phase-aligned DPA clock is used to write the data into the synchronizer. The synchronizer sits between the DPA block and the data realignment and SERDES circuitry. Because every channel using the DPA block can have a different phase selected to sample the data, the synchronizer is needed to synchronize the data to the high-speed clock domain of the data realignment and the SERDES circuitry. For high-speed source-synchronous interfaces such as POS-PHY 4 and the Parallel RapidIO standard, the source synchronous clock rate is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is necessary for these protocols because the source synchronous clock does not provide a byte or word boundary as the clock is one half the data rate, not one eighth. The Arria GX device’s high-speed differential I/O circuitry provides dedicated data realignment circuitry for user-controlled byte boundary shifting. This simplifies designs while saving ALM resources. You can use an ALM-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment.
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Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved as such that each I/O bank on the left side of the device has one receiver channel and one transmitter channel per LAB row. Figure 2–81 shows the fast PLL and channel layout in the EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D and EP1AGX60C/D devices. Figure 2–82 shows the fast PLL and channel layout in EP1AGX60E and EP1AGX90E devices.
Figure 2–81. Fast PLL and Channel Layout in EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D Devices (Note 1)
4 LVDS Clock 4 2 Fast PLL 1 DPA Clock Quadrant Quadrant
2
Fast PLL 2
4
LVDS Clock
DPA Clock
Quadrant
Quadrant
Note to Figure 2–81:
(1) For the number of channels each device supports, refer to Table 2–30.
Figure 2–82. Fast PLL and Channel Layout in EP1AGX60E and EP1AGX90E Devices (Note 1)
Fast PLL 7 2 4 LVDS Clock DPA Clock Quadrant Quadrant
4 2 Fast PLL 1
2
Fast PLL 2
4
LVDS Clock
DPA Clock
Quadrant
Quadrant
2 Fast PLL 8
Note to Figure 2–82:
(1) For the number of channels each device supports, refer to Table 2–30 through Table 2–34.
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Document Revision History
Table 2–35 shows the revision history for this chapter.
Table 2–35. Document Revision History Date and Document Version December 2009, v2.0 May 2008, v1.3
■ ■
Changes Made Document template update. Minor text edits.
Summary of Changes —
Added “Reverse Serial Pre-CDR Loopback” and “Calibration Block” sub-sections to “Transmitter Path” section. Added “Referenced Documents” section. Added GIGE information. Initial release.
— — — —
August 2007, v1.2 June 2007, v1.1 May 2007 v1.0
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Arria GX Device Handbook, Volume 1
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3. Configuration and Testing
AGX51003-2.0
Introduction
All Arria® GX devices provide JTAG boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1. You can perform JTAG boundary-scan testing either before or after, but not during configuration. Arria GX devices can also use the JTAG port for configuration with the Quartus® II software or hardware using either jam files (.jam) or jam byte-code files (.jbc). This chapter contains the following sections:
■ ■ ■ ■
“IEEE Std. 1149.1 JTAG Boundary-Scan Support” “SignalTap II Embedded Logic Analyzer” on page 3–3 “Configuration” on page 3–3 “Automated Single Event Upset (SEU) Detection” on page 3–8
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Arria GX devices support I/O element (IOE) standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user-mode through the CONFIG_IO instruction. You can use this capability for JTAG testing before configuration when some of the Arria GX pins drive or receive from other devices on the board using voltage-referenced standards. Because the Arria GX device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate electrical standards for chip-to-chip communication. Programming these I/O standards via JTAG allows you to fully test the I/O connections to other devices. A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have weak internal pull-up resistors. The JTAG input pins are powered by the 3.3-V VCCPD pins. The TDO output pin is powered by the VCCIO power supply in I/O bank 4. Arria GX devices also use the JTAG port to monitor the logic operation of the device with the SignalTap ® II embedded logic analyzer. Arria GX devices support the JTAG instructions shown in Table 3–1. 1 Arria GX, Cyclone® II, Cyclone, Stratix® , Stratix II, Stratix GX , and Stratix II GX devices must be within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Stratix, Arria GX, Cyclone, and Cyclone II devices are in the 18th or further position, they will fail configuration. This does not affect the functionality of the SignalTap ® II embedded logic analyzer.
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Chapter 3: Configuration and Testing IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3–1. Arria GX JTAG Instructions JTAG Instruction SAMPLE/PRELOAD Instruction Code 00 0000 0101 Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer. Allows external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the T DI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. Selects the 32-bit USERCODE register and places it between the TDI a nd TDO pins, allowing the USERCODE to be serially shifted out of T DO. Selects the IDCODE register and places it between T DI and TDO , allowing IDCODE to be serially shifted out of TDO. Places the 1-bit bypass register between the T DI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. Places the 1-bit bypass register between the T DI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. Used when configuring an Arria GX device via the JTAG port with a USB-Blaster TM , MasterBlaster TM , ByteBlasterMVTM, EthernetBlaster TM , or ByteBlaster II download cable, or when using a .jam or .jbc via an embedded processor or JRunnerTM . Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, during, or after configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction holds nSTATUS low to reset the configuration device. n STATUS is held low until the IOE configuration register is loaded and the TAP controller state machine transitions to the UPDATE_DR state.
EXTEST ( 1)
00 0000 1111
BYPASS
11 1111 1111
USERCODE
00 0000 0111
IDCODE HIGHZ (1)
00 0000 0110 00 0000 1011
CLAMP (1)
00 0000 1010
ICR instructions
—
PULSE_NCONFIG CONFIG_IO (2)
00 0000 0001 00 0000 1101
Notes to Table 3–1:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. (2) For more information about using the CONFIG_IO instruction, refer to the M orphIO: An I/O Reconfiguration Solution f or Altera Devices White Paper.
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Chapter 3: Configuration and Testing SignalTap II Embedded Logic Analyzer
3–3
The Arria GX device instruction register length is 10 bits and the USERCODE register length is 32 bits. Table 3–2 and Table 3–3 show the boundary-scan register length and device IDCODE information for Arria GX devices.
Table 3–2. Arria GX Boundary-Scan Register Length Device EP1AGX20 EP1AGX35 EP1AGX50 EP1AGX60 EP1AGX90 Table 3–3. 2-Bit Arria GX Device IDCODE IDCODE (32 Bits) Device Version (4 Bits) EP1AGX20 EP1AGX35 EP1AGX50 EP1AGX60 EP1AGX90 0000 0000 0000 0000 0000 Part Number (16 Bits) 0010 0001 0010 0001 0010 0001 0010 0001 0010 0001 0010 0010 0010 0001 0010 0010 0010 0001 0010 0011 Manufacturer Identity (11 Bits) 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 LSB (1 Bit) 1 1 1 1 1 Boundary-Scan Register Length 1320 1320 1668 1668 2016
SignalTap II Embedded Logic Analyzer
Arria GX devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA (FBGA) packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Arria GX architecture are configured with CMOS SRAM elements. Altera® FPGAs are reconfigurable and every device is tested with a high coverage production test program so you do not have to perform fault testing and can instead focus on simulation and design verification. Arria GX devices are configured at system power up with data stored in an Altera configuration device or provided by an external controller (for example, a MAX ® II device or microprocessor). You can configure Arria GX devices using the fast passive parallel (FPP), active serial (AS), passive serial (PS), passive parallel asynchronous (PPA), and JTAG configuration schemes. Each Arria GX device has an optimized interface that allows microprocessors to configure it serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat Arria GX devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy.
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Chapter 3: Configuration and Testing Configuration
In addition to the number of configuration methods supported, Arria GX devices also offer decompression and remote system upgrade features. The decompression feature allows Arria GX FPGAs to receive a compressed configuration bitstream and decompress this data in real-time, reducing storage requirements and configuration time. The remote system upgrade feature allows real-time system upgrades from remote locations of Arria GX designs. For more information, refer to “Configuration Schemes” on page 3–5.
Operating Modes
The Arria GX architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power up, and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. SRAM configuration elements allow you to reconfigure Arria GX devices in-circuit by loading new configuration data into the device. With real-time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, re-initializes the device, and resumes user-mode operation. You can perform in-field upgrades by distributing new configuration files either within the system or remotely. PORSEL is a dedicated input pin used to select power-on reset (POR) delay times of 12 ms or 100 ms during power up. When the PORSEL pin is connected to ground, the POR time is 100 ms. When the PORSEL pin is connected to VCC, the POR time is 12 ms. The nIO_PULLUP pin is a dedicated input that chooses whether the internal pull-up resistors on the user I/O pins and dual-purpose configuration I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR) are on or off before and during configuration. A logic high (1.5, 1.8, 2.5, 3.3 V) turns off the weak internal pull-up resistors, while a logic low turns them on. Arria GX devices also offer a new power supply, V C CPD, which must be connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on the configuration input pins and JTAG pins. VCCPD applies to all the JTAG input pins (TCK, TMS, TDI, and TRST) and the following configuration pins: nCONFIG, DCLK (when used as an input), nIO_PULLUP, DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The VCCSEL pin allows the VCCIO setting (of the banks where the configuration inputs reside) to be independent of the voltage required by the configuration inputs. Therefore, when selecting the VCCIO voltage, you do not have to take the VIL and VIH levels driven to the configuration inputs into consideration. The configuration input pins, nCONFIG, DCLK (when used as an input), nIO_PULLUP, RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR, have a dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input buffer. The VCCSEL input pin selects which input buffer is used. The 3.3-V/2.5-V input buffer is powered by VCCPD , while the 1.8-V/1.5-V input buffer is powered by VCCIO.
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VCCSEL is sampled during power up. Therefore, the V CCSEL setting cannot change on-the-fly or during a reconfiguration. The V CCSEL input buffer is powered by VCCINT and must be hard-wired to VC CPD or ground. A logic high VCC SEL connection selects the 1.8-V/1.5-V input buffer, and a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the logic levels driven out of the configuration device or MAX II microprocessor. If the design must support configuration input voltages of 3.3 V/2.5 V, set VCCSEL to a logic low. You can set the VCCIO voltage of the I/O bank that contains the configuration inputs to any supported voltage. If the design must support configuration input voltages of 1.8 V/1.5 V, set VCCSEL to a logic high and the VCCIO of the bank that contains the configuration inputs to 1.8 V/1.5 V. f For more information about multi-volt support, including information about using TDO and nCEO in multi-volt systems, refer to the Arria GX Architecture chapter.
Configuration Schemes
You can load the configuration data for an Arria GX device with one of five configuration schemes (refer to Table 3–4), chosen on the basis of the target application. You can use a configuration device, intelligent controller, or the JTAG port to configure an Arria GX device. A configuration device can automatically configure an Arria GX device at system power up. You can configure multiple Arria GX devices in any of the five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Arria GX FPGAs offer the following:
■ ■
Configuration data decompression to reduce configuration file storage Remote system upgrades for remotely updating Arria GX designs
Table 3–4 lists which configuration features can be used in each configuration scheme. f For more information about configuration schemes in Arria GX devices, refer to the Configuring Arria GX Devices chapter.
Table 3–4. Arria GX Configuration Features (Part 1 of 2) Configuration Scheme FPP AS Configuration Method MAX II device or microprocessor and flash device Enhanced configuration device Serial configuration device MAX II device or microprocessor and flash device PS Enhanced configuration device Download cable ( 4) PPA MAX II device or microprocessor and flash device Decompression v (1) v (2) v v v v — Remote System Upgrade v v v (3) v v — v
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Table 3–4. Arria GX Configuration Features (Part 2 of 2) Configuration Scheme JTAG
Notes for Table 3–4:
(1) (2) (3) (4) In these modes, the host system must send a DCLK t hat is 4× the data rate. The enhanced configuration device decompression feature is available, while the Arria GX decompression feature is not available. Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported. The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable, MasterBlaster ™ serial/USB communications cable, ByteBlaster II parallel port download cable, ByteBlasterMV parallel port download cable, and the EthernetBlaster download cable.
Configuration Method Download cable ( 4) MAX II device or microprocessor and flash device
Decompression — —
Remote System Upgrade — —
Device Configuration Data Decompression
Arria GX FPGAs support decompression of configuration data, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to Arria GX FPGAs. During configuration, the Arria GX FPGA decompresses the bitstream in real time and programs its SRAM cells. Arria GX FPGAs support decompression in the FPP (when using a MAX II device or microprocessor and flash memory), AS, and PS configuration schemes. Decompression is not supported in the PPA configuration scheme nor in JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in remote locations are difficult challenges faced by system designers. Arria GX devices can help effectively deal with these challenges with their inherent re programmability and dedicated circuitry to perform remote system updates. Remote system updates help deliver feature enhancements and bug fixes without costly recalls, reduce time to market, and extend product life. Arria GX FPGAs feature dedicated remote system upgrade circuitry to facilitate remote system updates. Soft logic (Nios® processor or user logic) implemented in the Arria GX device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry avoids system downtime and is the critical component for successful remote system upgrades. Remote system configuration is supported in the following Arria GX configuration schemes: FPP, AS, PS, and PPA. You can also implement remote system configuration in conjunction with Arria GX features such as real-time decompression of configuration data for efficient field upgrades. f For more information about remote configuration in Arria GX devices, refer to the Remote System Upgrades with Arria GX Devices chapter.
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Chapter 3: Configuration and Testing Configuration
3–7
Configuring Arria GX FPGAs with JRunner
The JRunner software driver configures Altera FPGAs, including Arria GX FPGAs, through the ByteBlaster™ II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner is targeted for embedded JTAG configuration. The source code is developed for the Windows NT operating system (OS), but can be customized to run on other platforms. f For more information about the JRunner software driver, refer to the AN414: JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration and the source files on the Altera website.
Programming Serial Configuration Devices with SRunner
You can program a serial configuration device in-system by an external microprocessor using SRunnerTM . SRunner is a software driver developed for embedded serial configuration device programming that can be easily customized to fit into different embedded systems. SRunner software driver reads a raw programming data file (.rpd) and writes to serial configuration devices. The serial configuration device programming time using SRunner software driver is comparable to the programming time when using the Quartus II software. f For more information about SRunner, refer to the AN418: SRunner: An Embedded Solution for Serial Configuration Device Programming and the source code on the Altera website. For more information about programming serial configuration devices, refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS64, and EPCS128) Data Sheet in the Configuration Handbook.
f
Configuring Arria GX FPGAs with the MicroBlaster Driver
The MicroBlaster™ software driver supports a raw binary file (RBF) programming input file and is ideal for embedded FPP or PS configuration. The source code is developed for the Windows NT operating system, although it can be customized to run on other operating systems. f For more information about the MicroBlaster software driver, refer to the C onfiguring the MicroBlaster Fast Passive Parallel Software Driver White Paper or the AN423: Configuring the MicroBlaster Passive Serial Software Driver.
PLL Reconfiguration
The phase-locked loops (PLLs) in the Arria GX device family support reconfiguration of their multiply, divide, VCO-phase selection, and bandwidth selection settings without reconfiguring the entire device. You can use either serial data from the logic array or regular I/O pins to program the PLL’s counter settings in a serial chain. This option provides considerable flexibility for frequency synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL.
© December 2009
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Arria GX Device Handbook, Volume 1
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Chapter 3: Configuration and Testing Automated Single Event Upset (SEU) Detection
f
For more information about Arria GX PLLs, refer to the P LLs in Arria GX Devices chapter.
Automated Single Event Upset (SEU) Detection
Arria GX devices offer on-chip circuitry for automated checking of single event upset (SEU) detection. Some applications that require the device to operate error free at high elevations or in close proximity to Earth’s North or South Pole requires periodic checks to ensure continued data integrity. The error detection cyclic redundancy check (CRC) feature controlled by the Device and Pin Options dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU. You can implement the error detection CRC feature with existing circuitry in Arria GX devices, eliminating the need for external logic. Arria GX devices compute CRC during configuration. The Arria GX device checks the computed-CRC against an automatically computed CRC during normal operation. The CRC_ERROR pin reports a soft error when configuration SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built into Arria GX devices to automatically perform error detection. This circuitry constantly checks for errors in the configuration SRAM cells while the device is in user mode. You can monitor one external pin for the error and use it to trigger a reconfiguration cycle. You can select the desired time between checks by adjusting a built-in clock divider.
Software Interface
Beginning with version 7.1 of the Quartus II software, you can turn on the automated error detection CRC feature in the Device and Pin Options dialog box. This dialog box allows you to enable the feature and set the internal frequency of the CRC between 400 kHz to 50 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the Arria GX FPGA. f For more information about CRC, refer to AN 357: Error Detection Using CRC in Altera FPGAs.
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Chapter 3: Configuration and Testing Document Revision History
3–9
Document Revision History
Table 3–5 lists the revision history for this chapter.
Table 3–5. Document Revision History Date and Document Version December 2009, v2.0 May 2009 v1.4 May 2008 v1.3 August 2007 v1.2 June 2007 v1.1 May 2007 v1.0
■ ■ ■
Changes Made Document template update. Minor text edits. Removed “Temperature Sensing Diode” section. Updated Table 3–1 and Table 3–4.
Summary of Changes — —
■
Updated note in “Introduction” section. Minor text edits. Added the “Referenced Documents” section. Deleted Signal Tap II information from Table 3–1. Initial Release — — — —
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Arria GX Device Handbook, Volume 1
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Chapter 3: Configuration and Testing Document Revision History
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
4. DC and Switching Characteristics
AGX51004-2.0
Operating Conditions
Arria® G X devices are offered in both commercial and industrial grades. Both commercial and industrial devices are offered in –6 speed grade only. This chapter contains the following sections:
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
“Operating Conditions” “Power Consumption” on page 4–25 “I/O Timing Model” on page 4–26 “Typical Design Performance” on page 4–32 “Block Performance” on page 4–84 “IOE Programmable Delay” on page 4–86 “Maximum Input and Output Clock Toggle Rate” on page 4–87 “Duty Cycle Distortion” on page 4–95 “High-Speed I/O Specifications” on page 4–100 “PLL Timing Specifications” on page 4–103 “External Memory Interface Specifications” on page 4–105 “JTAG Timing Specifications” on page 4–106
Table 4–1 through Table 4–42 on page 4–25 provide information on absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for Arria GX devices.
Absolute Maximum Ratings
Table 4–1 contains the absolute maximum ratings for the Arria GX device family.
Table 4–1. Arria GX Device Absolute Maximum Ratings Symbol VCCINT VCCIO VCCPD VI IOUT TSTG Parameter Supply voltage Supply voltage Supply voltage DC input voltage (4) DC output current, per pin Storage temperature No bias ( Note 1), (2) , ( 3) (Part 1 of 2) Conditions With respect to ground With respect to ground With respect to ground — — Minimum –0.5 –0.5 –0.5 –0.5 –25 –65 Maximum 1.8 4.6 4.6 4.6 40 150 Units V V V V mA C
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Altera Corporation
Arria GX Device Handbook, Volume 1
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Chapter 4: DC and Switching Characteristics Operating Conditions
Table 4–1. Arria GX Device Absolute Maximum Ratings Symbol TJ
Notes to Table 4–1:
( Note 1), (2) , ( 3) (Part 2 of 2) Conditions Minimum –55 Maximum 125 Units C
Parameter Junction temperature
BGA packages under bias
(1) For more information about operating requirements for Altera® devices, refer to the Arria GX Device Family Data Sheet chapter. (2) Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. (4) During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
Table 4–2. Maximum Duty Cycles in Voltage Transitions Symbol Parameter
(Note 1) Maximum Duty Cycles (%) 100 90 50 30 17 10
Condition VI = 4.0 V VI = 4.1 V
VI
Maximum duty cycles in voltage transitions
VI = 4.2 V VI = 4.3 V VI = 4.4 V VI = 4.5 V
Note to Table 4–2:
(1) During transition, the inputs may overshoot to the voltages shown based on the input duty cycle. The DC case is equivalent to 100% duty cycle.
Recommended Operating Conditions
Table 4–3 lists the recommended operating conditions for the Arria GX device family.
Table 4–3. Arria GX Device Recommended Operating Conditions (Part 1 of 2) Symbol VCCINT Parameter Supply voltage for internal logic and input buffers Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation VCCIO Supply voltage for output buffers, 1.8-V operation Supply voltage for output buffers, 1.5-V operation Supply voltage for output buffers, 1.2-V operation VCCPD VI VO Supply voltage for pre-drivers as well as configuration and JTAG I/O buffers. Input voltage (refer to Table 4–2) Output voltage Conditions Rise time 100 ms (3) Rise time 100 ms (3), ( 6) Rise time 100 ms (3) Rise time 100 ms (3) Rise time 100 ms (3) Rise time 100 ms (3) 100 s rise time 100 ms (4) (Note 1) (Part 1 of 2) Minimum 1.15 3.135 (3.00) 2.375 1.71 1.425 1.15 3.135 Maximum 1.25 3.465 (3.60) 2.625 1.89 1.575 1.25 3.465 Units V V V V V V V
( 2), (5) —
–0.5 0
4.0 VCCIO
V V
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Chapter 4: DC and Switching Characteristics Operating Conditions
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Table 4–3. Arria GX Device Recommended Operating Conditions (Part 2 of 2) Symbol TJ Parameter Operating junction temperature Conditions For commercial use For industrial use
(Note 1) (Part 2 of 2) Minimum 0 –40 Maximum 85 100 Units C C
Notes to Table 4–3:
(1) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. (2) During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Maximum VCC rise time is 100 ms, and VCC m ust rise monotonically from ground to VCC . (4) VCCPD m ust ramp-up from 0 V to 3.3 V within 100 s to 100 ms. If VCCPD is not ramped up within this specified time, the Arria GX device will not configure successfully. If the system does not allow for a V CCPD ramp-up time of 100 ms or less, hold nCONFIG low until all power supplies are reliable. (5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, can be driven before VCCINT, VCCPD, and VCCIO are powered. (6) VCCIO maximum and minimum conditions for PCI and PCI-X are shown in parentheses.
Transceiver Block Characteristics
Table 4–4 through Table 4–6 on page 4–4 contain transceiver block specifications.
Table 4–4. Arria GX Transceiver Block Absolute Maximum Ratings Symbol VCCA VCCP VCCR VCCT_B VCCL_B VCCH_B Parameter Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage (Note 1) Minimum –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 Maximum 4.6 1.8 1.8 1.8 1.8 2.4 Units V V V V V V
Conditions Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial
Note to Table 4–4:
(1) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated.
Table 4–5. Arria GX Transceiver Block Operating Conditions Symbol VCCA VCCP VCCR VCCT_B VCCL_B VCCH_B RREFB ( 1) Parameter Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Reference resistor Conditions Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Minimum 3.135 1.15 1.15 1.15 1.15 1.15 1.425 2K - 1% Typical 3.3 1.2 1.2 1.2 1.2 1.2 1.5 2K Maximum 3.465 1.25 1.25 1.25 1.25 1.25 1.575 2K +1% Units V V V V V V V
Note to Table 4–5:
(1) The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin.
© December 2009
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Arria GX Device Handbook, Volume 1
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Chapter 4: DC and Switching Characteristics Operating Conditions
Table 4–6. Arria GX Transceiver Block AC Specification (Part 1 of 3) –6 Speed Grade Commercial and Industrial Min Reference clock Input reference clock frequency Absolute VM A X for a REFCLK Pin Absolute VMIN for a REFCLK Pin Rise/Fall time Duty cycle Peak to peak differential input voltage VID (diff p-p) Spread spectrum clocking (1) On-chip termination resistors VICM (AC coupled) VICM ( DC coupled) (2) RREFB Transceiver Clocks Calibration block clock frequency Calibration block minimum power-down pulse width fixedclk clock frequency (3) reconfig clock frequency Transceiver block minimum power-down pulse width Receiver Data rate Absolute VMAX f or a receiver pin (4) Absolute VMIN for a receiver pin Maximum peak-to-peak differential input voltage VID ( diff p-p) Minimum peak-to-peak differential input voltage VID ( diff p-p) On-chip termination resistors — — — Vicm = 0.85 V DC Gain = 3 dB — Vicm = 0.85 V setting Vicm = 1.2 V setting BW = Low Bandwidth at 3.125 Gbps BW = Med BW = High 600 — –0.4 — 160 — — — — — 100±15% 850 ± 10% 850 ± 10% 850 ± 10% 1200 ± 10% — — — 1200 ± 10% 30 40 50 1200 ± 10% — — — MHz 3125 2.0 — 3.3 — Mbps V V V mV
Symbol / Description
Conditions
Units
Typ
Max
— — — — — — 0 to –0.5% — — PCI Express (PIPE) mode —
50 — –0.3 — 45 200 30
— — — 0.2 — — — 115 ± 20% 1200 ± 5%
622.08 3.3 — — 55 2000 33
MHz V V UI % mV kHz
mV 0.55 V
0.25
— 2000 +/-1%
— — — SDI mode —
10 30
— — 125 ±10%
125 —
MHz ns MHz
2.5 100
— —
50 —
MHz ns
mV mV
VICM ( 15)
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Table 4–6. Arria GX Transceiver Block AC Specification (Part 2 of 3) –6 Speed Grade Commercial and Industrial Min Bandwidth at 2.5 Gbps BW = Low BW = Med BW = High Return loss differential mode 50 MHz to 1.25 GHz (PCI Express) 100 MHz to 2.5 GHz (XAUI) Return loss common mode 50 MHz to 1.25 GHz (PCI Express) 100 MHz to 2.5 GHz (XAUI) Programmable PPM detector (5) Run length ( 6) Programmable equalization Signal detect/loss threshold (7) CDR LTR TIme (8), ( 9) CDR Minimum T1b (9), (10) LTD lock time ( 9), (11) Data lock time from rx_freqlocked ( 9), (12) Programmable DC gain Transmitter Buffer Output Common Mode voltage (Vocm) On-chip termination resistors — — 50 MHz to 1.25 GHz (PCI Express) Return loss differential mode 312 MHz to 625 MHz (XAUI) 625 MHz to 3.125GHz (XAUI) Return loss common mode Rise time Fall time Intra differential pair skew Intra-transceiver block skew (×4) (13) 50 MHz to 1.25 GHz (PCI Express) — — VOD = 800 mV — 35 35 — — 580 ± 10% 108±10% mV dB –10 — — — — — — — — — — 65 — 15 0 — ± 62.5, 100, 125, 200, 250, 300, 500, 1000 80 — — — — 100 — 0, 3, 6 5 175 75 — 4000 4 PPM UI dB mV us us ns us dB — — — Typ 35 50 60 Max — — — MHz
Symbol / Description
Conditions
Units
–10
dB
–6
dB
–10 –6 — — — — 65 65 15 100
dB -----------------------------------decade slope
dB ps ps ps ps
© December 2009
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Arria GX Device Handbook, Volume 1
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Chapter 4: DC and Switching Characteristics Operating Conditions
Table 4–6. Arria GX Transceiver Block AC Specification (Part 3 of 3) –6 Speed Grade Commercial and Industrial Min Transmitter PLL VCO frequency range Bandwidth at 3.125 Gbps — BW = Low BW = Med BW = High BW = Low Bandwidth at 2.5 Gbps TX PLL lock time from g xb_powerdown de-assertion ( 9) , (14) PCS Interface speed per mode Digital Reset Pulse Width
Notes to Table 4–6:
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) Spread spectrum clocking is allowed only in PCI Express (PIPE) mode if the upstream transmitter and the receiver share the same clock source. The reference clock DC coupling option is only available in PCI Express (PIPE) mode for the HCSL I/O standard. The fixedclk is used in PIPE mode receiver detect circuitry. The device cannot tolerate prolonged operation at this absolute maximum. The rate matcher supports only up to ± 300 PPM for PIPE mode and ± 100 PPM for GIGE mode. This parameter is measured by embedding the run length data in a PRBS sequence. Signal detect threshold detector circuitry is available only in PCI Express (PIPE mode). Time taken for rx_pll_locked to go high from rx_analogreset deassertion. Refer to Figure 4–1. For lock times specific to the protocols, refer to protocol characterization documents. Time for which the CDR needs to stay in LTR mode after rx_pll_locked is asserted and before rx_locktodata is asserted in manual mode. Refer to Figure 4–1. Time taken to recover valid data from GXB after the rx_locktodata signal is asserted in manual mode. Measurement results are based on PRBS31, for native data rates only. Refer to Figure 4–1. Time taken to recover valid data from GXB after the rx_freqlocked signal goes high in automatic mode. Measurement results are based on PRBS31, for native data rates only. Refer to Figure 4–2. This is applicable only to PCI Express (PIPE) ×4 and XAUI ×4 mode. Time taken to lock TX PLL from gxb_powerdown deassertion. The 1.2 V RX VICM settings is intended for DC-coupled LVDS links.
Symbol / Description
Conditions
Units
Typ
Max
500 — — — — — — —
— 3 5 9 1 2 4 —
1562.5 — — — — — — 100
MHz MHz
BW = Med BW = High —
MHz
us
— —
25
—
156.25
MHz —
Minimum is 2 parallel clock cycles
Figure 4–1 shows the lock time parameters in manual mode. Figure 4–2 shows the lock time parameters in automatic mode. 1 LTD = Lock to data LTR = Lock to reference clock
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Chapter 4: DC and Switching Characteristics Operating Conditions
4–7
Figure 4–1. Lock Time Parameters for Manual Mode
r x_analogreset
CDR status
LTR
LTD
r x_pll_locked
r x_locktodata
Invalid Data r x_dataout
Valid data
CDR LTR Time
LTD lock time
CDR Minimum T1b
Figure 4–2. Lock Time Parameters for Automatic Mode
CDR status
LTR
LTD
r x_freqlocked
r x_dataout
Invalid
data
Valid
data
Data lock time from rx_freqlocked
© December 2009
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Arria GX Device Handbook, Volume 1
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Chapter 4: DC and Switching Characteristics Operating Conditions
Figure 4–3 and Figure 4–4 show differential receiver input and transmitter output waveforms, respectively.
Figure 4–3. Receiver Input Waveform
Single-Ended Waveform Positive Channel (p) VID Negative Channel (n) VCM Ground
Differential Waveform
VID (diff peak-peak) = 2 x VID (single-ended) VID p−n=0V VID
Figure 4–4. Transmitter Output Waveform
Single-Ended Waveform Positive Channel (p) VOD Negative Channel (n) VCM Ground
Differential Waveform
VOD (diff peak-peak) = 2 x VOD (single-ended) VOD p−n=0V VOD
Table 4–7 lists the Arria GX transceiver block AC specification.
Table 4–7. Arria GX Transceiver Block AC Specification Description XAUI Transmit Jitter Generation ( 4)
REFCLK = 156.25 MHz
( Note 1), ( 2), (3) (Part 1 of 4) Condition –6 Speed Grade Commercial & Units Industrial
Total jitter at 3.125 Gbps
Pattern = CJPAT VOD = 1200 mV No Pre-emphasis
0.3
UI
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Chapter 4: DC and Switching Characteristics Operating Conditions
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Table 4–7. Arria GX Transceiver Block AC Specification Description
( Note 1), ( 2), (3) (Part 2 of 4) Condition –6 Speed Grade Commercial & Units Industrial
REFCLK = 156.25 MHz
Deterministic jitter at 3.125 Gbps
Pattern = CJPAT VOD = 1200 mV No Pre-emphasis
0.17
UI
XAUI Receiver Jitter Tolerance (4) Pattern = CJPAT Total jitter No Equalization DC Gain = 3 dB Pattern = CJPAT Deterministic jitter Peak-to-peak jitter Peak-to-peak jitter Peak-to-peak jitter No Equalization DC Gain = 3 dB Jitter frequency = 22.1 KHz Jitter frequency = 1.875 MHz Jitter frequency = 20 MHz > 8.5 > 0.1 > 0.1 UI UI UI > 0.37 UI > 0.65 UI
PCI Express (PIPE) Transmitter Jitter Generation (5) Total Transmitter Jitter Generation Compliance Pattern; VOD = 800 mV; Pre-emphasis = 49% < 0.25 UI p-p
PCI Express (PIPE) Receiver Jitter Tolerance ( 5) Total Receiver Jitter Tolerance Compliance Pattern; DC Gain = 3 db > 0.6 UI p-p
Gigabit Ethernet (GIGE) Transmitter Jitter Generation (7) Total Transmitter Jitter Generation (TJ) Deterministic Transmitter Jitter Generation (DJ) CRPAT: VOD = 800 mV; Pre-emphasis = 0% CRPAT; VOD = 800 mV; Pre-emphasis = 0% < 0.279 < 0.14 UI p-p UI p-p
Gigabit Ethernet (GIGE) Receiver Jitter Tolerance Total Jitter Tolerance Deterministic Jitter Tolerance CJPAT Compliance Pattern; DC Gain = 0 dB CJPAT Compliance Pattern; DC Gain = 0 dB > 0.66 > 0.4 UI p-p UI p-p
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Transmitter Jitter Generation (6) CJPAT Compliance Pattern; Total Transmitter Jitter Generation (TJ) VOD = 800 mV; Pre-emphasis = 0% CJPAT Compliance Pattern; Deterministic Transmitter Jitter Generation (DJ) VOD = 800 mV; Pre-emphasis = 0% < 0.17 UI p-p < 0.35 UI p-p
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Chapter 4: DC and Switching Characteristics Operating Conditions
Table 4–7. Arria GX Transceiver Block AC Specification Description
( Note 1), ( 2), (3) (Part 3 of 4) Condition –6 Speed Grade Commercial & Units Industrial
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Receiver Jitter Tolerance ( 6) Total Jitter Tolerance Combined Deterministic and Random Jitter Tolerance (JDR) Deterministic Jitter Tolerance (JD) CJPAT Compliance Pattern; DC Gain = 0 dB CJPAT Compliance Pattern; DC Gain = 0 dB CJPAT Compliance Pattern; DC Gain = 0 dB Jitter Frequency = 22.1 KHz Sinusoidal Jitter Tolerance Jitter Frequency = 200 KHz Jitter Frequency = 1.875 MHz Jitter Frequency = 20 MHz SDI Transmitter Jitter Generation (8) Data Rate = 1.485 Gbps (HD) REFCLK = 74.25 MHz Pattern = Color Bar Vod = 800 mV No Pre-emphasis Low-Frequency Roll-Off = 100 KHz Data Rate = 2.97 Gbps (3G) REFCLK = 148.5 MHz Pattern = Color Bar Vod = 800 mV No Pre-emphasis Low-Frequency Roll-Off = 100 KHz > 0.65 > 0.55 > 0.37 > 8.5 > 1.0 > 0.1 > 0.1 UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p
0.2
UIv
Alignment Jitter (peak-to-peak)
0.3
UI
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Table 4–7. Arria GX Transceiver Block AC Specification Description SDI Receiver Jitter Tolerance ( 8)
( Note 1), ( 2), (3) (Part 4 of 4) Condition –6 Speed Grade Commercial & Units Industrial
Jitter Frequency = 15 KHz Data Rate = 2.97 Gbps (3G) REFCLK = 148.5 MHz Pattern = Single Line Scramble Color Bar No Equalization DC Gain = 0 dB Jitter Frequency = 100 KHz Data Rate = 2.97 Gbps (3G) REFCLK = 148.5 MHz Pattern = Single Line Scramble Color Bar No Equalization DC Gain = 0 dB Jitter Frequency = 148.5 MHz Data Rate = 2.97 Gbps (3G) REFCLK = 148.5 MHz Pattern = Single Line Scramble Color Bar No Equalization DC Gain = 0 dB Jitter Frequency = 20 KHz Data Rate = 1.485 Gbps (HD) REFCLK = 74.25 MHz Pattern = 75% Color Bar No Equalization DC Gain = 0 dB Jitter Frequency = 100 KHz Data Rate = 1.485 Gbps (HD) REFCLK = 74.25 MHz Pattern = 75% Color Bar No Equalization DC Gain = 0 dB
>2
UI
Sinusoidal Jitter Tolerance (peak-to-peak)
> 0.3
UI
> 0.3
UI
>1
UI
Sinusoidal Jitter Tolerance (peak-to-peak)
> 0.2
UI
Notes to Table 4–7:
(1) (2) (3) (4) (5) (6) (7) (8) Dedicated REFCLK pins were used to drive the input reference clocks. Jitter numbers specified are valid for the stated conditions only. Refer to the protocol characterization documents for detailed information. The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification. The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0. The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3. The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification. The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M specifications.
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Arria GX Device Handbook, Volume 1
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Chapter 4: DC and Switching Characteristics Operating Conditions
Table 4–8 and Table 4–9 list the transmitter and receiver PCS latency for each mode, respectively.
Table 4–8. PCS Latency (Note 1) Transmitter PCS Latency Functional Mode XAUI Configuration TX PIPE — ×1, ×4, ×8 8-bit channel width ×1, ×4, ×8 16-bit channel width — 1.25 Gbps, 2.5 Gbps, 3.125 Gbps HD10-bit channel width HD, 3G 20-bit channel width 8-bit/10-bit channel width 16-bit/20-bit channel width — 1 1 — — — — — — TX Phase Comp FIFO 2–3 3–4 3–4 2–3 2–3 2–3 2–3 2–3 2–3 Byte Serializer 1 1 1 1 1 1 1 1 1 TX State Machine 0.5 — — — — — — — — 8B/10B Encoder 0.5 1 0.5 1 0.5 1 0.5 1 0.5 Sum ( 2) 4–5 6–7 6–7 4–5 4–5 4–5 4–5 4–5 4–5
PIPE
GIGE Serial RapidIO SDI BASIC Single Width
Notes to Table 4–8:
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles. (2) The total latency number is rounded off in the Sum column.
Table 4–9. PCS Latency (Part 1 of 2) (Part 1 of 2) Receiver PCS Latency Receiver Phase Comp FIFO Receiver State Machine Functional Mode
Configuration
Rate Matcher ( 3)
Byte Deserializer
8B/10B Decoder
Receiver PIPE
Word Aligner
Deskew FIFO
Byte Order
XAUI
— ×1, ×4 8-bit channel width ×1, ×4 16-bit channel width — 1.25 Gbps, 2.5 Gbps, 3.125 Gbps HD 10-bit channel width HD, 3G 20-bit channel width
2–2.5 4–5 2–2.5 4–5 2–2.5 5 2.5
2–2.5 — — — — — —
5.5–6.5 11–13 5.5–6.5 11–13 — — —
0.5 1 0.5 1 0.5 1 0.5
1 — — — — — —
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1–2 2–3 2–3 1–2 1–2 1–2 1–2
— 1 1 — — — —
14–17 21–25 13–16 19–23 6–7 9–10 6–7
PIPE
GIGE Serial RapidIO SDI
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Sum (2)
Chapter 4: DC and Switching Characteristics Operating Conditions
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Table 4–9. PCS Latency (Part 2 of 2) (Part 2 of 2) Receiver PCS Latency Receiver Phase Comp FIFO Receiver State Machine Functional Mode
Configuration
Rate Matcher ( 3)
Byte Deserializer
8B/10B Decoder
Receiver PIPE
Word Aligner
Deskew FIFO
Byte Order
8/10-bit channel width; with Rate Matcher BASIC Single Width 8/10-bit channel width; without Rate Matcher 16/20-bit channel width; with Rate Matcher 16/20-bit channel width; without Rate Matcher
Notes to Table 4–9:
4–5 4–5 2–2.5 2–2.5
— — — —
11–13 — 5.5–6.5 —
1 1 0.5 0.5
— — — —
1 1 1 1
1 1 1 1
1–2 1–2 1–2 1–2
1 — — —
19–23 8–10 11–14 6–7
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles. (2) The total latency number is rounded off in the Sum column. (3) The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set gap allowed by the protocol, actual PPM difference between the reference clocks, and so forth.
Table 4–10 through Table 4–13 show the typical VOD for data rates from 600 Mbps to 3.125 Gbps. The specification is for measurement at the package ball.
Table 4–10. Typical VOD Setting, TX Term = 100 Vcc HTX = 1.5 V VOD Typical (mV) VOD Setting (mV) 400 430 600 625 800 830 1000 1020 1200 1200
Table 4–11. Typical VOD Setting, TX Term = 100 Vcc HTX = 1.2 V VOD Typical (mV) VOD Setting (mV) 320 344 480 500 640 664 800 816 960 960
Table 4–12. Typical Pre-Emphasis (First Post-Tap), (Note 1) Vcc HTX = 1.5 V VOD Setting (mV) 1 First Post Tap Pre-Emphasis Level 2 3 TX Term = 100 400 600 800 24% — — 62% 31% 20% 112% 56% 35% 184% 86% 53% — 122% 73% 4 5
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Table 4–12. Typical Pre-Emphasis (First Post-Tap), (Note 1) Vcc HTX = 1.5 V VOD Setting (mV) 1000 1200
Note to Table 4–12:
(1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.
First Post Tap Pre-Emphasis Level 1 — — 2 — — 3 23% 17% 4 36% 25% 5 49% 35%
Table 4–13. Typical Pre-Emphasis (First Post-Tap), (Note 1) Vcc HTX = 1.2 V VOD Setting (mV) 1 First Post Tap Pre-Emphasis Level 2 3 TX Term = 100 320 480 640 800 960
Note to Table 4–13:
(1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.
4
5
24% — — — —
61% 31% 20% — —
114% 55% 35% 23% 18%
— 86% 54% 36% 25%
— 121% 72% 49% 35%
DC Electrical Characteristics
Table 4–14 lists the Arria GX device family DC electrical characteristics.
Table 4–14. Arria GX Device DC Operating Conditions (Part 1 of 2) Symbol II IOZ Parameter Input pin leakage current Tri-stated I/O pin leakage current VCCINT supply current (standby) Conditions VI = VCCIOmax to 0 V (2) VO = VCCIOmax t o 0 V ( 2) VI = ground, no load, no toggling inputs TJ = 25 °C VI = ground, no load, no toggling inputs TJ = 25 °C, VCCPD = 3.3V VI = ground, no load, no toggling inputs TJ = 25 °C All All EP1AGX20/35 EP1AGX50/60 EP1AGX90 EP1AGX20/35 EP1AGX50/60 EP1AGX90 EP1AGX20/35 EP1AGX50/60 EP1AGX90 (Note 1) Device Min –10 –10 — — — — — — — — — Typ — — 0.30 0.50 0.62 2.7 3.6 4.3 4.0 4.0 4.0 Max 10 10 (3) (3) (3) (3) (3) (3) (3) (3) (3) Units A A A A A mA mA mA mA mA mA
ICCINT0
ICCPD0
VCCPD supply current (standby)
ICCI00
VCCIO supply current (standby)
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Table 4–14. Arria GX Device DC Operating Conditions (Part 2 of 2) Symbol Parameter Conditions Vi = 0, VCCIO = 3.3 V Value of I/O pin pull-up resistor before and during configuration RCONF (4) Recommended value of I/O pin external pull-down resistor before and during configuration
Notes to Table 4–14:
(Note 1) Device — — — — — — Min 10 15 30 40 50 — Typ 25 35 50 75 90 1 Max 50 70 100 150 170 2 Units k k k k k k
Vi = 0, VCCIO = 2.5 V Vi = 0, VCCIO = 1.8 V Vi = 0, VCCIO = 1.5 V Vi = 0, VCCIO = 1.2 V —
(1) Typical values are for TA = 25 °C, VCCINT = 1.2 V, and VCCIO = 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V. (2) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, 1.5, and 1.2 V). (3) Maximum values depend on the actual TJ and design utilization. For maximum values, refer to the Excel-based PowerPlay Early Power Estimator (available at PowerPlay Early Power Estimators (EPE) and Power Analyzer) or the Quartus® II PowerPlay Power Analyzer feature for maximum values. For more information, refer to “Power Consumption” on page 4–25. (4) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
I/O Standard Specifications
Table 4–15 through Table 4–38 show the Arria GX device family I/O standard specifications.
Table 4–15. LVTTL Specifications Symbol VCCIO ( 1) VIH VIL VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions — — — IOH = –4 mA (2) IOL = 4 mA (2) Minimum 3.135 1.7 –0.3 2.4 — Maximum 3.465 4.0 0.8 — 0.45 Units V V V V V
Notes to Table 4–15:
(1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. (2) This specification is supported across all the programmable drive strength settings available for this I/O standard.
Table 4–16. LVCMOS Specifications Symbol VCCIO (1) VIH VIL VOH VOL
Notes to Table 4–16:
(1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. (2) This specification is supported across all the programmable drive strength available for this I/O standard.
Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions — — — VCCIO = 3.0, IOH = –0.1 mA ( 2) VCCIO = 3.0, IOL = 0.1 mA (2)
Minimum 3.135 1.7 –0.3 VCCIO – 0.2 —
Maximum 3.465 4.0 0.8 — 0.2
Units V V V V V
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Table 4–17. 2.5-V I/O Specifications Symbol VCCIO (1) VIH VIL VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions — — — I OH = –1 mA (2) I OL = 1 mA (2) Minimum 2.375 1.7 –0.3 2.0 — Maximum 2.625 4.0 0.7 — 0.4 Units V V V V V
Notes to Table 4–17:
(1) The Arria GX device VCCIO voltage level support of 2.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard.
Table 4–18. 1.8-V I/O Specifications Symbol VCCIO ( 1) VIH VIL VOH VOL
Notes to Table 4–18:
(1) The Arria GX device VCCIO voltage level support of 1.8 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in Arria GX Architectur e chapter.
Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions — — — I OH = –2 mA (2) I OL = 2 mA (2)
Minimum 1.71 0.65 × VCCIO –0.3 VCCIO – 0.45 —
Maximum 1.89 2.25 0.35 × VCCIO — 0.45
Units V V V V V
Table 4–19. 1.5-V I/O Specifications Symbol VCCIO ( 1) VIH VIL VOH VOL
Notes to Table 4–19:
(1) The Arria GX device VCCIO voltage level support of 1.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architectur e chapter.
Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions — — — IOH = –2 mA (2) IOL = 2 mA (2)
Minimum 1.425 0.65 VCCIO –0.3 0.75 VCCIO —
Maximum 1.575 VCCIO + 0.3 0.35 VCCIO — 0.25 VCCIO
Units V V V V V
Figure 4–5 and Figure 4–6 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS and LVPECL).
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Figure 4–5. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground
Differential Waveform
VID p−n=0V VID (Peak-to-Peak) VID
Figure 4–6. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground
Differential Waveform
VOD p−n=0V VOD
Table 4–20. 2.5-V LVDS I/O Specifications Symbol VCCIO VID VICM VOD VOCM RL Parameter I/O supply voltage for left and right I/O banks (1, 2, 5, and 6) Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input discrete resistor (external to Arria GX devices) Conditions — — — RL = 100 RL = 100 — Minimum 2.375 100 200 250 1.125 90 Typical 2.5 350 1,250 — — 100 Maximum 2.625 900 1,800 450 1.375 110 Units V mV mV mV V
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Table 4–21. 3.3-V LVDS I/O Specifications Symbol VCCIO ( 1) VID VICM VOD VOCM RL
Note to Table 4–21:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V CCINT, not VCCIO. The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT t o 3.3 V.
Parameter I/O supply voltage for top and bottom PLL banks (9, 10, 11, and 12) Input differential voltage swing (single-ended) Input common mode voltage Output common mode voltage Receiver differential input discrete resistor (external to Arria GX devices)
Conditions — — — RL = 100 —
Minimum 3.135 100 200 250 840 90
Typical 3.3 350 1,250 — — 100
Maximum 3.465 900 1,800 710 1,570 110
Units V mV mV mV mV
Output differential voltage (single-ended) RL = 100
Table 4–22. 3.3-V PCML Specifications Symbol VCCIO VID VICM VOD VOD VOCM VOCM VT R1 R2 Parameter I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Change in VO D between high and low Output common mode voltage Change in VO C M between high and low Output termination voltage Output external pull-up resistors Output external pull-up resistors Minimum 3.135 300 1.5 300 — 2.5 — — 45 45 Typical 3.3 — — 370 — 2.85 — VC C I O 50 50 Maximum 3.465 600 3.465 500 50 3.3 50 — 55 55 Units V mV V mV mV V mV V
Table 4–23. LVPECL Specifications Parameter VCCIO ( 1) VID VICM VOD VOCM RL
Note to Table 4–23:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO . The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Conditions I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input resistor
Minimum — — — RL = 100 RL = 100 —
Typical 3.135 300 1.0 525 1,650 90
Maximum 3.3 600 — — — 100
Units 3.465 1,000 2.5 970 2,250 110
Parameter V mV V mV mV
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Table 4–24. 3.3-V PCI Specifications Symbol VCCIO VIH VIL VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions — — — IOUT = –500 A IOUT = 1,500 A Minimum 3.0 0.5 VCCIO –0.3 0.9 VCCIO — Typical 3.3 — — — — Maximum 3.6 VCCIO + 0.5 0.3 VCCIO — 0.1 VCCIO Units V V V V V
Table 4–25. PCI-X Mode 1 Specifications Symbol VCCIO VIH VIL VIPU VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage High-level output voltage Low-level output voltage Conditions — — — — I OUT = –500 A I OUT = 1,500 A Minimum 3.0 0.5 VCCIO –0.3 0.7 VCCIO 0.9 VCCIO — Maximum 3.6 VCCIO + 0.5 0.35 VCCIO — — 0.1 VCCIO Units V V V V V V
Table 4–26. SSTL-18 Class I Specifications Symbol VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL Parameter Output supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage Conditions — — — — — — — I OH = –6.7 mA (1) I OL = 6.7 mA ( 1) Minimum 1.71 0.855 VREF – 0.04 VREF + 0.125 — VREF + 0.25 — VTT + 0.475 — Typical 1.8 0.9 VREF — — — — — — Maximum 1.89 0.945 VREF + 0.04 — VREF – 0.125 — VREF – 0.25 — VTT – 0.475 Units V V V V V V V V V
Note to Table 4–26:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architectur e chapter.
Table 4–27. SSTL-18 Class II Specifications Symbol VCCIO VREF VTT VIH ( DC) VIL ( DC) VIH ( AC) VIL (AC) Parameter Output supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage Conditions — — — — — — — Minimum 1.71 0.855 VREF – 0.04 VREF + 0.125 — VREF + 0.25 — Typical 1.8 0.9 VREF — — — — Maximum 1.89 0.945 VREF + 0.04 — VREF – 0.125 — VREF – 0.25 Units V V V V V V V
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Table 4–27. SSTL-18 Class II Specifications Symbol VOH VOL Parameter High-level output voltage Low-level output voltage Conditions I OH = –13.4 mA (1) I OL = 13.4 mA (1) Minimum VCCIO – 0.28 — Typical — — Maximum — 0.28 Units V V
Note to Table 4–27:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architectur e chapter.
Table 4–28. SSTL-18 Class I & II Differential Specifications Symbol VCCIO VSWING (DC) VX ( AC) VSWING ( AC) VISO VISO VOX (AC) Parameter Output supply voltage DC differential input voltage AC differential input cross point voltage AC differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation AC differential cross point voltage Minimum 1.71 0.25 (VCCIO/2) – 0.175 0.5 — — (VCCIO/2) – 0.125 Typical 1.8 — — — 0.5 VCC IO 200 — Maximum 1.89 — (VCCIO/2) + 0.175 — — — (VCCIO/2) + 0.125 Units V V V V V mV V
Table 4–29. SSTL-2 Class I Specifications Symbol VCCIO VTT VREF VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Note to Table 4–29:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arr ia GX Architecture chapter.
Parameter Output supply voltage Termination voltage Reference voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions — — — — — — — IOH = –8.1 mA ( 1) IOL = 8.1 mA (1)
Minimum 2.375 VREF – 0.04 1.188 VREF + 0.18 –0.3 VREF + 0.35 — VTT + 0.57 —
Typical 2.5 VREF 1.25 — — — — — —
Maximum 2.625 VREF + 0.04 1.313 3.0 VREF – 0.18 — VREF – 0.35
Units V V V V V V V V
VTT – 0.57
V
Table 4–30. SSTL-2 Class II Specifications (Part 1 of 2) Symbol VCC IO VTT VREF VIH (DC) Parameter Output supply voltage Termination voltage Reference voltage High-level DC input voltage Conditions — — — — Minimum 2.375 VREF – 0.04 1.188 VREF + 0.18 Typical 2.5 VREF 1.25 — Maximum 2.625 VREF + 0.04 1.313 VCCIO + 0.3 Units V V V V
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Table 4–30. SSTL-2 Class II Specifications (Part 2 of 2) Symbol VIL (DC) VIH (AC) VIL (AC) VOH VOL
Note to Table 4–30:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architectur e chapter.
Parameter Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions — — — IOH = –16.4 mA ( 1) I OL = 16.4 mA (1)
Minimum –0.3 VREF + 0.35 — VTT + 0.76 —
Typical — — — — —
Maximum VREF – 0.18 — VREF – 0.35 — VTT – 0.76
Units V V V V V
Table 4–31. SSTL-2 Class I & II Differential Specifications Symbol VCCIO VSWING (DC) VX ( AC) VSWING (AC) VISO VISO VOX (AC)
Note to Table 4–31:
(Note 1) Minimum 2.375 0.36 (VCCIO/2) – 0.2 0.7 — — (VCCIO/2) – 0.2 Typical 2.5 — — — 0.5 VCCIO 200 — Maximum 2.625 — (VCCIO /2) + 0.2 — — — (VCCIO /2) + 0.2 Units V V V V V mV V
Parameter Output supply voltage DC differential input voltage AC differential input cross point voltage AC differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation AC differential output cross point voltage
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter.
Table 4–32. 1.2-V HSTL Specifications Symbol VCCIO VREF VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL Parameter Output supply voltage Reference voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage Minimum 1.14 0.48 VCCIO VREF + 0.08 –0.15 VREF + 0.15 –0.24 VREF + 0.15 –0.15 Typical 1.2 0.5 VCCIO — — — — — — Maximum 1.26 0.52 VCCIO VCCIO + 0.15 VREF – 0.08 VCCIO + 0.24 VREF – 0.15 VCCIO + 0.15 VREF – 0.15 Units V V V V V V V V
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Table 4–33. 1.5-V HSTL Class I Specifications Symbol VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Note to Table 4–33:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architect ure chapter.
Parameter Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions — — — — — — — IOH = 8 mA (1) IOH = –8 mA ( 1)
Minimum 1.425 0.713 0.713 VREF + 0.1 –0.3 VREF + 0.2 — VCCIO – 0.4 —
Typical 1.5 0.75 0.75 — — — — — —
Maximum 1.575 0.788 0.788 — VREF – 0.1 — VREF – 0.2 — 0.4
Units V V V V V V V V V
Table 4–34. 1.5-V HSTL Class II Specifications Symbol VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Note to Table 4–34:
(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architect ure chapter.
Parameter Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions — — — — — — — IOH = 16 mA ( 1) I OH = –16 mA ( 1)
Minimum 1.425 0.713 0.713 VREF + 0.1 –0.3 VREF + 0.2 — VCCIO – 0.4 —
Typical 1.50 0.75 0.75 — — — — — —
Maximum 1.575 0.788 0.788 — VREF – 0.1 — VREF – 0.2 — 0.4
Units V V V V V V V V V
Table 4–35. 1.5-V HSTL Class I & II Differential Specifications Symbol VCCIO VDIF (DC) VCM (DC) VDIF (AC) VOX (AC) Parameter I/O supply voltage DC input differential voltage DC common mode input voltage AC differential input voltage AC differential cross point voltage Minimum 1.425 0.2 0.68 0.4 0.68 Typical 1.5 — — — — Maximum 1.575 — 0.9 — 0.9 Units V V V V V
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Table 4–36. 1.8-V HSTL Class I Specifications Symbol VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL Parameter Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage Conditions — — — — — — — IOH = 8 mA (1) IOH = –8 mA (1) Minimum 1.71 0.85 0.85 VREF + 0.1 –0.3 VREF + 0.2 — VCCIO – 0.4 — Typical 1.80 0.90 0.90 — — — — — — Maximum 1.89 0.95 0.95 — VREF – 0.1 — VREF – 0.2 — 0.4 Units V V V V V V V V V
Note to Table 4–36:
(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture chapter.
Table 4–37. 1.8-V HSTL Class II Specifications Symbol VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Note to Table 4–37:
(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architect ure chapter in volume 1 of the Arria GX Device Handbook.
Parameter Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions — — — — — — — I OH = 16 mA (1) IOH = –16 mA ( 1)
Minimum 1.71 0.85 0.85 VREF + 0.1 –0.3 VREF + 0.2 — VCCIO – 0.4 —
Typical 1.80 0.90 0.90 — — — — — —
Maximum 1.89 0.95 0.95 — VREF – 0.1 — VREF – 0.2 — 0.4
Units V V V V V V V V V
Table 4–38. 1.8-V HSTL Class I & II Differential Specifications Symbol VCCIO VDIF (DC) VCM (DC) VDIF (AC) VOX (AC) Parameter I/O supply voltage DC input differential voltage DC common mode input voltage AC differential input voltage AC differential cross point voltage Minimum 1.71 0.2 0.78 0.4 0.68 Typical 1.80 — — — — Maximum 1.89 — 1.12 — 0.9 Units V V V V V
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Chapter 4: DC and Switching Characteristics Operating Conditions
Bus Hold Specifications
Table 4–39 shows the Arria GX device family bus hold specifications.
Table 4–39. Bus Hold Parameters VC CIO Level Parameter Conditions 1.2 V Min Low sustaining current High sustaining current Low overdrive current High overdrive current Bus-hold trip point VIN > VIL ( maximum) VIN < VIH (minimum) 0V ). For example, and .pof file. Initial Capital Letters “Subheading Title” Indicates keyboard keys and menu names. For example, Delete key and the Options menu. Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”
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