EN5322QI

Enpirion® Power Datasheet EN5322QI 2A PowerSoC Synchronous Buck DC-DC Converter with Integrated Inductor General Description Ordering Information Part Number The EN5322 is a high efficiency synchronous buck converter with integrated inductor, PWM controller, MOSFETS, and compensation providing the smallest possible solution size. • Revolutionary Integrated Inductor • Total Solution Footprint as Small as 50 mm2 • 4 mm x 6 mm x 1.1 mm QFN Package • 4 MHz Fixed Switching Frequency • High Efficiency, up to 95 % • Low Ripple Voltage; 8 mVP-P Typical • 2% Initial VOUT Accuracy with VID Codes • 2% Initial 0.6 V Feedback Voltage Accuracy • 2.4 V to 5.5 V Input Voltage Range • 2 A Continuous Output Current Capability • Fast Transient Response • Low Dropout Operation: 100 % Duty Cycle • Power OK Signal with 5 mA Sink Capability • Dynamic Voltage Scaling with VID Codes • 17 A Typical Shutdown Current • Under Voltage Lockout, Over Current, Short Circuit, and Thermal Protection • RoHS Compliant; MSL 3 260 °C Reflow Three VID output voltage select pins provide seven pre-programmed output voltages along with an option for external resistor divider. Output voltage can be programmed on-the-fly to provide fast, dynamic voltage scaling with smooth transitions between VID programmed output voltages. Applications • • • • Package -40 to +85 24-pin QFN T&R QFN Evaluation Board Features The 4 MHz operation allows for the use of tiny MLCC capacitors. It also enables a very wide control loop bandwidth providing excellent transient performance and reduced output impedance. The internal compensation is designed for unconditional stability across all operating conditions. • Temp Rating (°C) EN5322QI EVB-EN5322QI Point of Load Regulation for Low Power Processors, Network Processors, DSPs’ FPGAs and ASICs Replacement of LDOs Noise Sensitive Applications such as A/V and RF Computing, Computer Peripherals, Storage, Networking, and Instrumentation DSL, STB, DVR, DTV, and iPC Application Circuit ON VIN OFF ENABLE VSENSE PVIN CIN VS0 VS1 10 uF EN5322 POK VS2 PGND AVIN VOUT VOUT COUT 47 uF PGND AGND 1 uF Figure 1. Typical Application Circuit 1 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI Absolute Maximum Ratings CAUTION: Absolute maximum ratings are stress ratings only. Functional operation beyond recommended operating conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Absolute Maximum Electrical Ratings MIN Voltages on: PVIN, AVIN, VOUT Voltages on: VSENSE, VS0, VS1, VS2, ENABLE, POK Voltage on: VFB ESD Rating (Human Body Model) ESD Rating (Charge Device Model) MAX -0.3 V -0.3 V -0.3 V 2 kV 500 V 6.5 V VIN 2.7 V -40 °C -65 °C +85 °C +150 °C +260 °C Absolute Maximum Thermal Ratings Ambient Operating Range Storage Temperature Range Reflow Peak Body Temperature MSL3 (10 s) Thermal Characteristics SYMBOL PARAMETER MIN TYP MAX Thermal Shutdown TSD 155 Thermal Shutdown Hysteresis TSDH 15 Thermal Resistance: Junction to Case (0 LFM) 6 JC Thermal Resistance: Junction to Ambient (0 LFM)* 36 JA * Based on a 2 oz. copper board and proper thermal design in line with JEDEC EIJ-JESD51 standards UNITS °C °C °C/W °C/W Recommended Operating Conditions PARAMETER SYMBOL MIN Input Voltage Range VIN 2.4 Output Voltage Range VOUT 0.6 Output Current ILOAD 0 Operating Junction Temperature TJ -45 Note: VDROPOUT is defined as (ILOAD x Dropout Resistance) including temperature effect. VIN MAX 5.5 - VDROPOUT 2 +125 UNITS V V A °C Electrical Characteristics VIN = 5 V and TA = 25 °C, unless otherwise noted. PARAMETER Operating Input Voltage Under Voltage Lockout UVLO Hysteresis Output Voltage with VID Codes (Note 1) SYMBOL VIN VUVLO VOUT TEST CONDITIONS VIN going low to high TA = 25 °C; VIN = 5V ILOAD = 100 mA VS2 VS1 VS0 VOUT (V) 0 0 0 3.3 0 0 1 2.5 0 1 0 1.8 0 1 1 1.5 1 0 0 1.25 1 0 1 1.2 1 1 0 0.8 2 03454 MIN 2.4 March 15, 2018 TYP MAX 5.5 2.2 0.15 -2.0 -2.0 -2.0 -2.0 -2.0 -2.0 -2.0 +2.0 +2.0 +2.0 +2.0 +2.0 +2.0 +2.0 UNITS V V V % www.altera.com/enpirion Rev H EN5322QI PARAMETER VFB Voltage SYMBOL VFB TA = 25 °C; VIN = 5V ILOAD = 100 mA, VS0 = VS1 = VS2 = 1 VOUT 2.4 V  VIN  5.5 V, ILOAD = 0 ~ 2 A, -40°C  TA  +85°C VS2 VS1 VS0 VOUT (V) 0 0 0 3.3 0 0 1 2.5 0 1 0 1.8 0 1 1 1.5 1 0 0 1.25 1 0 1 1.2 1 1 0 0.8 Output Voltage with VID Codes (Note 1) VFB Voltage VFB Dynamic Voltage Slew Rate Soft Start Slew Rate Soft Start Time VFB, ENABLE, VS0-VS2 Pin Input Current (Note 2) ENABLE, VS0-VS2 Voltage Threshold POK Upper Threshold POK Upper Threshold POK Lower Threshold POK Lower Threshold POK Low Voltage POK Pin VOH Leakage Current Shutdown Current Quiescent Current Quiescent Current 2.4 V  VIN  5.5 V, ILOAD = 0 ~ 2 A, VS0 = VS1 = VS2 = 1, -40°C  TA  +85°C Switching between VID settings VID Mode VOUT Programming VFB Mode VOUT Programming MIN TYP MAX UNITS 0.588 0.600 0.612 V 0.582 0.600 0.975 0.975 0.78 1.5 1.5 1.2 Logic Low Logic High VOUT Rising VOUT Falling VOUT Rising VOUT Falling ISINK = 5 mA, -40°C  TA  +85°C 0.0 1.4 111 102 92 90 0.15 POK High, -40°C  TA  +85°C ENABLE Low No Switching Switching, VOUT = 1.2 V 2.4 V  VIN  5.5 V, -40°C  TA  +85°C 2.1 FOSC COUT = 1 x 47 F 1206 X5R MLCC, VOUT = 1.2 V, ILOAD = 2 A Output Ripple Voltage VRIPPLE COUT = 2 x 22 F 0805 X5R MLCC, VOUT = 1.2 V, ILOAD = 2 A Note 1: The tolerances hold true only if VIN is greater than (VOUT + VDROPOUT). Note 2: VFB, ENABLE, VS0-VS2 pin input current specification is guaranteed by design. 3 03454 +3.0 +3.0 +3.0 +3.0 +3.0 +3.0 +3.0 -3.0 -3.0 -3.0 -3.0 -3.0 -3.0 -3.5 -40°C  TA  +85°C Current Limit Threshold PFET On Resistance NFET On Resistance Dropout Resistance Operating Frequency TEST CONDITIONS March 15, 2018 0.618 2.025 2.025 1.62 % V V/ms V/ms ms +/-40 nA 0.4 VIN V 0.4 % % % % V 500 nA 17 800 15 A A mA 3.0 A 160 60 200 4 m m m MHz 300 14 mVP-P 8 mVP-P www.altera.com/enpirion Rev H EN5322QI Pin Configuration Figure 2. Pin Diagram, Top View. Pin Description PIN NAME 1, 21-24 NC(SW) 2-3, 8-9 PGND 4-7 VOUT 10-12 VS2-0 13 VSENSE 14 VFB 15 AGND 16 AVIN 17 POK 18 ENABLE FUNCTION No Connect. These pins are internally connected to the common drain output of the internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. Input/Output Power Ground. Connect these pins to the ground electrode of the input and output filter capacitors. Refer to Layout Considerations section for details. Voltage and Power Output. Connect these pins to output capacitor(s). Output Voltage Select. These pins set one of seven preset output voltages and the external divider option (refer to Electrical Characteristics table for more details), and can be directly pulled up to VIN or pulled down to GND; these pins must not be left floating. Sense Pin for Internally Programmed Output Voltages with VID Codes. For either VID code or external resistor divider applications, connect this pin to the last local output filter capacitor for internal compensation. Feedback Pin for External Voltage Divider Network. Connect a resistor divider to this pin to set the output voltage. Use 340 k, 1% or better for the upper resistor. Analog Ground for the Controller Circuits Analog Voltage Input for the Controller Circuits. Connect this pin to the input power supply. Use a 1 F bypass capacitor on this pin. Power OK with an Open Drain Output. Refer to Power OK section. Input Enable. A logic high signal on this pin enables the output and initiates a soft start. A logic low signal disables the output and discharges the output to GND. The ENABLE pin should not be left floating as it could be in an unknown and random state. It is recommended to enable the device after both PVIN and AVIN is in regulation. See ENABLE operation for details. 4 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI PIN NAME 19-20 PVIN FUNCTION Input Power Supply. Connect to input supply. Decouple with input capacitor(s) to PGND. Functional Block Diagram PVIN POK UVLO POK Thermal Limit Current Limit ENABLE NC (SW) Soft Start P-Drive Logic (-) VOUT PWM Comp (+) N-Drive PGND VSENSE Sawtooth Generator Compensation Network (-) Switch VFB Error Amp (+) DAC Voltage Select VREF BIAS Package Boundary AVIN AGND VS0 VS1 VS2 Figure 3. Functional Block Diagram. 5 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI RPOK* 100k POK ON OFF VIN ENABLE CIN VS0 VS1 10 uF VOUT VSENSE PVIN VOUT EN5322 POK VS2 PGND AVIN COUT 47 uF PGND AGND 1 uF * Leave RPOK open if the POK function is not used. Figure 4. Typical Application Circuit with VID Codes. (NOTE: Enable can be separated from PVIN if the application requires it) Typical Performance Characteristics Circuit of Figure 4, VIN = 5 V, VOUT = 1.2 V and TA = 25°C, unless otherwise noted. Efficiency vs. Load Current (Vin = 3.3V) 95 95 90 90 85 85 Efficiency (%) Efficiency (%) Efficiency vs. Load Current (Vin = 5.0V) 80 75 70 65 60 75 70 65 60 55 55 50 50 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 Load Current (A) Load Current (A) Top to Bottom: VOUT = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V 6 03454 80 March 15, 2018 Top to Bottom: VOUT = 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V www.altera.com/enpirion Rev H EN5322QI Quiescent Current (No Switching) vs. Input Voltage Quiescent Current (mA) Quiescent Current (Switching) vs. Input Voltage Quiescent Current (uA) 840 820 800 780 760 740 2 3 4 5 18 16 14 12 10 8 2 6 3 6 Load Regulation (Vin = 5 V) Load Regulation (Vin = 5 V) 1.208 3.304 1.204 Output Voltage (V) Output Voltage (V) 5 Input Voltage (V) Input Voltage (V) 1.200 1.196 1.192 1.188 3.300 3.296 3.292 3.288 3.284 1.184 0 0.4 0.8 1.2 1.6 0 2 0.4 0.8 1.2 1.6 2 Load Current (A) Load Current (A) Output Ripple at 2 A Load (CH2: VOUT) Output Ripple at 2 A Load (CH2: VOUT) VIN = 3.3 V, VOUT = 1.2 V, COUT = 1 x 47 F VIN = 3.3 V, VOUT = 1.2 V, COUT = 2 x 22 F 7 03454 4 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI Transient Response at VIN = 5 V VOUT = 1.2V, COUT = 1 x 47 F (0-2 A Load Step, slew rate ≥ 10A/uS) CH1: VOUT, CH4: ILOAD Transient Response at VIN = 5 V VOUT = 3.3V, COUT = 1 x 47 F (0-2 A Load Step, slew rate ≥ 10A/uS) CH1: VOUT, CH4: ILOAD VOUT Scaling with VID Codes at VIN = 5 V (VOUT = 1.2 V – 2.5 V, IOUT = 0 – 2 A) CH1: VS2, CH2: VOUT, CH3: POK VOUT Scaling with VID Codes at VIN = 3.3 V (VOUT = 1.2 V – 2.5 V, IOUT = 0 – 2 A) CH1: VS2, CH2: VOUT, CH3: POK Power Up/Down at No Load (VIN = 5 V, VOUT = 1.2 V) CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR Power Up/Down at 0.6  Load (VIN = 5 V, VOUT = 1.2 V) CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR 8 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI Output Over Load at No Load (VIN = 5 V, VOUT = 1.2 V) CH2: VOUT, CH3: POK, CH4: IINDUCTOR Output Over Load at 2 A Load (VIN = 5 V, VOUT = 1.2 V) CH2: VOUT, CH3: POK, CH4: IINDUCTOR Output Over Load at No Load (VIN = 5 V, VOUT = 1.2 V) CH2: VOUT, CH3: POK, CH4: IINDUCTOR Output Over Load at 2 A Load (VIN = 5 V, VOUT = 1.2 V) CH2: VOUT, CH3: POK, CH4: IINDUCTOR Functional Description The EN5322 leverages advanced CMOS technology to provide high switching frequency, while also maintaining high efficiency. The converter uses voltage mode control to provide high noise immunity, low output impedance and excellent load transient response. No external compensation components are needed for most applications. Packaged in a 4 mm x 6 mm x 1.1 mm QFN, the EN5322 provides a high degree of flexibility in circuit design while maintaining a very small footprint. High switching frequency allows for the use of very small MLCC input and output filter capacitors. Output voltage is chosen from one of seven preset values via a three-pin VID voltage select scheme. An external divider option enables the selection of any output voltage  0.6 V. The VID pins can be toggled dynamically to 9 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI implement glitch-free dynamic voltage scaling between any two VID preset values. Excess bulk capacitance on the output of the device can cause an over-current condition at startup. POK monitors the output voltage and signals if it is within ±10% of nominal. Protection features include under voltage lockout (UVLO), over current protection, short circuit protection, and thermal overload protection. When operating in VID mode, the maximum total capacitance on the output, including the output filter capacitor and bulk and decoupling capacitance, at the load, is given as: COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 1000uF Stability over Wide Range of Operating Conditions The EN5322 utilizes an internal compensation network and is designed to provide stable operation over a wide range of operating conditions. To improve transient performance or reduce output voltage ripple with dynamic loads you have the option to add supplementary capacitance to the output. When programming VOUT using the VID pins, the EN5322 is stable with up to 60 F of output capacitance without compensation adjustment. Additional output capacitance above 60 F can be accommodated with compensation adjustment depending on the application. When programming VOUT with the resistor divider option, the maximum output capacitance may be limited. Please refer to the section on soft start for more details. The high switching frequency allows for a wide control loop bandwidth. When the EN5322QI output voltage is programmed using and external resistor divider the maximum total capacitance on the output is given as: COUT_TOTAL_MAX = 1.867x10-3/VOUT Farads The above number and formula assume a no load condition at startup. Over Current/Short Circuit Protection When an over current condition occurs, VOUT is pulled low. This condition is maintained for a period of 1.2 ms and then a normal soft start cycle is initiated. If the over current condition still persists, this cycle will repeat. Under Voltage Lockout An under voltage lockout circuit will hold off switching during initial power up until the input voltage reaches sufficient level to ensure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable switching. Hysteresis is included to prevent chattering between UVLO high and low states. Soft Start The EN5322QI has an internal soft-start circuit that controls the ramp of the output voltage. The control circuitry limits the VOUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. Enable The EN5322QI has two soft start operating modes. When VOUT is programmed using a preset voltage in VID mode, the device has a constant slew rate. When the EN5322QI is configured in external resistor divider mode, the device has a constant VOUT ramp time. Output voltage slew rate and ramp time is given in the Electrical Characteristics Table. The ENABLE pin provides means to shut down the converter or initiate normal operation. A logic high will enable the converter to go through the soft start cycle and regulate the output voltage to the desired value. A logic low will allow the device to discharge the output and go into shutdown mode for minimal power consumption. When the output is discharged, an auxiliary NFET turns on and limits the 10 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI discharge current to 300 mA or below. In shutdown mode, the device typically drains 17A. The ENABLE pin should not be left floating as it could be in an unknown and random state. It is recommended to enable the device after both PVIN and AVIN is in regulation. At extremely cold conditions below -30°C, the controller may not be properly powered if ENABLE is tied directly to AVIN during startup. It is recommended to use an external RC circuit to delay the ENABLE voltage rise so that the internal controller has time to startup into regulation (see circuit below). The RC circuit may be adjusted so that AVIN and PVIN are above UVLO before ENABLE is high. The startup time will be delayed by the extra time it takes for the capacitor voltage to reach the ENABLE threshold. Thermal Shutdown When excessive power is dissipated in the device, its junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature 155 °C, the thermal shutdown circuit turns off the converter, allowing the device to cool. When the junction temperature drops 15 °C, the device will be reenabled and go through a normal startup process. Power OK The EN5322 provides an open drain output to indicate if the output voltage stays within 92% to 111% of the set value. Within this range, the POK output is allowed to be pulled high. Outside this range, POK remains low. However, during transitions such as power up, power down, and dynamic voltage scaling, the POK output will not change state until the transition is complete for enhanced noise immunity. AVIN The POK has 5 mA sink capability for events where it needs to feed a digital controller with standard CMOS inputs. When POK is pulled high, the pin leakage current is as low as 500 nA maximum over temperature. This allows a large pull up resistor such as 100 k to be used for minimal current consumption in shutdown mode. 1k ENABLE 1µF The POK output can also be conveniently used as an ENABLE input of the next stage for power sequencing of multiple converters. Figure 5: ENABLE Delay Circuit 11 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI RPOK* 100k POK ON VIN OFF ENABLE PVIN CIN VS0 VS1 10 uF VOUT EN5322 POK VS2 PGND AVIN VOUT VSENSE Ra 340k VFB AGND COUT 47 uF PGND Rb 1 uF * Leave RPOK open if the POK function is not used. Figure 6. Typical Application Circuit with External Resistor Divider. (NOTE: Enable can be separated from PVIN if the application requires it) Application Information values is indeterminate. These pins must not be left floating. Setting the Output Voltage To provide the highest degree of flexibility in choosing output voltage, the EN5322QI uses a 3 pin VID (Voltage ID) output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to use an external voltage divider. Figure 4 shows a typical application circuit with VID codes. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. Table 1. VID voltage select settings. VS1 0 0 1 1 0 0 1 VS0 0 1 0 1 0 1 0 1 1 1 VOUT 3.3V 2.5V 1.8V 1.5V 1.25V 1.2V 0.8V User Selectable External Voltage Divider Table 1 shows the various VS0-VS2 pin logic states and the associated output voltage levels. A logic “1” indicates a connection to VIN or to a “high” logic voltage level. A logic “0” indicates a connection to ground or to a “low” logic voltage level. These pins can be either hardwired to VIN or GND or alternatively can be driven by standard logic levels. Logic low is defined as VLOW  0.4V. Logic high is defined as VHIGH  1.4V. Any level between these two As described above, the external voltage divider option is chosen by connecting the VS0, VS1, and VS2 pins to VIN or logic “high”. The EN5322QI uses a separate feedback pin, VFB, when using the external divider. VSENSE must be connected to VOUT as indicated in Figure 6. If the external voltage divider option is chosen, use 340 k, 1% or better for the upper resistor 12 03454 VS2 0 0 0 0 1 1 1 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI A 10 F, 10 V, 0805 MLC capacitor is needed on PVIN for all applications. A 1 F, 10 V, 0402 MLC capacitor on AVIN is needed for high frequency bypass to ensure clean chip supply for optimal performance. Ra. Then the value of the bottom resistor Rb in k is given as: Rb  204 k VOUT  0.6 A 47 F, 6.3 V, 1206 MLC capacitor is recommended on the output for most applications. The output ripple can be reduced by approximately 50% by using 2 x 22 F, 6.3V, 0805 MLC capacitors rather than 1 x 47 F. Where VOUT is the output voltage. Rb should also be a 1% or better resistor. Power-Up/Down Sequencing During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered down before the PVIN. It is recommended to follow the power-up and power-down sequencing to ensure that the EN5322QI is always sufficiently powered before the device begins operation. As described in the Soft Start section, there is a limitation on the maximum bulk capacitance that can be placed on the output of this device. Please refer to that section for more details. Table 2. Recommended input and output capacitors Description Mfg. P/N Taiyo Yuden LMK212BJ106KG 10F, 10V, CIN Murata GRM21BR71A106KE51L Pre-Bias Start-up The EN5322QI does not support startup into a pre-biased condition. Be sure the output capacitors are not charged or the output of the EN5322QI is not pre-biased when the EN5322QI is first enabled. COUT Input and Output Capacitor Selection Panasonic Taiyo Yuden Murata Kemet ECJ-2FB1A106K JMK316BJ476ML GRM31CR60J476ME19L C1206C476M9PACTU POK Pull Up Resistor Selection Low ESR MLC capacitors with X5R or X7R or equivalent dielectric should be used for input and output capacitors. Y5V or equivalent dielectrics lose too much capacitance with frequency, DC bias, and temperature. Therefore, they are not suitable for switchmode DC-DC converter filtering, and must be avoided. POK can be pulled up through a resistor to any voltage source as high as VIN. The simplest way is to connect POK to the power input of the converter through a resistor. A 100 k pull up resistor is typically recommended for most applications for minimal current drain from the voltage source and good noise immunity. POK can sink up to 5mA. 13 03454 X5R, 10%, 0805 47F, 6.3V, X5R, 20%, 1206 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI Layout Recommendations spokes to connect the vias to the ground plane. This connection provides the path for heat dissipation from the converter. Recommendation 4: Multiple small vias (the same size as the thermal vias discussed in recommendation 3) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias along the edge of the GND copper closest to the +V copper. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. Recommendation 5: AVIN is the power supply for the small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 7 this connection is made at the input capacitor. Connect a 1µF capacitor from the AVIN pin to AGND. Recommendation 6: The layer 1 metal under the device must not be more than shown in Figure 7. See the section regarding exposed metal on bottom of package. As with any switch-mode DC/DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 7: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace short in order to avoid noise coupling into the node. Recommendation 8: Keep RA, RB close to the VFB pin (See Figures 7). The VFB pin is a highimpedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the AGND pin instead of going through the GND plane. Recommendation 9: Altera provides schematic and layout reviews for all customer designs. Please contact local sales representatives for references to Power Applications Engineering support (www.altera.com/mysupport). Figure 7. Optimized Layout Recommendations Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN5322QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EN5322QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Recommendation 3: The thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or 14 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI Design Considerations for Lead-Frame Based Modules Exposed Metal Pads on Package Bottom QFN lead-frame based package technology utilizes exposed metal pads on the bottom of the package that provide improved thermal dissipation and low package thermal resistance, smaller package footprint and thickness, large lead size and pitch, and excellent lead coplanarity. As the EN5322 package is a fully integrated module consisting of multiple internal devices, the lead-frame provides circuit interconnection and mechanical support of these devices resulting in multiple exposed metal pads on the package bottom. Only the two large thermal pads and the perimeter leads are to be mechanically/electrically connected to the PCB through a SMT soldering process. All other exposed metal is to remain free of any interconnection to the PCB. Figure 8 shows the recommended PCB metal layout for the EN5322 package. A GND pad with a solder mask "bridge" to separate into two pads and 24 signal pads are to be used to match the metal on the package. The PCB should be clear of any other metal, including traces, vias, etc., under the package to avoid electrical shorting. Figure 8. Recommended Footprint for PCB. 15 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI Package and Mechanical Figure 9. EN5322QI Package Dimensions 16 03454 March 15, 2018 www.altera.com/enpirion Rev H EN5322QI Revision History Change(s) from Datasheet Rev F to Rev G in February 2014 - ENABLE functional description has been rewritten and updated to include delay circuit…………… Page 11 Change(s) from Datasheet Rev G to Rev H in February 2014 - Updated Typical Application Circuits to show that ENABLE is best toggled after PVIN is stable…......Page 1 - Updated Power Up/Down Sequencing description……………………….……………………..………...Page 13 Contact Information Altera Corporation 101 Innovation Drive San Jose, CA 95134 Phone: 408-544-7000 www.altera.com © 2014 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 17 03454 March 15, 2018 www.altera.com/enpirion Rev H