EN6347QI

EN6347QI 4A Voltage Mode Synchronous Buck PWM DC-DC Converter with Integrated Inductor Description Features The EN6347QI is a Power System on a Chip (PowerSoC) DC-DC converter. It integrates MOSFET switches, small-signal circuits, compensation, and the inductor in an advanced 4mm x 7mm QFN package. ! Integrated Inductor, MOSFETS, Controller ! Minimal external components. ! Up to 4A Continuous Output Current Capability. The EN6347QI is specifically designed to meet the precise voltage and fast transient requirements of present and future highperformance, low-power processor, DSP, FPGA, memory boards and system level applications in distributed power architecture. The device’s advanced circuit techniques, ultra high switching frequency, and proprietary integrated inductor technology deliver high-quality, ultra compact, non-isolated DC-DC conversion. ! 3 MHz operating frequency. Switching frequency can be phase locked to an external clock. ! High efficiency, up to 95%. ! Wide input voltage range of 2.5V to 6.6V. ! Light Load Mode with programmable set point. ! Output Enable pin and Power OK signal. The Enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. In addition, a reduction in the number of vendors required for the complete power solution helps to enable an overall system cost savings. ! Programmable soft-start time. ! Under Voltage Lockout, Over Current, Short Circuit and Thermal Protection. ! RoHS compliant, MSL level 3, 260C reflow. All Enpirion products are RoHS compliant and lead-free manufacturing environment compatible. ! Point of load regulation for processors, DSPs, FPGAs, and ASICs ! Noise sensitive applications such as A/V, RF and Gbit I/O ! Low voltage, distributed power architectures such as 0.8V, 1.0V, 1.2, 2.5V, 3.3V, 5V rails ! Blade servers, RAID storage systems, RA 0402 RB 0402 Applications Css 0402 CA 0402 EN6347QI LAN/SAN adapter cards, wireless base stations, industrial automation, test and Output Cap 47uF/1206 measurement, embedded computing, Input Cap 22uF/1206 Figure 1: Total Solution Footprint PWM mode (Not to scale) Total Area 75 mm2 communications, and multi-function printers. ! Ripple sensitive applications ! Beat frequency sensitive applications www.enpirion.com 05991 10/04/2011 Rev: B EN6347QI EN6347QI Pin Assignments (Top View) Figure 2: Typical Application Schematic (PWM mode) Ordering Information Temp Rating (°C) Package -40 to +85 38-pin QFN T&R -40 to +85 38-pin QFN T&R QFN Evaluation Board Part Number EN6347QI EN6347QI3 EN6347QI-E Figure 3: Pinout Diagram (Top View) NOTE: All pins must be soldered to PCB. Pin Description PIN NAME 1-2, 12, 34-38 NC(SW) 3-4, 22-25 NC 5-11 VOUT 13-18 PGND 19-21 PVIN 26 LLM/SYNC 27 ENABLE 28 POK 29 RLLM 30 SS 31 VFB 32 33 AGND AVIN 39 PGND FUNCTION NO CONNECT – These pins are internally connected to the common switching node of the internal MOSFETs. They are not to be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in damage to the device. NO CONNECT – These pins may be internally connected. Do not connect to each other or to any other electrical signal. Failure to follow this guideline may result in device damage. Regulated converter output. Connect these pins to the load and place output capacitor between these pins and PGND pins 13-15. Input/Output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT and PVIN pin descriptions for more details. Input power supply. Connect to input power supply. Decouple with input capacitor to PGND pins 16-18. Dual function pin providing LLM Enable and External Clock Synchronization (see Application Section). At static Logic HIGH, device will allow automatic engagement of light load mode. At static logic LOW, the device is forced into PWM only. A clocked input to this pin will synchronize the internal switching frequency to the external signal. If this pin is left floating, it will pull to a static logic high, enabling LLM. Input Enable. Applying logic high enables the output and initiates a soft-start. Applying logic low disables the output. Power OK is an open drain transistor used for power system state indication. POK is logic high when VOUT is within -10% of VOUT nominal. Programmable LLM engage resistor to AGND allows for adjustment of load current at which Light-Load Mode engages. Can be left open for PWM only operation. Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value of this capacitor determines the startup time. External Feedback Input. The feedback loop is closed through this pin. A voltage divider at VOUT is used to set the output voltage. The midpoint of the divider is connected to VFB. A phase lead capacitor from this pin to VOUT is also required to stabilize the loop. Analog Ground. This is the controller ground return. Connect to a quiet ground. Input power supply for the controller. Connect to input voltage at a quiet point. Device thermal pad to be connected to the system GND plane. See Layout Recommendations section. "Enpirion 2011 all rights reserved, E&OE 05991 2 10/04/2011 www.enpirion.com Rev: B EN6347QI Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER SYMBOL MIN MAX UNITS VIN -0.5 7.0 V Pin Voltages – ENABLE, POK, LLM/SYNC -0.5 VIN +0.3 V Pin Voltages – VFB, SS, RLLM -0.5 2.75 V -65 150 °C 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C ESD Rating - all pins (based on HBM) 2000 V Supply Voltage – PVIN, AVIN, VOUT Storage Temperature Range TSTG Maximum Operating Junction Temperature TJ-ABS Max Recommended Operating Conditions PARAMETER SYMBOL MIN MAX UNITS VIN 2.5 6.6 V Operating Junction Temperature TJ-OP - 40 125 °C Operating Ambient Temperature TAMB - 40 85 °C 260 °C MAX UNITS Input Supply Voltage Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A Thermal Characteristics PARAMETER SYMBOL MIN TYP Thermal Shutdown TSD 160 °C Thermal Shutdown Hysteresis TSDH 35 °C Thermal Resistance: Junction to Ambient (Note 1) #JA 30 °C/W Thermal Resistance: Junction to Case #JC 3 °C/W Note 1: Based on 2oz. external copper layers and proper thermal design in line with EIA/JEDEC JESD51-7 standard for high thermal conductivity boards. "Enpirion 2011 all rights reserved, E&OE 05991 3 10/04/2011 www.enpirion.com Rev: B EN6347QI Electrical Characteristics NOTE: VIN=6.6V over operating temperature range unless otherwise noted. Typical values are at TA = 25°C. PARAMETER SYMBOL TEST CONDITIONS Operating Input Voltage VIN Under Voltage Lock-out – VIN Rising VUVLOR Voltage above which UVLO is not asserted Under Voltage Lock-out – VIN Falling VUVLOF Voltage below which UVLO is asserted Shut-Down Supply Current IS Operating Quiescent Current MIN TYP 2.5 MAX UNITS 6.6 V 2.3 V 2.075 V ENABLE=0V 100 $A IQ LLM/SYNC = High 650 $A Feedback Pin Voltage EN6347QI EN6347QI3 VFB Feedback node voltage at: VIN = 5V, ILOAD = 0, TA = 25°C 0.7425 0.735 0.75 0.75 0.7575 0.765 V Feedback Pin Voltage EN6347QI EN6347QI3 VFB Feedback node voltage at: 2.5V VIN 6.6V 0A ILOAD 4A, TA = -40 to 85°C 0.735 0.7275 0.75 0.75 0.765 0.7725 V Feedback pin Input Leakage Current (Note 1) IFB VFB pin input leakage current -5 5 nA VOUT Rise Time (Note 1) tRISE Measured from when VIN > VUVLOR & ENABLE pin voltage crosses its logic high threshold to when VOUT reaches its final value. CSS = 15 nF 0.9 1.5 ms Soft Start Capacitor Range CSS_RANGE 68 nF Output Drop Out Voltage Resistance (Note 1) VDO RDO VINMIN - VOUT at Full load Input to Output Resistance 360 90 mV m% Continuous Output Current IOUT PWM mode LLM mode (Note 2) 4 4 A Over Current Trip Level IOCP VIN = 5V, VOUT = 1.2V Disable Threshold VDISABLE ENABLE pin logic low. 0.0 0.6 V ENABLE Threshold VENABLE ENABLE pin logic high 2.5V VIN 6.6V 1.8 VIN V ENABLE Lockout Time TENLOCKOUT ENABLE pin Input Current (Note 1) IENABLE Switching Frequency (Free Running) 1.2 10 240 60 0 0.002 6.5 A 3.2 ms ENABLE pin has ~180k% pull down 40 $A FSW Free Running frequency of oscillator 3 MHz External SYNC Clock Frequency Lock Range FPLL_LOCK Range of SYNC clock frequency SYNC Input Threshold – Low (LLM/SYNC PIN) VSYNC_LO SYNC Clock Logic Level SYNC Input Threshold – High (LLM/SYNC PIN) VSYNC_HI SYNC Clock Logic Level - (Note 3) POK Threshold POK Threshold voltage as a fraction of expected output voltage "Enpirion 2011 all rights reserved, E&OE 05991 4 10/04/2011 2.7 1.8 90 3.3 MHz 0.8 V 2.5 V % www.enpirion.com Rev: B EN6347QI PARAMETER SYMBOL POK Output low Voltage VPOKL POK Output Hi Voltage POK pin VOH leakage current (Note 1) TEST CONDITIONS MAX UNITS With 4mA current sink into POK 0.4 V VPOKH 2.5V VIN V IPOKL POK high 1 µA VIN MIN TYP 6.6V Minimum VIN-VOUT to ensure proper LLM operation LLM Engage Headroom LLM Logic Low (LLM/SYNC PIN) VLLM_LO LLM Static Logic Level LLM Logic High (LLM/SYNC PIN) VLLM_HI LLM Static Logic Level LLM/SYNC Pin Current 800 mV 0.3 V 1.5 LLM/SYNC Pin is