Altera Device Package Information
04R-00498-1.0
Package
Outline
8-Pin Small Outline Integrated Circuit Package (SOIC) - Wire Bond
All dimensions and tolerances conform to ASME Y14.5M – 1994.
Controlling dimension is in millimeters.
Pin 1 may be indicated by an ID dot, or a special feature, in its proximity on package surface.
Package Information
Description
Specification
Ordering Code Reference
S
Package Acronym
SOIC
Substrate Material
Copper
Lead Finish (plating)
Pb-free: Matte Tin (Annealed)
JEDEC Outline Reference
MS-012
Lead Coplanarity
0.1 mm
Weight
0.08 g (Typ.)
Moisture Sensitivity Level
Printed on moisture barrier bag
Variation: AA
Package Outline Dimension Table
Symbol
Millimeters
Min.
Nom.
Max.
A
1.35
-
1.75
A1
0.10
-
0.25
A2
-
-
-
D
4.90 BSC
E
6.00 BSC
E1
3.90 BSC
L
0.40
L1
1.27
-
b
0.33
c
0.19
e
-
0.51
-
0.25
1.27 BSC
October 2017
-
0
Intel Corporation
-
10°
04R-00498-1.0
Altera Device Package Information
2
Package Outline
______________________________________________________________________________
04R-00498-1.0
October 2017
Intel Corporation
Altera Device Package Information
3
Document Revision History
Table 1 shows the revision history for this document.
Table 1. Document Revision History
Date
Version
October 2017
101 Innovation Drive
San Jose, CA 95134
www.altera.com
October 2017
1.0
Changes
Initial release
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Intel Corporation
04R-00498-1.0
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