EPM7128E

MAX 7000 ® Programmable Logic Device Family Data Sheet September 2005, ver. 6.7 Features... ■ ■ ■ ■ ■ ■ ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) PCI-compliant devices available f For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Table 1. MAX 7000 Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz) EPM7032 600 32 2 36 6 5 2.5 4 151.5 EPM7064 1,250 64 4 68 6 5 2.5 4 151.5 EPM7096 1,800 96 6 76 7.5 6 3 4.5 125.0 EPM7128E 2,500 128 8 100 7.5 6 3 4.5 125.0 EPM7160E 3,200 160 10 104 10 7 3 5 100.0 EPM7192E 3,750 192 12 124 12 7 3 6 90.9 EPM7256E 5,000 256 16 164 12 7 3 6 90.9 Altera Corporation DS-MAX7000-6.7 1 MAX 7000 Programmable Logic Device Family Data Sheet Table 2. MAX 7000S Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz) EPM7032S 600 32 2 36 5 2.9 2.5 3.2 175.4 ■ ■ ■ ■ ■ EPM7064S 1,250 64 4 68 5 2.9 2.5 3.2 175.4 EPM7128S 2,500 128 8 100 6 3.4 2.5 4 147.1 EPM7160S 3,200 160 10 104 6 3.4 2.5 3.9 149.3 EPM7192S 3,750 192 12 124 7.5 4.1 3 4.7 125.0 EPM7256S 5,000 256 16 164 7.5 3.9 3 4.7 128.2 ...and More Features ■ ■ ■ ■ Open-drain output option in MAX 7000S devices Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power-saving mode for a reduction of over 50% in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages Programmable security bit for protection of proprietary designs 3.3-V or 5.0-V operation – MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages) – Pin compatible with low-voltage MAX 7000A and MAX 7000B devices Enhanced features available in MAX 7000E and MAX 7000S devices – Six pin- or logic-driven output enable signals – Two global clock signals with optional inversion – Enhanced interconnect resources for improved routability – Fast input setup times provided by a dedicated path from I/O pin to macrocell registers – Programmable output slew-rate control Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations 2 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet ■ ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest Programming support – Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices – The BitBlasterTM serial download cable, ByteBlasterMVTM parallel port download cable, and MasterBlasterTM serial/universal serial bus (USB) download cable program MAX 7000S devices General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades. Table 3. MAX 7000 Speed Grades Device -5 EPM7032 EPM7032S EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E EPM7256S Speed Grade -6 v v v v v v -7 v v v v v v v v v v v v v v -10P -10 v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v -12P -12 v -15 v -15T v -20 Altera Corporation 3 MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate. In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4. Table 4. MAX 7000 Device Features Feature EPM7032 EPM7064 EPM7096 All MAX 7000E Devices All MAX 7000S Devices v v(1) v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v ISP via JTAG interface JTAG BST circuitry Open-drain output option Fast input registers Six global output enables Two global clocks Slew-rate control MultiVolt interface (2) Programmable register Parallel expanders Shared expanders Power-saving mode Security bit PCI-compliant devices available Notes: (1) (2) Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only. The MultiVolt I/O interface is not available in 44-pin packages. 4 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. The MAX 7000 architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices are available in a wide range of packages, including PLCC, PGA, PQFP, RQFP, and TQFP packages. See Table 5. Table 5. MAX 7000 Maximum User I/O Pins Device Note (1) 160Pin PQFP 160Pin PGA 192Pin PGA 208Pin PQFP 208Pin RQFP 4444446884- 100- 100Pin Pin Pin Pin Pin Pin Pin PLCC PQFP TQFP PLCC PLCC PQFP TQFP 36 36 36 36 36 36 36 36 36 52 52 68 68 64 68 68 64 64 76 84 84 84 84 (2) 84 (2) 68 68 EPM7032 EPM7032S EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E EPM7256S Notes: (1) (2) 100 100 104 104 124 124 132 (2) 164 164 (2) 164 164 124 When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins become JTAG pins. Perform a complete thermal analysis before committing a design to this device package. For more information, see the Operating Requirements for Altera Devices Data Sheet. MAX 7000 devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. Altera Corporation 5 MAX 7000 Programmable Logic Device Family Data Sheet MAX 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and highspeed parallel expander product terms to provide up to 32 product terms per macrocell. The MAX 7000 family provides programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000E and MAX 7000S devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000 devices (except 44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing MAX 7000 devices to be used in mixed-voltage systems. The MAX 7000 family is supported byAltera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)— and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industrystandard PC- and UNIX-workstation-based EDA tools. The software runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f Functional Description For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. The MAX 7000 architecture includes the following elements: ■ ■ ■ ■ ■ Logic array blocks Macrocells Expander product terms (shareable and parallel) Programmable interconnect array I/O control blocks 6 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of EPM7032, EPM7064, and EPM7096 devices. Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram INPUT/GLCK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2 LAB A 8 to 16 8 to 16 I/O pins I/O Control Block 36 36 LAB B 8 to 16 Macrocells 1 to 16 16 Macrocells 17 to 32 16 I/O Control Block 8 to 16 I/O pins 8 to 16 LAB C 8 to 16 8 to 16 I/O pins I/O Control Block 36 PIA 36 8 to 16 LAB D 8 to 16 Macrocells 33 to 48 16 Macrocells 49 to 64 16 I/O Control Block 8 to 16 I/O pins 8 to 16 8 to 16 Altera Corporation 7 MAX 7000 Programmable Logic Device Family Data Sheet Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices. Figure 2. MAX 7000E & MAX 7000S Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 Output Enables 6 Output Enables 6 to16 LAB A LAB B 6 to16 6 to 16 I/O Pins I/O Control Block 6 to16 Macrocells 1 to 16 16 36 36 Macrocells 17 to 32 6 to16 I/O Control Block 6 to 16 I/O Pins 16 6 6 to16 LAB C 6 to16 PIA 6 to16 LAB D 6 6 to16 6 to 16 I/O Pins I/O Control Block 6 to16 Macrocells 33 to 48 16 36 36 Macrocells 49 to 64 6 to16 I/O Control Block 6 to 16 I/O Pins 16 6 6 to16 6 to16 6 Logic Array Blocks The MAX 7000 device architecture is based on the linking of highperformance, flexible, logic array modules called logic array blocks (LABs). LABs consist of 16-macrocell arrays, as shown in Figures 1 and 2. Multiple LABs are linked together via the programmable interconnect array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and macrocells. 8 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each LAB is fed by the following signals: ■ ■ ■ 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions Direct input paths from I/O pins to the registers that are used for fast setup times for MAX 7000E and MAX 7000S devices Macrocells The MAX 7000 macrocell can be individually configured for either sequential or combinatorial logic operation. The macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. The macrocell of EPM7032, EPM7064, and EPM7096 devices is shown in Figure 3. Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell Logic Array Parallel Logic Expanders (from other macrocells) Global Clear Global Clocks 2 Fast Input Select Programmable Register Register Bypass To I/O Control Block From I/O pin PRN D/T Q ProductTerm Select Matrix Clear Select Clock/ Enable Select VCC ENA CLRN Shared Logic Expanders 36 Signals from PIA 16 Expander Product Terms to PIA Altera Corporation 9 MAX 7000 Programmable Logic Device Family Data Sheet Figure 4 shows a MAX 7000E and MAX 7000S device macrocell. Figure 4. MAX 7000E & MAX 7000S Device Macrocell Logic Array Parallel Logic Expanders (from other macrocells) Global Clear Global Clocks 2 from I/O pin Fast Input Select Programmable Register Register Bypass to I/O Control Block PRN D/T Q ProductTerm Select Matrix Clear Select Clock/ Enable Select VCC ENA CLRN Shared Logic Expanders 36 Signals from PIA 16 Expander Product Terms to PIA Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell’s register clear, preset, clock, and clock enable control functions. Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources: ■ ■ Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design. For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. 10 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes: ■ ■ ■ By a global clock signal. This mode achieves the fastest clock-tooutput performance. By a global clock signal and enabled by an active-high clock enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. By an array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. In EPM7032, EPM7064, and EPM7096 devices, the global clock signal is available from a dedicated clock pin, GCLK1, as shown in Figure 1. In MAX 7000E and MAX 7000S devices, two global clock signals are available. As shown in Figure 2, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figures 3 and 4, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear of the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register in the device will be set to a low state. All MAX 7000E and MAX 7000S I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be driven to an input D flipflop with an extremely fast (2.5 ns) input setup time. Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, the more complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources; however, the MAX 7000 architecture also allows both shareable and parallel expander product terms (“expanders”) that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Altera Corporation 11 MAX 7000 Programmable Logic Device Family Data Sheet Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (tSEXP) is incurred when shareable expanders are used. Figure 5 shows how shareable expanders can feed multiple macrocells. Figure 5. Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic 36 Signals from PIA 16 Shared Expanders Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. 12 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The compiler can allocate up to three sets of up to five parallel expanders automatically to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14 product terms, the Compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes four product terms, increasing the total delay by 2 × tPEXP. Two groups of 8 macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lowernumbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. Figure 6 shows how parallel expanders can be borrowed from a neighboring macrocell. Figure 6. Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. From Previous Macrocell Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic 36 Signals from PIA 16 Shared Expanders To Next Macrocell Altera Corporation 13 MAX 7000 Programmable Logic Device Family Data Sheet Programmable Interconnect Array Logic is routed between LABs via the programmable interconnect array (PIA). This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 7000 dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure 7 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB. Figure 7. PIA Routing To LAB PIA Signals While the routing delays of channel-based routing schemes in masked or FPGAs are cumulative, variable, and path-dependent, the MAX 7000 PIA has a fixed delay. The PIA thus eliminates skew between signals and makes timing performance easy to predict. I/O Control Blocks The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All I/O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or VCC. Figure 8 shows the I/O control block for the MAX 7000 family. The I/O control block of EPM7032, EPM7064, and EPM7096 devices has two global output enable signals that are driven by two dedicated active-low output enable pins (OE1 and OE2). The I/O control block of MAX 7000E and MAX 7000S devices has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins, or a subset of the I/O macrocells. 14 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 8. I/O Control Block of MAX 7000 Devices EPM7032, EPM7064 & EPM7096 Devices VCC OE1 OE2 GND From Macrocell To PIA MAX 7000E & MAX 7000S Devices Six Global Output Enable Signals PIA VCC To Other I/O Pins From Macrocell Fast Input to Macrocell Register To PIA GND Open-Drain Output (1) Slew-Rate Control Note: (1) The open-drain output option is available only in MAX 7000S devices. Altera Corporation 15 MAX 7000 Programmable Logic Device Family Data Sheet When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When the tri-state buffer control is connected to VCC, the output is enabled. The MAX 7000 architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic. In-System Programmability (ISP) MAX 7000S devices are in-system programmable via an industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE Std. 1149.1-1990). ISP allows quick, efficient iterations during design development and debugging cycles. The MAX 7000S architecture internally generates the high programming voltage required to program EEPROM cells, allowing in-system programming with only a single 5.0 V power supply. During in-system programming, the I/O pins are tri-stated and pulled-up to eliminate board conflicts. The pull-up value is nominally 50 k¾. ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board with standard in-circuit test equipment before they are programmed. MAX 7000S devices can be programmed by downloading the information via in-circuit testers (ICT), embedded processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster, BitBlaster download cables. (The ByteBlaster cable is obsolete and is replaced by the ByteBlasterMV cable, which can program and configure 2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling and allows devices to be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers cannot support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code. The JamTM Standard Test and Programming Language (STAPL) can be used to program MAX 7000S devices with in-circuit testers, PCs, or embedded processor. 16 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet f For more information on using the Jam language, refer to AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor. The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 7000S device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1 ms. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1 ms. 2. 3. 4. 5. 6. Altera Corporation 17 MAX 7000 Programmable Logic Device Family Data Sheet Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: ■ ■ A pulse time to erase, program, or read the EEPROM cells. A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device. By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 7000S Device The time required to program a single MAX 7000S device in-system can be calculated from the following formula: Cycle PTCK t PROG = t PPULSE + ------------------------------f TCK where: tPROG tPPULSE = Programming time = Sum of the fixed times to erase, program, and verify the EEPROM cells CyclePTCK = Number of TCK cycles to program a device fTCK = TCK frequency The ISP times for a stand-alone verification of a single MAX 7000S device can be calculated from the following formula: Cycle VTCK t VER = t VPULSE + -------------------------------f TCK = Verify time where: tVER tVPULSE = Sum of the fixed times to verify the EEPROM cells CycleVTCK = Number of TCK cycles to verify a device 18 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The programming times described in Tables 6 through 8 are associated with the worst-case method using the enhanced ISP algorithm. Table 6. MAX 7000S tPULSE & CycleTCK Values Device Programming tPPULSE (s) EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S 4.02 4.50 5.11 5.35 5.71 6.43 Stand-Alone Verification tVPULSE (s) 0.03 0.03 0.03 0.03 0.03 0.03 CyclePTCK 342,000 504,000 832,000 1,001,000 1,192,000 1,603,000 CycleVTCK 200,000 308,000 528,000 640,000 764,000 1,024,000 Tables 7 and 8 show the in-system programming and stand alone verification times for several common test clock frequencies. Table 7. MAX 7000S In-System Programming Times for Different Test Clock Frequencies Device 10 MHz EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S 4.06 4.55 5.19 5.45 5.83 6.59 fTCK 5 MHz 4.09 4.60 5.27 5.55 5.95 6.75 Units 200 kHz 5.73 7.02 9.27 10.35 11.67 14.45 2 MHz 4.19 4.76 5.52 5.85 6.30 7.23 1 MHz 4.36 5.01 5.94 6.35 6.90 8.03 500 kHz 4.71 5.51 6.77 7.35 8.09 9.64 100 kHz 7.44 9.54 13.43 15.36 17.63 22.46 50 kHz 10.86 14.58 21.75 25.37 29.55 38.49 s s s s s s Table 8. MAX 7000S Stand-Alone Verification Times for Different Test Clock Frequencies Device 10 MHz EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S 0.05 0.06 0.08 0.09 0.11 0.13 fTCK 5 MHz 0.07 0.09 0.14 0.16 0.18 0.24 Units 200 kHz 1.03 1.57 2.67 3.23 3.85 5.15 2 MHz 0.13 0.18 0.29 0.35 0.41 0.54 1 MHz 0.23 0.34 0.56 0.67 0.79 1.06 500 kHz 0.43 0.64 1.09 1.31 1.56 2.08 100 kHz 2.03 3.11 5.31 6.43 7.67 10.27 50 kHz 4.03 6.19 10.59 12.83 15.31 20.51 s s s s s s Altera Corporation 19 MAX 7000 Programmable Logic Device Family Data Sheet Programmable Speed/Power Control MAX 7000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more, because most logic applications require only a small fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX 7000 device for either high-speed (i.e., with the Turbo BitTM option turned on) or low-power (i.e., with the Turbo Bit option turned off) operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tEN, and tSEXP, tACL, and tCPPW parameters. Output Configuration MAX 7000 device outputs can be programmed to meet a variety of system-level requirements. MultiVolt I/O Interface MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O interface feature, which allows MAX 7000 devices to interface with systems that have differing supply voltages. The 5.0-V devices in all packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCINT pins must always be connected to a 5.0-V power supply. With a 5.0-V VCCINT level, input voltage thresholds are at TTL levels, and are therefore compatible with both 3.3-V and 5.0-V inputs. The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V supply, the output levels are compatible with 5.0-V systems. When VCCIO is connected to a 3.3-V supply, the output high is 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V incur a nominally greater timing delay of tOD2 instead of tOD1. Open-Drain Output Option (MAX 7000S Devices Only) MAX 7000S devices provide an optional open-drain (functionally equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane. 20 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet By using an external 5.0-V pull-up resistor, output pins on MAX 7000S devices can be set to meet 5.0-V CMOS input voltages. When VCCIO is 3.3 V, setting the open drain option will turn off the output pull-up transistor, allowing the external pull-up resistor to pull the output high enough to meet 5.0-V CMOS input voltages. When VCCIO is 5.0 V, setting the output drain option is not necessary because the pull-up transistor will already turn off when the pin exceeds approximately 3.8 V, allowing the external pull-up resistor to pull the output high enough to meet 5.0-V CMOS input voltages. Slew-Rate Control The output buffer for each MAX 7000E and MAX 7000S I/O pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. In MAX 7000E devices, when the Turbo Bit is turned off, the slew rate is set for low noise performance. For MAX 7000S devices, each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. Programming with External Hardware f MAX 7000 devices can be programmed on Windows-based PCs with the Altera Logic Programmer card, the Master Programming Unit (MPU), and the appropriate device adapter. The MPU performs a continuity check to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardware Data Sheet. The Altera development system can use text- or waveform-format test vectors created with the Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional behavior of a MAX 7000 device with the results of simulation. Moreover, Data I/O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices. f For more information, see the Programming Hardware Manufacturers. Altera Corporation 21 MAX 7000 Programmable Logic Device Family Data Sheet IEEE Std. 1149.1 (JTAG) Boundary-Scan Support MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std. 1149.1-1990. Table 9 describes the JTAG instructions supported by the MAX 7000 family. The pin-out tables (see the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information) show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins. Table 9. MAX 7000 JTAG Instructions JTAG Instruction SAMPLE/PRELOAD Devices EPM7128S EPM7160S EPM7192S EPM7256S EPM7128S EPM7160S EPM7192S EPM7256S EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. EXTEST BYPASS IDCODE Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. ISP Instructions These instructions are used when programming MAX 7000S devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc), or Serial Vector Format file (.svf) via an embedded processor or test equipment. 22 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The instruction register length of MAX 7000S devices is 10 bits. Tables 10 and 11 show the boundary-scan register length and device IDCODE information for MAX 7000S devices. Table 10. MAX 7000S Boundary-Scan Register Length Device EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Note: (1) This device does not support JTAG boundary-scan testing. Selecting either the EXTEST or SAMPLE/PRELOAD instruction will select the one-bit bypass register. Boundary-Scan Register Length 1 (1) 1 (1) 288 312 360 480 Table 11. 32-Bit MAX 7000 Device IDCODE Device Version (4 Bits) EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Notes: (1) (2) Note (1) IDCODE (32 Bits) Part Number (16 Bits) 0111 0000 0011 0010 0111 0000 0110 0100 0111 0001 0010 1000 0111 0001 0110 0000 0111 0001 1001 0010 0111 0010 0101 0110 Manufacturer’s 1 (1 Bit) Identity (11 Bits) (2) 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 1 1 1 1 1 1 0000 0000 0000 0000 0000 0000 The most significant bit (MSB) is on the left. The least significant bit (LSB) for all JTAG IDCODEs is 1. Altera Corporation 23 MAX 7000 Programmable Logic Device Family Data Sheet Figure 9 shows the timing requirements for the JTAG signals. Figure 9. MAX 7000 JTAG Waveforms TMS TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH tJSZX tJSCO tJSXZ Table 12 shows the JTAG timing parameters and values for MAX 7000S devices. Table 12. JTAG Timing Parameters & Values for MAX 7000S Devices Symbol tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance 20 45 25 25 25 Parameter Min 100 50 50 20 45 Max Unit ns ns ns ns ns 25 25 25 ns ns ns ns ns ns ns ns f 24 For more information, see Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Design Security All MAX 7000 devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. Each MAX 7000 device is functionally tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 10. Test patterns can be used and then erased during early stages of the production flow. Figure 10. MAX 7000 AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast ground-current transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.5-V devices and outputs. Numbers without brackets are for 3.3-V devices and outputs. Generic Testing VCC 464 Ω [703 Ω] Device Output To Test System 250 Ω [8.06 KΩ ] Device input rise and fall times < 3 ns C1 (includes JIG capacitance) QFP Carrier & Development Socket f MAX 7000 and MAX 7000E devices in QFP packages with 100 or more pins are shipped in special plastic carriers to protect the QFP leads. The carrier is used with a prototype development socket and special programming hardware available from Altera. This carrier technology makes it possible to program, test, erase, and reprogram a device without exposing the leads to mechanical stress. For detailed information and carrier dimensions, refer to the QFP Carrier & Development Socket Data Sheet. 1 MAX 7000S devices are not shipped in carriers. Altera Corporation 25 MAX 7000 Programmable Logic Device Family Data Sheet Operating Conditions Tables 13 through 18 provide information about absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 5.0-V MAX 7000 devices. Note (1) Min –2.0 –2.0 –25 No bias Under bias Ceramic packages, under bias PQFP and RQFP packages, under bias –65 –65 Table 13. MAX 7000 5.0-V Device Absolute Maximum Ratings Symbol VCC VI IOUT TSTG TAMB TJ Parameter Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature Conditions With respect to ground (2) Max 7.0 7.0 25 150 135 150 135 Unit V V mA °C °C °C °C Table 14. MAX 7000 5.0-V Device Recommended Operating Conditions Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and (3), (4), (5) input buffers Supply voltage for output drivers, 5.0-V operation Supply voltage for output drivers, 3.3-V operation (3), (4) (3), (4), (6) (7) Conditions Min 4.75 (4.50) 4.75 (4.50) 3.00 (3.00) 4.75 –0.5 (8) 0 Max 5.25 (5.50) 5.25 (5.50) 3.60 (3.60) 5.25 VCCINT + 0.5 VCCIO 70 85 90 105 40 40 Unit V V V V V V °C °C °C °C ns ns VCCISP VI VO TA TJ tR tF Supply voltage during ISP Input voltage Output voltage Ambient temperature Junction temperature Input rise time Input fall time For commercial use For industrial use For commercial use For industrial use 0 –40 0 –40 26 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 15. MAX 7000 5.0-V Device DC Operating Conditions Symbol VIH VIL VOH Note (9) Min 2.0 –0.5 (8) Parameter High-level input voltage Low-level input voltage 5.0-V high-level TTL output voltage 3.3-V high-level TTL output voltage 3.3-V high-level CMOS output voltage Conditions Max VCCINT + 0.5 0.8 Unit V V V V V IOH = –4 mA DC, VCCIO = 4.75 V (10) IOH = –4 mA DC, VCCIO = 3.00 V (10) IOH = –0.1 mA DC, VCCIO = 3.0 V (10) IOL = 12 mA DC, VCCIO = 4.75 V (11) IOL = 12 mA DC, VCCIO = 3.00 V (11) IOL = 0.1 mA DC, VCCIO = 3.0 V(11) VI = –0.5 to 5.5 V (11) VI = –0.5 to 5.5 V (11), (12) 2.4 2.4 VCCIO – 0.2 0.45 0.45 0.2 –10 –40 10 40 VOL 5.0-V low-level TTL output voltage 3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage V V V μA μA II IOZ Leakage current of dedicated input pins I/O pin tri-state output off-state current Table 16. MAX 7000 5.0-V Device Capacitance: EPM7032, EPM7064 & EPM7096 Devices Symbol CIN CI/O Note (13) Max 12 12 Parameter Input pin capacitance I/O pin capacitance Conditions VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz Min Unit pF pF Table 17. MAX 7000 5.0-V Device Capacitance: MAX 7000E Devices Symbol CIN CI/O Note (13) Min Max 15 15 Parameter Input pin capacitance I/O pin capacitance Conditions VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz Unit pF pF Table 18. MAX 7000 5.0-V Device Capacitance: MAX 7000S Devices Symbol CIN CI/O Note (13) Min Max 10 10 Parameter Dedicated input pin capacitance I/O pin capacitance Conditions VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz Unit pF pF Altera Corporation 27 MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) See the Operating Requirements for Altera Devices Data Sheet. Minimum DC input voltage on I/O pins is –0.5 V and on 4 dedicated input pins is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns. Numbers in parentheses are for industrial-temperature-range devices. VCC must rise monotonically. The POR time for all 7000S devices does not exceed 300 μs. The sufficient VCCINT voltage level for POR is 4.5 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level. 3.3-V I/O operation is not available for 44-pin packages. The VCCISP parameter applies only to MAX 7000S devices. During in-system programming, the minimum DC input voltage is –0.3 V. These values are specified under the MAX 7000 recommended operating conditions in Table 14 on page 26. The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers to high-level TTL or CMOS output current. The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to low-level TTL, PCI, or CMOS output current. When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically –60 μA. Capacitance is measured at 25° C and is sample-tested only. The OE1 pin has a maximum capacitance of 20 pF. (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) Figure 11 shows the typical output drive characteristics of MAX 7000 devices. Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices 150 IOL 150 IOL 120 120 Typical I O Output Current (mA) 90 60 VCCIO = 5.0 V Room Temperature IOH Typical I O Output Current (mA) 90 60 VCCIO = 3.3 V Room Temperature IOH 30 30 1 2 3 4 5 1 2 3 3.3 4 5 VO Output Voltage (V) VO Output Voltage (V) Timing Model MAX 7000 device timing can be analyzed with the Altera software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 12. MAX 7000 devices have fixed internal delays that enable the designer to determine the worst-case timing of any design. The Altera software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for a device-wide performance evaluation. 28 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 12. MAX 7000 Timing Model Internal Output Enable Delay t IOE (1) Input Delay t IN PIA Delay t PIA Global Control Delay t GLOB Logic Array Delay t LAD Register Control Delay t LAC tIC t EN Shared Expander Delay t SEXP Fast Input Delay t F I N (1) Parallel Expander Delay t PEXP Register Delay t SU tH t PRE t CLR t RD t COMB t FSU t FH Output Delay t OD1 t OD2 (2) t OD3 t XZ t Z X1 t Z X2 (2) t Z X3 (1) I/O Delay tIO Notes: (1) (2) Only available in MAX 7000E and MAX 7000S devices. Not available in 44-pin devices. The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 13 shows the internal timing relationship of internal and external delay parameters. f For more infomration, see Application Note 94 (Understanding MAX 7000 Timing). Altera Corporation 29 MAX 7000 Programmable Logic Device Family Data Sheet Figure 13. Switching Waveforms tR & tF < 3 ns. Inputs are driven at 3 V for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Combinatorial Mode tIN Input Pin tIO I/O Pin tPIA PIA Delay tSEXP Shared Expander Delay tLAC , tLAD Logic Array Input tPEXP Parallel Expander Delay tCOMB Logic Array Output tOD Output Pin Global Clock Mode Global Clock Pin Global Clock at Register tR tIN tCH tGLOB tH tCL tF tSU Data or Enable (Logic Array Output) Array Clock Mode tR Input or I/O Pin tACH tIN tIO tACL tF Clock into PIA Clock into Logic Array Clock at Register Data from Logic Array tPIA tIC tSU tH tRD Register to PIA to Logic Array tPIA tOD tCLR , tPRE tOD tPIA Register Output to Pin 30 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Tables 19 through 26 show the MAX 7000 and MAX 7000E AC operating conditions. Table 19. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Conditions Note (1) -7 Speed Grade Min Max 7.5 7.5 6.0 0.0 3.0 0.5 4.0 2.5 2.5 2.5 2.0 C1 = 35 pF 3.0 3.0 (3) C1 = 35 pF (4) (5) 3.0 1.0 6.6 151.5 6.6 (5) (6) 151.5 200 125.0 166.7 125.0 8.0 6.5 3.0 3.0 3.0 1.0 8.0 3.0 3.0 3.0 2.0 7.5 4.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz -6 Speed Grade Min Max 6.0 6.0 5.0 0.0 Unit tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tODH tCNT fCNT tACNT fACNT fMAX Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency Maximum clock frequency C1 = 35 pF C1 = 35 pF (2) (2) C1 = 35 pF 2.5 0.5 Altera Corporation 31 MAX 7000 Programmable Logic Device Family Data Sheet Table 20. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -7 Min Max 0.5 0.5 1.0 4.0 0.8 3.0 3.0 2.0 2.0 2.5 7.0 2.0 2.5 7.0 ns ns ns ns ns ns ns ns ns ns ns Speed Grade -6 Min Max 0.4 0.4 Unit tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Slow slew rate = off, VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off, VCCIO = 3.3 V Output buffer and pad delay Slow slew rate = on, VCCIO = 5.0 V or 3.3 V Output buffer enable delay Slow slew rate = off, VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off, VCCIO = 3.3 V Output buffer enable delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (8) (2) (2) (2) C1 = 35 pF C1 = 35 pF (7) C1 = 35 pF (2) (2) 0.8 3.5 0.8 2.0 2.0 tZX1 tZX2 tZX3 C1 = 35 pF C1 = 35 pF (7) C1 = 35 pF (2) 4.0 4.5 9.0 4.0 4.5 9.0 ns ns ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA C1 = 5 pF 3.0 1.5 2.5 0.5 4.0 3.0 2.0 3.0 0.5 0.8 0.8 2.5 2.0 0.8 2.0 2.0 0.8 10.0 4.0 ns ns ns ns ns 1.0 1.0 3.0 3.0 1.0 2.0 2.0 1.0 10.0 ns ns ns ns ns ns ns ns ns 32 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 21. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade MAX 7000E (-10P) MAX 7000 (-10) MAX 7000E (-10) Min Max 10.0 10.0 7.0 0.0 3.0 0.5 5.0 4.0 4.0 2.0 3.0 4.0 4.0 3.0 3.0 10.0 4.0 4.0 4.0 4.0 4.0 1.0 10.0 10.0 100.0 10.0 10.0 100.0 125.0 10.0 8.0 0.0 3.0 0.5 5 Unit Min Max 10.0 10.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tODH tCNT fCNT tACNT fACNT fMAX Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time C1 = 35 pF C1 = 35 pF Global clock setup time of fast input (2) Global clock hold time of fast input (2) Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency Maximum clock frequency (5) (6) (5) (3) C1 = 35 pF (4) C1 = 35 pF C1 = 35 pF 4.0 1.0 100.0 100.0 125.0 Altera Corporation 33 MAX 7000 Programmable Logic Device Family Data Sheet Table 22. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade Unit MAX 7000E (-10P) Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Slow slew rate = off VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V Output buffer enable delay Slow slew rate = off VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off VCCIO = 3.3 V Output buffer enable delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (8) (2) (2) (2) C1 = 35 pF (2) MAX 7000 (-10) MAX 7000E (-10) Min Max 1.0 1.0 1.0 5.0 0.8 5.0 5.0 2.0 2.0 ns ns ns ns ns ns ns ns ns Max 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 tOD2 C1 = 35 pF (7) 2.0 2.5 ns tOD3 C1 = 35 pF (2) 5.5 6.0 ns tZX1 C1 = 35 pF 5.0 5.0 ns tZX2 C1 = 35 pF (7) 5.5 5.5 ns tZX3 C1 = 35 pF (2) 9.0 9.0 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA C1 = 5 pF 2.0 3.0 3.0 0.5 5.0 3.0 3.0 3.0 0.5 2.0 2.0 5.0 5.0 1.0 3.0 3.0 1.0 11.0 5.0 ns ns ns ns ns 1.0 1.0 5.0 5.0 1.0 3.0 3.0 1.0 11.0 ns ns ns ns ns ns ns ns ns 34 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 23. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade Unit MAX 7000E (-12P) Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tODH tCNT fCNT tACNT fACNT fMAX Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input (2) Global clock hold time of fast input (2) Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency Maximum clock frequency (5) (6) 90.9 125.0 (5) 90.9 11.0 (3) C1 = 35 pF (4) C1 = 35 pF 5.0 5.0 5.0 1.0 11.0 C1 = 35 pF 4.0 4.0 3.0 4.0 12.0 C1 = 35 pF C1 = 35 pF 7.0 0.0 3.0 0.0 6.0 MAX 7000 (-12) MAX 7000E (-12) Min Max 12.0 12.0 10.0 0.0 3.0 0.0 6.0 4.0 4.0 4.0 4.0 12.0 5.0 5.0 5.0 1.0 11.0 90.9 11.0 90.9 125.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz Max 12.0 12.0 Altera Corporation 35 MAX 7000 Programmable Logic Device Family Data Sheet Table 24. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade Unit MAX 7000E (-12P) Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Slow slew rate = off VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V Output buffer enable delay Slow slew rate = off VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off VCCIO = 3.3 V Output buffer enable delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (8) (2) (2) (2) C1 = 35 pF (2) MAX 7000 (-12) MAX 7000E (-12) Min Max 2.0 2.0 1.0 7.0 1.0 5.0 5.0 2.0 3.0 ns ns ns ns ns ns ns ns ns Max 1.0 1.0 1.0 7.0 1.0 7.0 5.0 2.0 1.0 tOD2 C1 = 35 pF (7) 2.0 4.0 ns tOD3 C1 = 35 pF (2) 5.0 7.0 ns tZX1 C1 = 35 pF 6.0 6.0 ns tZX2 C1 = 35 pF (7) 7.0 7.0 ns tZX3 C1 = 35 pF (2) 10.0 10.0 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA C1 = 5 pF 1.0 6.0 4.0 0.0 6.0 4.0 4.0 2.0 2.0 2.0 2.0 5.0 7.0 2.0 4.0 4.0 1.0 12.0 6.0 ns ns ns ns ns 1.0 1.0 5.0 5.0 0.0 3.0 3.0 1.0 12.0 ns ns ns ns ns ns ns ns ns 36 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 25. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Conditions -15 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tODH tCNT fCNT tACNT fACNT fMAX Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency Maximum clock frequency (5) (6) 76.9 100 (5) 76.9 13.0 (3) C1 = 35 pF (4) C1 = 35 pF 6.0 6.0 6.0 1.0 13.0 (2) (2) C1 = 35 pF 5.0 5.0 4.0 4.0 15.0 C1 = 35 pF C1 = 35 pF 11.0 0.0 3.0 0.0 8.0 Note (1) Speed Grade -15T Min Max 15.0 15.0 11.0 0.0 – – 8.0 6.0 6.0 4.0 4.0 15.0 6.5 6.5 6.5 1.0 13.0 76.9 13.0 76.9 83.3 62.5 83.3 62.5 16.0 8.0 8.0 8.0 1.0 16.0 6.0 6.0 5.0 5.0 20.0 12.0 0.0 5.0 0.0 12.0 Unit -20 Min Max 20.0 20.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz Max 15.0 15.0 Altera Corporation 37 MAX 7000 Programmable Logic Device Family Data Sheet Table 26. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter Conditions -15 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Slow slew rate = off VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V Output buffer enable delay Slow slew rate = off VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off VCCIO = 3.3 V Output buffer enable delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input (2) Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (8) (2) (2) C1 = 35 pF (2) Note (1) Speed Grade -15T Max 2.0 2.0 2.0 8.0 1.0 6.0 6.0 3.0 4.0 Unit -20 Min Max 3.0 3.0 4.0 9.0 2.0 8.0 8.0 4.0 5.0 ns ns ns ns ns ns ns ns ns Min Max 2.0 2.0 – 10.0 1.0 6.0 6.0 – 4.0 tOD2 C1 = 35 pF (7) 5.0 – 6.0 ns tOD3 C1 = 35 pF (2) 8.0 – 9.0 ns tZX1 C1 = 35 pF 6.0 6.0 10.0 ns tZX2 C1 = 35 pF (7) 7.0 – 11.0 ns tZX3 C1 = 35 pF (2) 10.0 – 14.0 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA C1 = 5 pF 4.0 4.0 2.0 2.0 6.0 4.0 4.0 – – 1.0 1.0 6.0 6.0 1.0 4.0 4.0 2.0 13.0 6.0 4.0 5.0 4.0 3.0 1.0 1.0 6.0 6.0 1.0 4.0 4.0 2.0 15.0 10.0 ns ns ns ns ns 1.0 1.0 8.0 8.0 3.0 4.0 4.0 3.0 15.0 ns ns ns ns ns ns ns ns ns 38 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) (3) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more information on switching waveforms. This parameter applies to MAX 7000E devices only. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use. The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. (4) (5) (6) (7) (8) Tables 27 and 28 show the EPM7032S AC operating conditions. Table 27. EPM7032S External Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -5 Note (1) Speed Grade -6 -7 -10 Unit Min Max Min Max Min Max Min Max tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tODH tCNT fCNT tACNT Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency Minimum array clock period (4) 175.4 5.7 (2) C1 = 35 pF (3) C1 = 35 pF 2.5 2.5 2.5 1.0 5.7 142.9 7.0 C1 = 35 pF 2.0 2.0 0.7 1.8 5.4 2.5 2.5 2.5 1.0 7.0 116.3 8.6 C1 = 35 pF C1 = 35 pF 2.9 0.0 2.5 0.0 3.2 2.5 2.5 0.9 2.1 6.6 3.0 3.0 3.0 1.0 8.6 100.0 10.0 5.0 5.0 4.0 0.0 2.5 0.0 3.5 3.0 3.0 1.1 2.7 8.2 4.0 4.0 4.0 1.0 10.0 6.0 6.0 5.0 0.0 2.5 0.0 4.3 4.0 4.0 2.0 3.0 10.0 7.5 7.5 7.0 0.0 3.0 0.5 5.0 10.0 10.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns Altera Corporation 39 MAX 7000 Programmable Logic Device Family Data Sheet Table 27. EPM7032S External Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -5 Note (1) Speed Grade -6 -7 -10 Unit Min Max Min Max Min Max Min Max fACNT fMAX Maximum internal array clock frequency Maximum clock frequency (4) (5) 175.4 250.0 142.9 200.0 116.3 166.7 100.0 125.0 MHz MHz Table 28. EPM7032S Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -5 Min Max 0.2 0.2 2.2 3.1 0.9 2.6 2.5 0.7 Unit -10 Max 0.3 0.3 2.5 4.6 1.4 4.0 4.0 1.0 0.4 0.9 5.4 4.0 4.5 9.0 4.0 -6 Min Max 0.2 0.2 2.1 3.8 1.1 3.3 3.3 0.8 0.3 0.8 5.3 4.0 4.5 9.0 4.0 1.0 2.0 1.8 0.7 1.2 0.9 2.7 2.6 1.6 2.0 2.0 1.6 1.1 3.4 3.3 1.4 2.4 2.4 1.3 2.5 1.7 0.8 -7 Min Min Max 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 2.0 5.5 5.0 5.5 9.0 5.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2.0 2.0 5.0 5.0 1.0 3.0 3.0 ns ns ns ns ns ns ns tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Output buffer and pad delay Output buffer and pad delay Output buffer enable delay Output buffer enable delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 5 pF 0.8 1.7 1.9 0.6 0.2 0.7 5.2 4.0 4.5 9.0 4.0 2.0 3.0 3.0 0.5 1.9 1.4 4.2 4.0 1.7 3.0 3.0 40 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 28. EPM7032S Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -5 Min Max 1.1 12.0 Unit -10 Max 1.4 10.0 -6 Min Max 1.1 10.0 -7 Min Min Max 1.0 11.0 ns ns tPIA tLPA PIA delay Low-power adder (7) (8) Notes to tables: (1) (2) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. (3) (4) (5) (6) (7) (8) Tables 29 and 30 show the EPM7064S AC operating conditions. Table 29. EPM7064S External Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -5 Note (1) Speed Grade -6 -7 -10 Unit Min Max Min Max Min Max Min Max tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time C1 = 35 pF 2.0 2.0 0.7 1.8 C1 = 35 pF C1 = 35 pF 2.9 0.0 2.5 0.0 3.2 2.5 2.5 0.9 2.1 5.0 5.0 3.6 0.0 2.5 0.0 4.0 3.0 3.0 3.0 2.0 6.0 6.0 6.0 0.0 3.0 0.5 4.5 4.0 4.0 2.0 3.0 7.5 7.5 7.0 0.0 3.0 0.5 5.0 10.0 10.0 ns ns ns ns ns ns ns ns ns ns ns Altera Corporation 41 MAX 7000 Programmable Logic Device Family Data Sheet Table 29. EPM7064S External Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -5 Note (1) Speed Grade -6 -7 -10 Unit Min Max Min Max Min Max Min Max tACO1 tACH tACL tCPPW tODH tCNT fCNT tACNT fACNT fMAX Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency Maximum clock frequency (4) (5) 175.4 250.0 (4) 175.4 5.7 140.8 200.0 (2) C1 = 35 pF (3) C1 = 35 pF 2.5 2.5 2.5 1.0 5.7 140.8 7.1 125.0 166.7 5.4 2.5 2.5 2.5 1.0 7.1 125.0 8.0 100.0 125.0 6.7 3.0 3.0 3.0 1.0 8.0 100.0 10.0 7.5 4.0 4.0 4.0 1.0 10.0 10.0 ns ns ns ns ns ns MHz ns MHz MHz Table 30. EPM7064S Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -5 Note (1) Speed Grade -6 -7 -10 Unit Min Max Min Max Min Max Min Max tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tXZ tSU tH Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Output buffer and pad delay Output buffer and pad delay Output buffer enable delay Output buffer enable delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 5 pF 0.8 1.7 0.2 0.2 2.2 3.1 0.9 2.6 2.5 0.7 0.2 0.7 5.2 4.0 4.5 9.0 4.0 1.0 2.0 0.2 0.2 2.6 3.8 1.1 3.2 3.2 0.8 0.3 0.8 5.3 4.0 4.5 9.0 4.0 3.0 2.0 0.5 0.5 1.0 4.0 0.8 3.0 3.0 2.0 2.0 2.5 7.0 4.0 4.5 9.0 4.0 2.0 3.0 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 2.0 5.5 5.0 5.5 9.0 5.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 42 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 30. EPM7064S Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -5 Min Max tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (7) (8) 1.9 0.6 1.2 0.9 2.7 2.6 1.6 2.0 2.0 1.1 12.0 Note (1) Speed Grade -6 Min Max 1.8 0.7 1.6 1.0 3.3 3.2 1.9 2.4 2.4 1.3 11.0 Unit -10 Min Max 3.0 0.5 1.0 1.0 3.0 3.0 1.0 2.0 2.0 1.0 10.0 2.0 2.0 5.0 5.0 1.0 3.0 3.0 1.0 11.0 ns ns ns ns ns ns ns ns ns ns ns -7 Min Max 3.0 0.5 Notes to tables: (1) (2) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. (3) (4) (5) (6) (7) (8) Altera Corporation 43 MAX 7000 Programmable Logic Device Family Data Sheet Tables 31 and 32 show the EPM7128S AC operating conditions. Table 31. EPM7128S External Timing Parameters Symbol Parameter Conditions -6 Note (1) Speed Grade -7 -10 -15 Unit Min Max Min Max Min Max Min Max tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tODH tCNT fCNT tACNT fACNT fMAX Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency Maximum clock frequency (4) (5) 147.1 166.7 (4) 147.1 6.8 125.0 166.7 (2) C1 = 35 pF (3) C1 = 35 pF 3.0 3.0 3.0 1.0 6.8 125.0 8.0 100.0 125.0 C1 = 35 pF 3.0 3.0 0.9 1.8 6.5 3.0 3.0 3.0 1.0 8.0 100.0 10.0 76.9 100.0 C1 = 35 pF C1 = 35 pF 3.4 0.0 2.5 0.0 4.0 3.0 3.0 3.0 2.0 7.5 4.0 4.0 4.0 1.0 10.0 76.9 13.0 6.0 6.0 6.0 0.0 3.0 0.5 4.5 4.0 4.0 2.0 5.0 10.0 6.0 6.0 6.0 1.0 13.0 7.5 7.5 7.0 0.0 3.0 0.5 5.0 5.0 5.0 4.0 4.0 15.0 10.0 10.0 11.0 0.0 3.0 0.0 8.0 15.0 15.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz 44 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 32. EPM7128S Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -6 Min Max -7 Min Max 0.5 0.5 1.0 4.0 0.8 3.0 3.0 2.0 2.0 2.5 7.0 4.0 4.5 9.0 4.0 3.0 2.0 3.0 0.5 1.4 1.0 3.1 3.0 2.0 2.4 2.4 1.0 1.0 3.0 3.0 1.0 2.0 2.0 1.0 10.0 2.0 5.0 3.0 0.5 2.0 2.0 5.0 5.0 1.0 3.0 3.0 1.0 11.0 Unit -15 Min Max 2.0 2.0 2.0 8.0 1.0 6.0 6.0 3.0 4.0 5.0 8.0 6.0 7.0 10.0 6.0 4.0 4.0 2.0 1.0 1.0 1.0 6.0 6.0 1.0 4.0 4.0 2.0 13.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -10 Min Max 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 2.0 5.5 5.0 5.5 9.0 5.0 tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Output buffer and pad delay Output buffer and pad delay Output buffer enable delay Output buffer enable delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (7) (8) C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 5 pF 1.0 1.7 1.9 0.6 0.2 0.2 2.6 3.7 1.1 3.0 3.0 0.7 0.4 0.9 5.4 4.0 4.5 9.0 4.0 1.4 11.0 Altera Corporation 45 MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. (3) (4) (5) (6) (7) (8) Tables 33 and 34 show the EPM7160S AC operating conditions. Table 33. EPM7160S External Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -6 Note (1) Speed Grade -7 -10 -15 Unit Min Max Min Max Min Max Min Max tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tODH tCNT fCNT Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency (4) 149.3 (2) C1 = 35 pF (3) C1 = 35 pF 3.0 3.0 2.5 1.0 6.7 122.0 C1 = 35 pF 3.0 3.0 0.9 1.7 6.4 3.0 3.0 3.0 1.0 8.2 100.0 C1 = 35 pF C1 = 35 pF 3.4 0.0 2.5 0.0 3.9 3.0 3.0 1.1 2.1 7.9 4.0 4.0 4.0 1.0 10.0 76.9 6.0 6.0 4.2 0.0 3.0 0.0 4.8 4.0 4.0 2.0 3.0 10.0 6.0 6.0 6.0 1.0 13.0 7.5 7.5 7.0 0.0 3.0 0.5 5 5.0 5.0 4.0 4.0 15.0 10.0 10.0 11.0 0.0 3.0 0.0 8 15.0 15.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 46 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 33. EPM7160S External Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -6 Note (1) Speed Grade -7 -10 -15 Unit Min Max Min Max Min Max Min Max tACNT fACNT fMAX Minimum array clock period Maximum internal array clock frequency Maximum clock frequency (4) (5) 149.3 166.7 6.7 122.0 166.7 8.2 100.0 125.0 10.0 76.9 100.0 13.0 ns MHz MHz Table 34. EPM7160S Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -6 Min Max tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Output buffer and pad delay Output buffer and pad delay Output buffer enable delay Output buffer enable delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 5 pF 1.0 1.6 1.9 0.6 1.3 1.0 2.9 2.8 2.0 2.4 0.2 0.2 2.6 3.6 1.0 2.8 2.8 0.7 0.4 0.9 5.4 4.0 4.5 9.0 4.0 Note (1) Speed Grade -7 Min Max 0.3 0.3 3.2 4.3 1.3 3.4 3.4 0.9 0.5 1.0 5.5 4.0 4.5 9.0 4.0 1.2 2.0 2.2 0.8 1.6 1.3 3.5 3.4 2.4 3.0 2.0 3.0 3.0 0.5 2.0 2.0 5.0 5.0 1.0 3.0 Unit -15 Min Max 2.0 2.0 2.0 8.0 1.0 6.0 6.0 3.0 4.0 5.0 8.0 6.0 7.0 10.0 6.0 4.0 4.0 2.0 1.0 1.0 1.0 6.0 6.0 1.0 4.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -10 Min Max 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 2.0 5.5 5.0 5.5 9.0 5.0 Altera Corporation 47 MAX 7000 Programmable Logic Device Family Data Sheet Table 34. EPM7160S Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -6 Note (1) Speed Grade -7 -10 -15 Unit Min Max Min Max Min Max Min Max tCLR tPIA tLPA Register clear time PIA delay Low-power adder (7) (8) 2.4 1.6 11.0 3.0 2.0 10.0 3.0 1.0 11.0 4.0 2.0 13.0 ns ns ns Notes to tables: (1) (2) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. (3) (4) (5) (6) (7) (8) Tables 35 and 36 show the EPM7192S AC operating conditions. Table 35. EPM7192S External Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -7 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time C1 = 35 pF 3.0 3.0 1.0 C1 = 35 pF C1 = 35 pF 4.1 0.0 3.0 0.0 4.7 4.0 4.0 2.0 Note (1) Speed Grade -10 Max 7.5 7.5 7.0 0.0 3.0 0.5 5.0 5.0 5.0 4.0 Unit -15 Min Max 10.0 10.0 Min Max 15.0 15.0 ns ns ns ns ns ns 8.0 ns ns ns ns 11.0 0.0 3.0 0.0 48 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 35. EPM7192S External Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -7 Min tAH tACO1 tACH tACL tCPPW tODH tCNT fCNT tACNT fACNT fMAX Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency Maximum clock frequency (4) (5) 125.0 166.7 (4) 125.0 8.0 (2) C1 = 35 pF (3) C1 = 35 pF 3.0 3.0 3.0 1.0 8.0 1.8 7.8 Note (1) Speed Grade -10 Max Min 3.0 10.0 4.0 4.0 4.0 1.0 10.0 100.0 10.0 100.0 125.0 76.9 100.0 76.9 13.0 6.0 6.0 6.0 1.0 13.0 Unit -15 Max Min 4.0 Max ns 15.0 ns ns ns ns ns ns MHz ns MHz MHz Table 36. EPM7192S Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -7 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tXZ tSU Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Output buffer and pad delay Output buffer and pad delay Output buffer enable delay Output buffer enable delay Output buffer enable delay Output buffer disable delay Register setup time C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 5 pF 1.1 Note (1) Speed Grade -10 Max 0.3 0.3 3.2 4.2 1.2 3.1 3.1 0.9 0.5 1.0 5.5 4.0 4.5 9.0 4.0 2.0 Unit -15 Min Max 2.0 2.0 2.0 8.0 1.0 6.0 6.0 3.0 4.0 5.0 7.0 6.0 7.0 10.0 6.0 4.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 2.0 5.5 5.0 5.5 9.0 5.0 Altera Corporation 49 MAX 7000 Programmable Logic Device Family Data Sheet Table 36. EPM7192S Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -7 Min tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (7) (8) 1.7 2.3 0.7 Note (1) Speed Grade -10 Max Min 3.0 3.0 0.5 1.4 1.2 3.2 3.1 2.5 2.7 2.7 2.4 10.0 2.0 2.0 5.0 5.0 1.0 3.0 3.0 1.0 11.0 Unit -15 Min 4.0 2.0 1.0 1.0 1.0 6.0 6.0 1.0 4.0 4.0 2.0 13.0 Max Max ns ns ns ns ns ns ns ns ns ns ns ns Notes to tables: (1) (2) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. (3) (4) (5) (6) (7) (8) 50 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Tables 37 and 38 show the EPM7256S AC operating conditions. Table 37. EPM7256S External Timing Parameters Symbol Parameter Conditions -7 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tODH tCNT fCNT tACNT fACNT fMAX Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Output data hold time after clock Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency Maximum clock frequency (4) (5) 128.2 166.7 (4) 128.2 7.8 100.0 125.0 (2) C1 = 35 pF (3) C1 = 35 pF 3.0 3.0 3.0 1.0 7.8 100.0 10.0 76.9 100.0 C1 = 35 pF 3.0 3.0 0.8 1.9 7.8 4.0 4.0 4.0 1.0 10.0 76.9 13.0 C1 = 35 pF C1 = 35 pF 3.9 0.0 3.0 0.0 4.7 4.0 4.0 2.0 3.0 10.0 6.0 6.0 6.0 1.0 13.0 Note (1) Speed Grade -10 Max 7.5 7.5 7.0 0.0 3.0 0.5 5.0 5.0 5.0 4.0 4.0 15.0 Unit -15 Min Max 10.0 10.0 Min Max 15.0 15.0 ns ns ns ns ns ns 8.0 ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz 11.0 0.0 3.0 0.0 Altera Corporation 51 MAX 7000 Programmable Logic Device Family Data Sheet Table 38. EPM7256S Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -7 Min Max 0.3 0.3 3.4 3.9 1.1 2.6 2.6 0.8 Unit -15 Min Max 2.0 2.0 2.0 8.0 1.0 6.0 6.0 3.0 4.0 5.0 8.0 6.0 7.0 10.0 6.0 4.0 4.0 2.0 1.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.0 1.0 6.0 6.0 1.0 4.0 4.0 2.0 13.0 ns ns ns ns ns ns ns ns ns -10 Min Max 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 2.0 5.5 5.0 5.5 9.0 5.0 2.0 3.0 3.0 0.5 1.1 1.1 2.9 2.6 2.8 2.7 2.7 2.0 2.0 5.0 5.0 1.0 3.0 3.0 1.0 11.0 tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay Output buffer and pad delay Output buffer and pad delay Output buffer enable delay Output buffer enable delay Output buffer enable delay Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (7) (8) C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 35 pF C1 = 35 pF (6) C1 = 35 pF C1 = 5 pF 1.1 1.6 2.4 0.6 0.5 1.0 5.5 4.0 4.5 9.0 4.0 3.0 10.0 52 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. (3) (4) (5) (6) (7) (8) Power Consumption Supply power (P) versus frequency (fMAX in MHz) for MAX 7000 devices is calculated with the following equation: P = PINT + PIO = ICCINT × VCC + PIO The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The ICCINT value, which depends on the switching frequency and the application logic, is calculated with the following equation: ICCINT = A × MCTON + B × (MCDEV – MCTON) + C × MCUSED × fMAX × togLC The parameters in this equation are shown below: MCTON MCDEV MCUSED fMAX togLC A, B, C = Number of macrocells with the Turbo Bit option turned on, as reported in the MAX+PLUS II Report File (.rpt) = Number of macrocells in the device = Total number of macrocells in the design, as reported in the MAX+PLUS II Report File (.rpt) = Highest clock frequency to the device = Average ratio of logic cells toggling at each clock (typically 0.125) = Constants, shown in Table 39 Altera Corporation 53 MAX 7000 Programmable Logic Device Family Data Sheet Table 39. MAX 7000 ICC Equation Constants Device EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S A 1.87 1.63 1.63 1.17 1.17 1.17 1.17 0.93 0.93 0.93 0.93 0.93 0.93 B 0.52 0.74 0.74 0.54 0.54 0.54 0.54 0.40 0.40 0.40 0.40 0.40 0.40 C 0.144 0.144 0.144 0.096 0.096 0.096 0.096 0.040 0.040 0.040 0.040 0.040 0.040 This calculation provides an ICC estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output load. Actual ICC values should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. 54 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 14 shows typical supply current versus frequency for MAX 7000 devices. Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 1 of 2) EPM7032 EPM7064 180 VCC = 5.0 V Room Temperature 151.5 MHz 300 VCC = 5.0 V Room Temperature 151.5 MHz 140 High Speed 200 Typical ICC Active (mA) High Speed 100 Typical ICC Active (mA) 60.2 MHz 100 60 60.2 MHz Low Power 20 0 50 Low Power 100 150 200 0 50 100 150 200 Frequency (MHz) Frequency (MHz) EPM7096 450 VCC = 5.0 V Room Temperature 125 MHz 350 High Speed Typical ICC Active (mA) 250 55.5 MHz 150 Low Power 50 0 50 100 150 Frequency (MHz) Altera Corporation 55 MAX 7000 Programmable Logic Device Family Data Sheet Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 2 of 2) EPM7128E 500 EPM7160E 500 VCC = 5.0 V Room Temperature 400 125 MHz 400 VCC = 5.0 V Room Temperature 100 MHz Typical ICC Active (mA) 300 Typical ICC Active (mA) 300 High Speed 200 High Speed 200 55.5 MHz 100 47.6 MHz 100 Low Power Low Power 150 200 0 50 100 0 50 100 150 200 Frequency (MHz) Frequency (MHz) EPM7192E 500 EPM7256E 750 VCC = 5.0 V Room Temperature 400 90.9 MHz 600 VCC = 5.0 V Room Temperature 90.9 MHz Typical ICC Active (mA) 300 High Speed 43.5 MHz Typical ICC Active (mA) 450 High Speed 300 43.4 MHz 200 100 Low Power 150 Low Power 0 25 50 75 100 125 0 25 50 75 100 125 Frequency (MHz) Frequency (MHz) 56 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 15 shows typical supply current versus frequency for MAX 7000S devices. Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 1 of 2) EPM7032S EPM7064S 60 50 40 30 20 VCC = 5.0 V Room Temperature 142.9 MHz 120 100 80 60 VCC = 5.0 V Room Temperature 175.4 MHz Typical ICC Active (mA) High Speed Typical ICC Active (mA) High Speed 58.8 MHz 40 56.5 MHz 10 Low Power 20 Low Power 0 50 100 150 200 0 50 100 150 200 Frequency (MHz) Frequency (MHz) EPM7128S EPM7160S 280 240 VCC = 5.0 V Room Temperature 300 VCC = 5.0 V Room Temperature 149.3 MHz 147.1 MHz 200 240 Typical ICC Active (mA) 160 High Speed 56.2 MHz Typical ICC Active (mA) 180 High Speed 120 120 80 40 56.5 MHz Low Power 0 50 100 60 Low Power 0 50 100 150 200 150 200 Frequency (MHz) Frequency (MHz) Altera Corporation 57 MAX 7000 Programmable Logic Device Family Data Sheet Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 2 of 2) EPM7192S EPM7256S 300 VCC = 5.0 V Room Temperature 125.0 MHz 400 VCC = 5.0 V Room Temperature 128.2 MHz 240 Typical ICC Active (mA) High Speed 180 300 High Speed Typical ICC Active (mA) 200 120 55.6 MHz 56.2 MHz Low Power 60 100 Low Power 0 25 50 75 100 125 0 25 50 75 100 125 Frequency (MHz) Frequency (MHz) Device Pin-Outs See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. 58 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figures 16 through 22 show the package pin-out diagrams for MAX 7000 devices. Figure 16. 44-Pin Package Pin-Out Diagram Package outlines not drawn to scale. INPUT/OE2/(GCLK2) (1) INPUT/OE2/(GCLK2) (1) INPUT//GCLK1 INPUT/GCLRn INPUT/GCLRn INPUT/GCLK1 INPUT/OE1 INPUT/OE1 GND VCC GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin 1 Pin 34 6 54 3 2 1 44 43 42 41 40 39 38 37 36 I/O I/O/(TDO) (2) I/O I/O VCC I/O I/O I/O/(TCK) (2) I/O GND I/O (2) I/O/(TDI) I/O I/O GND I/O I/O I/O I/O/(TDO) (2) I/O I/O VCC I/O (2) I/O /(TDI) I/O I/O GND I/O I/O 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O 35 34 33 32 31 30 29 I/O (2) I/O/(TMS) I/O VCC I/O I/O EPM7032 I/O I/O/(TCK) (2) I/O GND I/O (2) I/O/(TMS) I/O VCC I/O I/O EPM7032 EPM7032S EPM7064 EPM7064S GND Pin 12 VCC Pin 23 44-Pin PQFP INPUT/OE2/(GCLK2) (1) 44-Pin PLCC INPUT/GCLRn INPUT/GCLK1 INPUT/OE1 GND VCC I/O I/O I/O I/O I/O Pin 1 Pin 34 (2) I/O /(TDI) I/O I/O GND I/O I/O I/O I/O/(TDO) (2) I/O I/O (2) I/O /(TMS) I/O VCC I/O I/O EPM7032 EPM7032S EPM7064 EPM7064S VCC I/O I/O I/O/(TCK) (2) I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND Pin 12 VCC I/O Pin 23 44-Pin TQFP Notes: (1) (2) The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. JTAG ports are available in MAX 7000S devices only. Altera Corporation VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O 59 MAX 7000 Programmable Logic Device Family Data Sheet Figure 17. 68-Pin Package Pin-Out Diagram Package outlines not drawn to scale. I/O I/O I/O GND I/O I/O VCCINT INPUT/OE2/(GCLK2) (1) INPUT/GCLRn INPUT/OE1 INPUT/GCLK1 GND I/O I/O VCCIO I/O I/O I/O VCCIO (2) I/O/(TDI) I/O I/O I/O GND I/O I/O (2) I/O/(TMS) I/O VCCIO I/O I/O I/O I/O GND 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 EPM7064 EPM7096 I/O I/O GND I/O/(TDO) (2) I/O I/O I/O VCCIO I/O I/O I/O/(TCK) (2) I/O GND I/O I/O I/O I/O Notes: (1) (2) The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. JTAG ports are available in MAX 7000S devices only. 60 I/O I/O I/O I/O VCCIO I/O I/O GND VCCINT I/O I/O GND I/O I/O I/O I/O VCCIO 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 68-Pin PLCC Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 18. 84-Pin Package Pin-Out Diagram Package outline not drawn to scale. I/O VCCIO (3) I/O/(TDI) I/O I/O I/O I/O GND I/O I/O I/O (3) I/O/(TMS) I/O I/O VCCIO I/O I/O I/O I/O I/O GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O I/O I/O I/O GND I/O (1) I/O I/O VCCINT INPUT/OE2/(GCLK2) (2) INPUT/GLCRn INPUT/OE1 INPUT/GCLK1 GND I/O I/O I/O (1) VCCIO I/O I/O I/O EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O I/O GND I/O/(TDO) (3) I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/(TCK) (3) I/O I/O GND I/O I/O I/O I/O I/O Notes: (1) (2) (3) Pins 6, 39, 46, and 79 are no-connect (N.C.) pins on EPM7096, EPM7160E, and EPM7160S devices. The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. JTAG ports are available in MAX 7000S devices only. Altera Corporation I/O I/O I/O I/O I/O VCCIO I/O (1) I/O I/O GND VCCINT I/O I/O I/O (1) GND I/O I/O I/O I/O I/O VCCIO 84-Pin PLCC 61 MAX 7000 Programmable Logic Device Family Data Sheet Figure 19. 100-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 81 Pin 1 Pin 76 EPM7064 EPM7096 EPM7128E EPM7128S EPM7160E EPM7064S EPM7128S EPM7160S Pin 31 Pin 51 Pin 26 Pin 51 100-Pin PQFP 100-Pin TQFP Figure 20. 160-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin 121 EPM7192E Bottom View EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E Pin 41 Pin 81 160-Pin PGA 160-Pin PQFP 62 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 21. 192-Pin Package Pin-Out Diagram Package outline not drawn to scale. U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 EPM7256E Bottom View 192-Pin PGA Figure 22. 208-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 157 EPM7256E EPM7256S Pin 53 Pin 105 208-Pin PQFP/RQFP Altera Corporation 63 MAX 7000 Programmable Logic Device Family Data Sheet Revision History The information contained in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.7 supersedes information published in previous versions. The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.7: Version 6.7 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.7: ■ Reference to AN 88: Using the Jam Language for ISP & ICR via an Embedded Processor has been replaced by AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor. Version 6.6 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.6: ■ ■ Added Tables 6 through 8. Added “Programming Sequence” section on page 17 and “Programming Times” section on page 18. Version 6.5 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.5: ■ Updated text on page 16. Version 6.4 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.4: ■ Added Note (5) on page 28. Version 6.3 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.3: ■ Updated the “Open-Drain Output Option (MAX 7000S Devices Only)” section on page 20. 64 Altera Corporation Notes: Altera Corporation 65 MAX 7000 Programmable Logic Device Family Data Sheet 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: literature@altera.com 66 Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. 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