EPM9560

® Includes MAX 9000A MAX 9000 Programmable Logic Device Family Data Sheet June 2003, ver. 6.5 Features... ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1) 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz Fully compliant with the peripheral component interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2 Dual-output macrocell for independent use of combinatorial and registered logic FastTrack® Interconnect for fast, predictable interconnect delays Input/output registers with clear and clock enable on all I/O pins Programmable output slew-rate control to reduce switching noise MultiVolt™ I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices Configurable expander product-term distribution allowing up to 32 product terms per macrocell Programmable power-saving mode for more than 50% power reduction in each macrocell Table 1. MAX 9000 Device Features Feature Usable gates Flipflops Macrocells Logic array blocks (LABs) Maximum user I/O pins tPD1 (ns) tFSU (ns) tFCO (ns) fCNT (MHz) EPM9320 EPM9320A 6,000 484 320 20 168 10 3.0 4.5 144 EPM9400 8,000 580 400 25 159 15 5 7 118 EPM9480 10,000 676 480 30 175 10 3.0 4.8 144 EPM9560 EPM9560A 12,000 772 560 35 216 10 3.0 4.8 144 Altera Corporation DS-M9000-6.5 1 MAX 9000 Programmable Logic Device Family Data Sheet ...and More Features ■ ■ ■ ■ ■ ■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable security bit for protection of proprietary designs Software design support and automatic place-and-route provided by Altera’s MAX+PLUS® II development system on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with Altera’s Master Programming Unit (MPU), BitBlasterTM serial download cable, ByteBlasterTM parallel port download cable, and ByteBlasterMVTM parallel port download cable, as well as programming hardware from third-party manufacturers Offered in a variety of package options with 84 to 356 pins (see Table 2) Note (1) 304-Pin RQFP – – – – 216 – Table 2. MAX 9000 Package Options & I/O Counts Device EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A Notes: (1) 84-Pin PLCC 60 (2) 60 (2) 59 (2) – – – 208-Pin RQFP 132 132 139 146 153 153 240-Pin RQFP – – 159 175 191 191 280-Pin PGA 168 – – – 216 – 356-Pin BGA 168 168 – – 216 216 (2) MAX 9000 device package types include plastic J-lead chip carrier (PLCC), power quad flat pack (RQFP), ceramic pin-grid array (PGA), and ball-grid array (BGA) packages. Perform a complete thermal analysis before committing a design to this device package. See Application Note 74 (Evaluating Power for Altera Devices). 2 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet General Description The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the MAX 9000 family is compliant with the PCI Local Bus Specification, Revision 2.2. Table 3 shows the speed grades available for MAX 9000 devices. Table 3. MAX 9000 Speed Grade Availability Device -10 EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A Speed Grade -15 v v v v v v v v v -20 v Table 4 shows the performance of MAX 9000 devices for typical functions. Table 4. MAX 9000 Performance Application Note (1) Macrocells Used -10 16-bit loadable counter 16-bit up/down counter 16-bit prescaled counter 16-bit address decode 16-to-1 multiplexer Note: (1) Internal logic array block (LAB) performance is shown. Numbers in parentheses show external delays from row input pin to row I/O pin. Speed Grade -15 118 118 118 7.9 (15) 10.9 (18) Units -20 100 100 100 10 (20) 16 (26) MHz MHz MHz ns ns 16 16 16 1 1 144 144 144 5.6 (10) 7.7 (12.1) The MAX 9000 architecture supports high-density integration of systemlevel logic functions. It easily integrates multiple programmable logic devices ranging from PALs, GALs, and 22V10s to field-programmable gate array (FPGA) devices and EPLDs. Altera Corporation 3 MAX 9000 Programmable Logic Device Family Data Sheet All MAX 9000 device packages provide four dedicated inputs for global control signals with large fan-outs. Each I/O pin has an associated I/O cell register with a clock enable control on the periphery of the device. As outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times. MAX 9000 EPLDs provide 5.0-V in-system programmability (ISP). This feature allows the devices to be programmed and reprogrammed on the printed circuit board (PCB) for quick and efficient iterations during design development and debug cycles. MAX 9000 devices are guaranteed for 100 program and erase cycles. MAX 9000 EPLDs contain 320 to 560 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. For increased flexibility, each macrocell offers a dual-output structure that allows the register and the product terms to be used independently. This feature allows register-rich and combinatorialintensive designs to be implemented efficiently. The dual-output structure of the MAX 9000 macrocell also improves logic utilization, thus increasing the effective capacity of the devices. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high-speed parallel expander product terms to provide up to 32 product terms per macrocell. The MAX 9000 family provides programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the user to configure one or more macrocells to operate at 50% or less power while adding only a nominal timing delay. MAX 9000 devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. MAX 9000 devices offer the MultiVolt feature, which allows output drivers to be set for either 3.3-V or 5.0-V operation in mixedvoltage systems. 4 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet The MAX 9000 family is supported by Altera’s MAX+PLUS II development system, a single, integrated software package that offers schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIXworkstation-based EDA tools. The MAX+PLUS II software runs on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. f Functional Description For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet. MAX 9000 devices use a third-generation MAX architecture that yields both high performance and a high degree of utilization for most applications. The MAX 9000 architecture includes the following elements: ■ ■ ■ ■ ■ ■ Logic array blocks Macrocells Expander product terms (shareable and parallel) FastTrack Interconnect Dedicated inputs I/O cells Figure 1 shows a block diagram of the MAX 9000 architecture. Altera Corporation 5 MAX 9000 Programmable Logic Device Family Data Sheet Figure 1. MAX 9000 Device Block Diagram I/O Cell (IOC) IOC IOC IOC IOC IOC IOC IOC IOC Logic Array Block (LAB) IOC FastTrack Interconnect IOC IOC IOC Macrocell LAB Local Array IOC IOC IOC IOC Logic Array Blocks The MAX 9000 architecture is based on linking high-performance, flexible logic array modules called logic array blocks (LABs). LABs consist of 16-macrocell arrays that are fed by the LAB local array, as shown in Figure 2 on page 7. Multiple LABs are linked together via the FastTrack Interconnect, a series of fast, continuous channels that run the entire length and width of the device. The I/O pins are supported by I/O cells (IOCs) located at the end of each row (horizontal) and column (vertical) path of the FastTrack Interconnect. Each LAB is fed by 33 inputs from the row interconnect and 16 feedback signals from the macrocells within the LAB. All of these signals are available within the LAB in their true and inverted form. In addition, 16 shared expander product terms (“expanders”) are available in their inverted form, for a total of 114 signals that feed each product term in the LAB. Each LAB is also fed by two low-skew global clocks and one global clear that can be used for register control signals in all 16 macrocells. 6 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet LABs drive the row and column interconnect directly. Each macrocell can drive out of the LAB onto one or both routing resources. Once on the row or column interconnect, signals can traverse to other LABs or to the IOCs. Figure 2. MAX 9000 Logic Array Block Global Control Select DIN1 GCLK1 GCLK2 DIN2 DIN3 GCLR To Peripheral Bus and Other LABs in the Device DIN4 GOE To Peripheral Bus Row FastTrack Interconnect 33 16 16 LAB Local Array (114 Channels) See Figure 7 for details. Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 16 48 16 48 Column FastTrack Interconnect Shared Expander Signals 16 16 Local Feedback Altera Corporation 7 MAX 9000 Programmable Logic Device Family Data Sheet Macrocells The MAX 9000 macrocell consists of three functional blocks: the product terms, the product-term select matrix, and the programmable register. The macrocell can be individually configured for both sequential and combinatorial logic operation. See Figure 3. Figure 3. MAX 9000 Macrocell & Local Array LAB Local Array 33 Row FastTrack Interconnect Inputs Global Clear Global Clocks 2 Parallel Expanders (from Other Macrocells) Macrocell Input Select Register Bypass Programmable Register ProductTerm Select Matrix Clock/ Enable Select VCC PRN D/T Q ENA CLRN To Row or Column FastTrack Interconnect Clear Select Local Array Feedback 16 Local Feedbacks 16 Shareable Expander Product Combinatorial logic is implemented in the local array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell’s register clear, preset, clock, and clock enable control functions. Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources: ■ ■ Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells The MAX+PLUS II software automatically optimizes product-term allocation according to the logic requirements of the design. 8 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet For registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation with programmable clock control. The flipflop can also be bypassed for combinatorial operation. During design entry, the user specifies the desired register type; the MAX+PLUS II software then selects the most efficient register operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: ■ By either global clock signal. This mode achieves the fastest clock-tooutput performance. By a global clock signal and enabled by an active-high clock enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. By an array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. ■ ■ Two global clock signals are available. As shown in Figure 2, these global clock signals can be the true or the complement of either of the global clock pins (DIN1 and DIN2). Each register also supports asynchronous preset and clear functions. As shown in Figure 3, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear inputs to registers are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the dedicated global clear pin (DIN3). The global clear can be programmed for active-high or active-low operation. All MAX 9000 macrocells offer a dual-output structure that provides independent register and combinatorial logic output within the same macrocell. This function is implemented by a process called register packing. When register packing is used, the product-term select matrix allocates one product term to the D input of the register, while the remaining product terms can be used to implement unrelated combinatorial logic. Both the registered and the combinatorial output of the macrocell can feed either the FastTrack Interconnect or the LAB local array. Altera Corporation 9 MAX 9000 Programmable Logic Device Family Data Sheet Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, some logic functions are more complex and require additional product terms. Although another macrocell can supply the required logic resources, the MAX 9000 architecture also offers both shareable and parallel expander product terms that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the LAB local array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (tLOCAL + tSEXP) is incurred when shareable expanders are used. Figure 4 shows how shareable expanders can feed multiple macrocells. Figure 4. MAX 9000 Shareable Expanders Shareable expanders can be shared by any or all macrocells in the LAB. LAB Local Array 33 Row FastTrack Interconnect Signals Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic 16 Local Feedbacks 16 Shared Expanders 10 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. Figure 5 shows how parallel expanders can feed the neighboring macrocell. Figure 5. MAX 9000 Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. 33 Row FastTrack Interconnect Signals LAB Local Array From Previous Macrocell Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic 16 Local Feedbacks 16 Shared Expanders To Next Macrocell Altera Corporation 11 MAX 9000 Programmable Logic Device Family Data Sheet The MAX+PLUS II Compiler automatically allocates as many as three sets of up to five parallel expanders to macrocells that require additional product terms. Each set of expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14 product terms, the Compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes four product terms, increasing the total delay by 2 × tPEXP. Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lowernumbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. FastTrack Interconnect In the MAX 9000 architecture, connections between macrocells and device I/O pins are provided by the FastTrack Interconnect, a series of continuous horizontal and vertical routing channels that traverse the entire device. This device-wide routing structure provides predictable performance even in complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. Figure 6 shows the interconnection of four adjacent LABs with row and column interconnects. 12 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Figure 6. MAX 9000 Device Interconnect Resources Each LAB is named on the basis of its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device. See Figure 9 for details. IOC1 IOC10 IOC1 IOC10 Column FastTrack Interconnect IOC1 Row FastTrack Interconnect See Figure 8 for details. IOC1 IOC8 IOC8 See Figure 7 for details. LAB A1 LAB A2 IOC1 IOC1 IOC8 IOC8 LAB B1 LAB B2 IOC1 IOC10 IOC1 IOC10 The LABs within MAX 9000 devices are arranged into a matrix of columns and rows. Table 5 shows the number of columns and rows in each MAX 9000 device. Table 5. MAX 9000 Rows & Columns Devices EPM9320, EPM9320A EPM9400 EPM9480 EPM9560, EPM9560A Rows 4 5 6 7 Columns 5 5 5 5 Altera Corporation 13 MAX 9000 Programmable Logic Device Family Data Sheet Each row of LABs has a dedicated row interconnect that routes signals both into and out of the LABs in the row. The row interconnect can then drive I/O pins or feed other LABs in the device. Each row interconnect has a total of 96 channels. Figure 7 shows how a macrocell drives the row and column interconnect. Figure 7. MAX 9000 LAB Connections to Row & Column Interconnect 48 Column Channels 96 Row Channels Each macrocell drives one row channel. LAB Dual-output macrocell feeds both FastTrack Interconnect and LAB local array. Macrocell 1 Macrocell 2 To LAB Local Array Each macrocell drives one of three column channels. Additional multiplexer provides column-to-row path if macrocell drives row channel. Each macrocell in the LAB can drive one of three separate column interconnect channels. The column channels run vertically across the entire device, and are shared by the macrocells in the same column. The MAX+PLUS II Compiler optimizes connections to a column channel automatically. 14 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet A row interconnect channel can be fed by the output of the macrocell through a 4-to-1 multiplexer that the macrocell shares with three column channels. If the multiplexer is used for a macrocell-to-row connection, the three column signals can access another row channel via an additional 3-to-1 multiplexer. Within any LAB, the multiplexers provide all 48 column channels with access to 32 row channels. Row-to-I/O Cell Connections Figure 8 illustrates the connections between row interconnect channels and IOCs. An input signal from an IOC can drive two separate row channels. When an IOC is used as an output, the signal is driven by a 10-to-1 multiplexer that selects the row channels. Each end of the row channel feeds up to eight IOCs on the periphery of the device. Figure 8. MAX 9000 Row-to-IOC Connections 10 IOC1 Row FastTrack Interconnect 96 96 96 10 IOC8 Each IOC is driven by a 10-to-1 multiplexer. Each IOC can drive up to two row channels. Column-to-I/O Cell Connections Each end of a column channel has up to 10 IOCs (see Figure 9). An input signal from an IOC can drive two separate column channels. When an IOC is used as an output, the signal is driven by a 17-to-1 multiplexer that selects the column channels. Altera Corporation 15 MAX 9000 Programmable Logic Device Family Data Sheet Figure 9. MAX 9000 Column-to-IOC Connections IOC1 IOC10 Each IOC is driven by a 17-to-1 multiplexer. Each IOC can drive up to two column channels. 17 48 48 48 17 Column FastTrack Interconnect Dedicated Inputs In addition to the general-purpose I/O pins, MAX 9000 devices have four dedicated input pins. These dedicated inputs provide low-skew, devicewide signal distribution to the LABs and IOCs in the device, and are typically used for global clock, clear, and output enable control signals. The global control signals can feed the macrocell or IOC clock and clear inputs, as well as the IOC output enable. The dedicated inputs can also be used as general-purpose data inputs because they can feed the row FastTrack Interconnect (see Figure 2 on page 7). I/O Cells Figure 10 shows the IOC block diagram. Signals enter the MAX 9000 device from either the I/O pins that provide general-purpose input capability or from the four dedicated inputs. The IOCs are located at the ends of the row and column interconnect channels. 16 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Figure 10. MAX 9000 IOC Peripheral Control Bus [12..0] VCC OE [7..0] 8 To Row or Column FastTrack Interconnect From Row or Column FastTrack Interconnect 13 D CLK [3..0] 4 VCC ENA [5..0] 6 CLR [1..0] 2 VCC Q ENA CLRN Slew-Rate Control I/O pins can be used as input, output, or bidirectional pins. Each IOC has an IOC register with a clock enable input. This register can be used either as an input register for external data that requires fast setup times, or as an output register for data that requires fast clock-to-output performance. The IOC register clock enable allows the global clock to be used for fast clock-to-output performance, while maintaining the flexibility required for selective clocking. The clock, clock enable, clear, and output enable controls for the IOCs are provided by a network of I/O control signals. These signals can be supplied by either the dedicated input pins or internal logic. The IOC control-signal paths are designed to minimize the skew across the device. All control-signal sources are buffered onto high-speed drivers that drive the signals around the periphery of the device. This “peripheral bus” can be configured to provide up to eight output enable signals, up to four clock signals, up to six clock enable signals, and up to two clear signals. Table 6 on page 18 shows the sources that drive the peripheral bus and how the IOC control signals share the peripheral bus. Altera Corporation 17 MAX 9000 Programmable Logic Device Family Data Sheet The output buffer in each IOC has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces board-level noise and adds a nominal timing delay to the output buffer delay (tOD) parameter. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a global basis. The slew rate control affects both rising and falling edges of the output signals. Table 6. Peripheral Bus Sources Peripheral Control Signal Source EPM9320 EPM9320A Row C Row B Row A Row B Row A Row D Row C Row B/GOE Row A/GCLR GCLK1 GCLK2 Row D Row C EPM9400 Row E Row E Row E Row B Row A Row D Row C Row B/GOE Row A/GCLR GCLK1 GCLK2 Row D Row C EPM9480 Row F Row F Row E Row B Row A Row D Row C Row B/GOE Row A/GCLR GCLK1 GCLK2 Row D Row C EPM9560 EPM9560A Row G Row F Row E Row B Row A Row D Row C Row B/GOE Row A/GCLR GCLK1 GCLK2 Row D Row C OE0/ENA0 OE1/ENA1 OE2/ENA2 OE3/ENA3 OE4/ENA4 OE5 OE6 OE7/CLR1 CLR0/ENA5 CLK0 CLK1 CLK2 CLK3 Output Configuration The MAX 9000 device architecture supports the MultiVolt I/O interface feature, which allows MAX 9000 devices to interface with systems of differing supply voltages. The 5.0-V devices in all packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCINT pins must always be connected to a 5.0-V power supply. With a 5.0-V VCCINT level, input voltages are at TTL levels and are therefore compatible with 3.3-V and 5.0-V inputs. 18 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet The VCCIO pins can be connected to either a 3.3-V or 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V power supply, the output levels are compatible with 5.0-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V incur a nominally greater timing delay of tOD2 instead of tOD1. In-System Programmability (ISP) MAX 9000 devices can be programmed in-system through a 4-pin JTAG interface. ISP offers quick and efficient iterations during design development and debug cycles. The MAX 9000 architecture internally generates the 12.0-V programming voltage required to program EEPROM cells, eliminating the need for an external 12.0-V power supply to program the devices on the board. During ISP, the I/O pins are tri-stated to eliminate board conflicts. ISP simplifies the manufacturing flow by allowing the devices to be mounted on a printed circuit board with standard pick-and-place equipment before they are programmed. MAX 9000 devices can be programmed by downloading the information via in-circuit testers, embedded processors, or the Altera BitBlaster, ByteBlaster, or ByteBlasterMV download cable. (The ByteBlaster cable is obsolete and has been replaced by the ByteBlasterMV cable, which can interface with 2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are placed on the board eliminates lead damage on high pin-count packages (e.g., QFP packages) due to device handling. MAX 9000 devices can also be reprogrammed in the field (i.e., product upgrades can be performed in the field via software or modem). In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers platforms have difficulties supporting an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code. Altera Corporation 19 MAX 9000 Programmable Logic Device Family Data Sheet Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 9000 device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1 ms. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1 ms. 2. 3. 4. 5. 6. Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: ■ ■ A pulse time to erase, program, or read the EEPROM cells. A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device. 20 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 9000 Device The time required to program a single MAX 9000 device in-system can be calculated from the following formula: t PR OG =t PP ULSE Cyc le PTC K + ------------------------------f T CK where: tPROG tPPULSE CyclePTCK fTCK = Programming time = Sum of the fixed times to erase, program, and verify the EEPROM cells = Number of TCK cycles to program a device = TCK frequency The ISP times for a stand-alone verification of a single MAX 9000 device can be calculated from the following formula: t VER =t VPULSE C ycle VTC K + -------------------------------f TC K = Verify time where: tVER = Sum of the fixed times to verify the EEPROM cells tVPULSE CycleVTCK = Number of TCK cycles to verify a device Altera Corporation 21 MAX 9000 Programmable Logic Device Family Data Sheet The programming times described in Tables 7 through 9 are associated with the worst-case method using the ISP algorithm. Table 7. MAX 9000 tPULSE & CycleTCK Values Device Programming tPPULSE (s) EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A 11.79 12.00 12.21 12.42 Stand-Alone Verification tVPULSE (s) 0.15 0.15 0.15 0.15 CyclePTCK 2,966,000 3,365,000 3,764,000 4,164,000 CycleVTCK 1,806,000 2,090,000 2,374,000 2,658,000 Tables 8 and 9 show the in-system programming and stand alone verification times for several common test clock frequencies. Table 8. MAX 9000 In-System Programming Times for Different Test Clock Frequencies Device 10 MHz EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A 12.09 12.34 12.59 12.84 fTCK 5 MHz 12.38 12.67 12.96 13.26 Units 200 kHz 26.62 28.83 31.03 33.24 2 MHz 13.27 13.68 14.09 14.50 1 MHz 14.76 15.37 15.98 16.59 500 kHz 17.72 18.73 19.74 20.75 100 kHz 41.45 45.65 49.85 54.06 50 kHz 71.11 79.30 87.49 95.70 s s s s Table 9. MAX 9000 Stand-Alone Verification Times for Different Test Clock Frequencies Device 10 MHz EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A 0.33 0.36 0.39 0.42 fTCK 5 MHz 0.52 0.57 0.63 0.69 Units 200 kHz 9.18 10.60 12.02 13.44 2 MHz 1.06 1.20 1.34 1.48 1 MHz 1.96 2.24 2.53 2.81 500 kHz 3.77 4.33 4.90 5.47 100 kHz 18.21 21.05 23.89 26.73 50 kHz 36.27 41.95 47.63 53.31 s s s s 22 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Programming with External Hardware f MAX 9000 devices can be programmed on Windows-based PCs with an Altera Logic Programmer card, the Master Programming Unit (MPU), and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardware Data Sheet. The MAX+PLUS II software can use text- or waveform-format test vectors created with the MAX+PLUS II Text Editor or Waveform Editor to test a programmed device. For added design verification, designers can perform functional testing to compare the functional behavior of a MAX 9000 device with the results of simulation. Data I/O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices. f IEEE Std. 1149.1 (JTAG) Boundary-Scan Support For more information, see Programming Hardware Manufacturers. MAX 9000 devices support JTAG BST circuitry as specified by IEEE Std. 1149.1-1990. Table 10 describes the JTAG instructions supported by the MAX 9000 family. The pin-out tables starting on page 38 show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins. Table 10. MAX 9000 JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. EXTEST BYPASS Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be shifted out of TDO. Supported by the EPM9320A, EPM9400, EPM9480, and EPM9560A devices only. Selects the user electronic signature (UESCODE) register and allows the UESCODE to be shifted out of TDO serially. This instruction is supported by MAX 9000A devices only. These instructions are used when programming MAX 9000 devices via the JTAG ports with the BitBlaster or ByteBlasterMV download cable, or using a Jam File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format (.svf) File via an embedded processor or test equipment. IDCODE UESCODE ISP Instructions Altera Corporation 23 MAX 9000 Programmable Logic Device Family Data Sheet The instruction register length for MAX 9000 devices is 10 bits. EPM9320A and EPM9560A devices support a 16-bit UESCODE register. Tables 11 and 12 show the boundary-scan register length and device IDCODE information for MAX 9000 devices. Table 11. MAX 9000 Boundary-Scan Register Length Device EPM9320, EPM9320A EPM9400 EPM9480 EPM9560, EPM9560A Boundary-Scan Register Length 504 552 600 648 Table 12. 32-Bit MAX 9000 Device IDCODE Device Version (4 Bits) EPM9320A (3) EPM9400 EPM9480 EPM9560A (3) Notes: (1) (2) (3) Note (1) IDCODE (32 Bits) Part Number (16 Bits) (2) 1001 0011 0010 0000 1001 0100 0000 0000 1001 0100 1000 0000 1001 0101 0110 0000 Manufacturer’s Identity (11 Bits) 00001101110 00001101110 00001101110 00001101110 1 (1 Bit) 1 1 1 1 0000 0000 0000 0000 The IDCODE’s least significant bit (LSB) is always 1. The most significant bit (MSB) is on the left. Although the EPM9320A and EPM9560A devices support the IDCODE instruction, the EPM9320 and EPM9560 devices do not. Figure 11 shows the timing requirements for the JTAG signals. 24 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Figure 11. MAX 9000 JTAG Waveforms TMS TDI tJCP tJCH tJCL tJPSU tJPH TCK tJPZX tJPCO tJPXZ TDO tJSSU tJSH Signal to Be Captured Signal to Be Driven tJSZX tJSCO tJSXZ Table 13 shows the JTAG timing parameters and values for MAX 9000 devices. Table 13. JTAG Timing Parameters & Values for MAX 9000 Devices Symbol tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance 20 45 25 25 25 Parameter Min 100 50 50 20 45 Max Unit ns ns ns ns ns 25 25 25 ns ns ns ns ns ns ns ns f For detailed information on JTAG operation in MAX 9000 devices, refer to Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Altera Corporation 25 MAX 9000 Programmable Logic Device Family Data Sheet Programmable Speed/Power Control MAX 9000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. Because most logic applications require only a small fraction of all gates to operate at maximum frequency, this feature allows total power dissipation to be reduced by 50% or more. The designer can program each individual macrocell in a MAX 9000 device for either high-speed (i.e., with the Turbo Bit™ option turned on) or low-power (i.e., with the Turbo Bit option turned off) operation. As a result, speed-critical paths in the design can run at high speed, while remaining paths operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tLPA) for the LAB local array delay (tLOCAL). Design Security All MAX 9000 EPLDs contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security, because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is erased. MAX 9000 EPLDs are fully functionally tested. Complete testing of each programmable EEPROM bit and all logic functionality ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 12. Test patterns can be used and then erased during the early stages of the production flow. Figure 12. MAX 9000 AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast groundcurrent transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in parentheses are for 3.3-V outputs. Numbers without parentheses are for 5.0-V devices or outputs. VCC 464 Ω (703 Ω) Device Output Generic Testing To Test System 250 Ω (8.06 KΩ) Device input rise and fall times < 3 ns C1 (includes JIG capacitance) 26 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Operating Conditions Tables 14 through 20 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for MAX 9000 devices. Note (1) Conditions With respect to ground (2) Table 14. MAX 9000 Device Absolute Maximum Ratings Symbol VCC VI VCCISP IOUT TSTG TAMB TJ Parameter Supply voltage DC input voltage Supply voltage during in-system programming DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias Min –2.0 –2.0 –2.0 –25 –65 –65 Max 7.0 7.0 7.0 25 150 135 150 135 Unit V V V mA °C °C °C °C Ceramic packages, under bias PQFP and RQFP packages, under bias Table 15. MAX 9000 Device Recommended Operating Conditions Symbol V CCINT VCCI O Parameter Supply voltage for internal logic and input buffers Supply voltage for output drivers, 5.0-V operation Supply voltage for output drivers, 3.3-V operation (3), (4) (3), (4) (3), (4) Conditions Min 4.75 (4.50) 4.75 (4.50) 3.00 (3.00) 4.75 –0.5 0 Max 5.25 (5.50) 5.25 (5.50) 3.60 (3.60) 5.25 V CCINT + 0.5 V CCIO 70 85 90 105 40 40 Unit V V V V V V °C °C °C °C ns ns VCCISP VI VO TA TJ tR tF Supply voltage during in-system programming Input voltage Output voltage Ambient temperature For commercial use For industrial use Junction temperature Input rise time Input fall time For commercial use For industrial use 0 –40 0 –40 Altera Corporation 27 MAX 9000 Programmable Logic Device Family Data Sheet Table 16. MAX 9000 Device DC Operating Conditions Symbol V IH V IL V OH Notes (5), (6) Conditions Min 2.0 –0.5 Parameter High-level input voltage Low-level input voltage 5.0-V high-level TTL output voltage 3.3-V high-level TTL output voltage 3.3-V high-level CMOS output voltage (7) Max V CCINT + 0.5 0.8 Unit V V V V V I OH = –4 mA DC, VCCIO = 4.75 V (8) I OH = –4 mA DC, VCCIO = 3.00 V (8) I OH = –0.1 mA DC, VCCIO = 3.00 V (8) I OL = 12 mA DC, VCCIO = 4.75 V (8) I OL = 12 mA DC, VCCIO = 3.00 V (8) I OL = 0.1 mA DC, VCCIO = 3.00 V (8) 2.4 2.4 VCCIO – 0.2 0.45 0.45 0.2 –10 –40 10 40 V OL 5.0-V low level TTL output voltage 3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage V V V µA µA II I OZ I/O pin leakage current of dedicated input VI = –0.5 to 5.5 V (9) pins Tri-state output off-state current VI = –0.5 to 5.5 V Table 17. MAX 9000 Device Capacitance: EPM9320, EPM9400, EPM9480 & EPM9560 Devices Symbol C DIN1 C DIN2 C DIN3 C DIN4 C I/O Note (10) Max 18 18 17 20 12 Parameter Dedicated input capacitance Dedicated input capacitance Dedicated input capacitance Dedicated input capacitance I/O pin capacitance Conditions V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Min Unit pF pF pF pF pF Table 18. MAX 9000A Device Capacitance: EPM9320A & EPM9560A Devices Symbol C DIN1 C DIN2 C DIN3 C DIN4 C I/O Note (10) Min Max 16 10 10 12 8 Parameter Dedicated input capacitance Dedicated input capacitance Dedicated input capacitance Dedicated input capacitance I/O pin capacitance Conditions V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Unit pF pF pF pF pF Table 19. MAX 9000 Device Typical ICC Supply Current Values Symbol I CC1 Parameter Conditions EPM9320 EPM9400 EPM9480 EPM9560 Unit 106 132 140 146 mA I CC supply current (low-power mode, VI = ground, standby, typical) no load (11) 28 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Table 20. MAX 9000A Device Typical ICC Supply Current Values Symbol I CC1 Parameter Conditions EPM9320A EPM9560A Unit 99 174 mA I CC supply current (low-power mode, VI = ground, no load (11) standby, typical) Notes to tables: (1) (2) See the Operating Requirements for Altera Devices Data Sheet. Minimum DC input on I/O pins is –0.5 V and on the four dedicated input pins is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions. (3) VCC must rise monotonically. (4) Numbers in parentheses are for industrial-temperature-range devices. (5) Typical values are for T A = 25° C and V CC = 5.0 V. (6) These values are specified under the MAX 9000 recommended operating conditions, shown in Table 15 on page 27. (7) During in-system programming, the minimum V IH of the JTAG TCK pin is 3.6 V. The minimum VIH of this pin during JTAG testing remains at 2.0 V. To attain this 3.6-V VIH during programming, the ByteBlaster and ByteBlasterMV download cables must have a 5.0-V VCC. (8) This parameter is measured with 50% of the outputs each sinking 12 mA. The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to the low-level TTL or CMOS output current. (9) JTAG pin input leakage is typically –60 µΑ. (10) Capacitance is sample-tested only and is measured at 25° C. (11) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. I CC is measured at 0° C. Figure 13 shows typical output drive characteristics for MAX 9000 devices with 5.0-V and 3.3-V VCCIO. Figure 13. Output Drive Characteristics of MAX 9000 Devices 5.0-V 150 Note (1) 3.3-V IOL 150 IOL 120 120 Typical IO 90 Output Current (mA) 60 VCCIO = 5.0 V Room Temperature Typical IO 90 Output Current (mA) 60 VCCIO = 3.3 V Room Temperature IOH 30 30 IOH 1 2 3 4 5 1 2 3 3.3 4 5 Output Voltage (V) Output Voltage (V) Note: (1) Output drive characteristics include the JTAG TDO pin. Altera Corporation 29 MAX 9000 Programmable Logic Device Family Data Sheet Timing Model The continuous, high-performance FastTrack Interconnect ensures predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and hence have unpredictable performance. Timing simulation and delay prediction are available with the MAX+PLUS II Simulator and Timing Analyzer, or with industrystandard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides pointto-point timing delay information, setup and hold time prediction, and device-wide performance analysis. The MAX 9000 timing model in Figure 14 shows the delays that correspond to various paths and functions in the circuit. This model contains three distinct parts: the macrocell, IOC, and interconnect, including the row and column FastTrack Interconnect and LAB local array paths. Each parameter shown in Figure 14 is expressed as a worst-case value in the internal timing characteristics tables in this data sheet. Handcalculations that use the MAX 9000 timing model and these timing parameters can be used to estimate MAX 9000 device performance. f For more information on calculating MAX 9000 timing delays, see Application Note 77 (Understanding MAX 9000 Timing). 30 Altera Corporation Altera Corporation tROW Figure 14. MAX 9000 Timing Model Macrocell IOC Output Data Delay tIODR tIODC Logic Array Delay I/O Register Delays tPEXP Parallel Expander Delay Macrocell/ Register Delays Output Delays I/O Pin tLAD FastTrack Drive Delay tFTD tCOL Register Control Delay tLAC tIC tEN tIOC tIORD tIOCOMB tIOSU tIOH tIOCLR tLOCAL tRD tCOMB tSU tH tPRE tCLR I/O Cell Control Delay tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 Shared Expander Delay Input Delay tINREG tINCOMB tSEXP I/O Register Feedback Delay tIOFD Global Input Delays tDIN_D tDIN_CLK tDIN_CLR tDIN_IO MAX 9000 Programmable Logic Device Family Data Sheet tDIN_IOC 31 MAX 9000 Programmable Logic Device Family Data Sheet Tables 21 through 24 show timing for MAX 9000 devices. Table 21. MAX 9000 External Timing Characteristics Symbol Parameter Conditions -10 Min tPD1 tPD2 Row I/O pin input to row I/O pin output Column I/O pin input to column I/O pin output C1 = 35 pF (2) C1 = 35 pF EPM9320A (2) EPM9320 EPM9400 EPM9480 EPM9560A EPM9560 tFSU t FH t FCO t CNT fCNT Global clock setup time for I/O cell Global clock hold time for I/O cell Global clock to I/O cell output delay C1 = 35 pF 3.0 0.0 1.0 (3) 4.8 6.9 144.9 117.6 5.0 0.0 1.0 (3) 7.0 8.5 100.0 11.4 16.6 6.0 0.0 1.0 (3) 8.5 10.0 23.6 Note (1) Speed Grade -15 Min Max 15.0 Unit -20 Min Max 20.0 ns ns Max 10.0 10.8 16.0 16.2 16.4 23.0 23.2 23.4 ns ns ns ns ns ns ns ns ns MHz Minimum internal global clock (4) period Maximum internal global clock (4) frequency 32 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Table 22. MAX 9000 Internal Timing Characteristics Symbol Parameter Conditions Note (1) Speed Grade -10 Min Max 3.5 3.5 3.5 3.5 3.5 0.5 0.5 0.4 2.4 2.0 3.5 3.7 0.5 3.0 3.5 4.0 4.0 1.0 15.0 Unit -20 Min Max 4.5 4.5 4.5 4.5 7.5 2.0 1.0 1.0 4.0 4.5 4.5 4.5 2.0 20.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns -15 Min Max 4.0 4.0 4.0 4.0 5.0 1.0 1.0 1.0 t LAD t LAC tI C t EN t SEXP t PEXP t RD t COMB t SU tH t PRE t CLR tFTD t LPA Logic array delay Logic control array delay Array clock delay Register enable time Shared expander delay Parallel expander delay Register delay Combinatorial delay Register setup time Register hold time Register preset time Register clear time FastTrack drive delay Low-power adder (5) 10.0 Altera Corporation 33 MAX 9000 Programmable Logic Device Family Data Sheet Table 23. IOC Delays Symbol Parameter Conditions -10 Min t I ODR t I ODC t I OC t I ORD t I OCOMB t I OSU t I OH t I OCLR t I OFD t I NREG t I NCOMB tOD1 I/O row output data delay I/O column output data delay I/O control delay I/O register clock-to-output delay I/O combinatorial delay I/O register setup time before clock I/O register hold time after clock I/O register clear delay I/O register feedback delay I/O input pad and buffer to I/O register delay I/O input pad and buffer to row and column delay Output buffer and pad delay, Slow slew rate = off, V CCIO = 5.0 V Output buffer and pad delay, Slow slew rate = off, V CCIO = 3.3 V Output buffer and pad delay, Slow slew rate = on, V CCIO = 5.0 V or 3.3 V Output buffer disable delay Output buffer enable delay, Slow slew rate = off, V CCIO = 5.0 V Output buffer enable delay, Slow slew rate = off, V CCIO = 3.3 V Output buffer enable delay, Slow slew rate = on, V CCIO = 3.3 V or 5.0 V C1 = 35 pF 2.0 1.0 1.5 0.0 3.5 1.5 1.8 (6) Speed Grade -15 Min Max 0.2 0.2 1.0 1.0 1.0 4.0 1.0 3.0 0.0 4.5 2.0 2.5 5.0 1.0 3.0 0.5 5.5 2.5 2.5 Unit -20 Min Max 1.5 1.5 2.0 1.5 1.5 ns ns ns ns ns ns ns ns ns ns ns ns Max 0.2 0.4 0.5 0.6 0.2 tOD2 C1 = 35 pF 2.3 3.5 3.5 ns tOD3 C1 = 35 pF 8.3 10.0 10.5 ns tXZ tZX1 C1 = 5 pF C1 = 35 pF 2.5 2.5 2.5 2.5 2.5 2.5 ns ns tZX2 C1 = 35 pF 3.0 3.5 3.5 ns tZX3 C1 = 35 pF 9.0 10.0 10.5 ns 34 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Table 24. Interconnect Delays Symbol Parameter Conditions -10 Min t LOCAL t ROW t COL t DIN_D t DIN_CLK t DIN_CLR t DIN_IOC t DIN_IO LAB local array delay FastTrack row delay FastTrack column delay Dedicated input data delay Dedicated input clock delay Dedicated input clear delay Dedicated input I/O register clock delay Dedicated input I/O register control delay (6) (6) Speed Grade -15 Min Max 0.5 1.4 1.7 4.5 3.5 5.0 3.5 6.0 Unit -20 Min Max 0.5 2.0 3.0 5.0 4.0 5.5 4.5 6.5 Max 0.5 0.9 0.9 4.0 2.7 4.5 2.5 5.5 ns ns ns ns ns ns ns ns Notes to tables: (1) (2) (3) (4) (5) (6) These values are specified under the MAX 9000 device recommended operating conditions, shown in Table 15 on page 27. See Application Note 77 (Understanding MAX 9000 Timing) for more information on test conditions for tPD1 and tPD2 delays. This parameter is a guideline that is sample-tested only. It is based on extensive device characterization. This parameter applies for both global and array clocking as well as both macrocell and I/O cell registers. Measured with a 16-bit loadable, enabled, up/down counter programmed in each LAB. The t LPA parameter must be added to the tLOCAL parameter for macrocells running in low-power mode. The tROW , tCOL, and tIOC delays are worst-case values for typical applications. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. Power Consumption The supply power (P) versus frequency (fMAX) for MAX 9000 devices can be calculated with the following equation: P = PINT + PIO = ICCINT × VCC + PIO The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The ICCINT value depends on the switching frequency and the application logic. The ICCINT value is calculated with the following equation: ICCINT = (A × MC TON) + [B × (MC DEV – MCTON)] + (C × MCUSED × f MAX × togLC) Altera Corporation 35 MAX 9000 Programmable Logic Device Family Data Sheet The parameters in this equation are shown below: MC TON = Number of macrocells with the Turbo Bit option turned on, as reported in the MAX+PLUS II Report File (.rpt) MCDEV = Number of macrocells in the device MCUSED = Number of macrocells used in the design, as reported in the MAX+PLUS II Report File = Highest clock frequency to the device f MAX = Average percentage of logic cells toggling at each clock togLC (typically 12.5%) A, B, C = Constants, shown in Table 25 Table 25. MAX 9000 ICC Equation Constants Device EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A Constant A 0.81 0.56 0.60 0.68 0.68 0.56 Constant B 0.33 0.31 0.33 0.29 0.26 0.31 Constant C 0.056 0.024 0.053 0.064 0.052 0.024 This calculation provides an ICC estimate based on typical conditions with no output load, using a typical pattern of a 16-bit, loadable, enabled up/down counter in each LAB. Actual ICC values should be verified during operation, because the measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Figure 15 shows typical supply current versus frequency for MAX 9000 devices. 36 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Figure 15. ICC vs. Frequency for MAX 9000 Devices (Part 1 of 2) EPM9320 1000 EPM9320A 1000 800 800 Typical 600 ICC Active (mA) 400 118 MHz Typical ICC Active (mA) 600 400 Turbo 42 MHz 200 200 59 MHz 144 MHz Turbo Non-Turbo 0 25 50 75 100 125 0 25 50 Non-Turbo 75 100 125 Frequency (MHz) Frequency (MHz) EPM9400 1000 EPM9480 1000 800 800 118 MHz Typical ICC Active (mA) 600 118 MHz Typical ICC Active (mA) 600 Turbo 400 400 Turbo 42 MHz 42 MHz 200 200 Non-Turbo 0 25 50 75 100 125 0 25 Non-Turbo 50 75 100 125 Frequency (MHz) Frequency (MHz) Altera Corporation 37 MAX 9000 Programmable Logic Device Family Data Sheet Figure 15. ICC vs. Frequency for MAX 9000 Devices (Part 2 of 2) EPM9560 1000 EPM9560A 1000 800 118 MHz 800 Typical ICC Active (mA) 600 Turbo 400 42 MHz 200 Typical ICC Active (mA) 600 144 MHz 400 Turbo 59 MHz 200 Non-Turbo 0 25 50 75 100 125 0 25 Non-Turbo 50 75 100 125 Frequency (MHz) Frequency (MHz) Device Pin-Outs Tables 26 through 29 show the dedicated pin names and numbers for each EPM9320, EPM9320A, EPM9400, EPM9480, EPM9560, and EPM9560A device package. Table 26. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 1 of 2) Pin Name DIN1 (GCLK1) DIN2 (GCLK2) DIN4 (GOE) TCK TMS TDI TDO Note (1) 356-Pin BGA AD13 AF14 AD1 AC24 A18 E23 A13 D3 84-Pin PLCC (2) 1 84 208-Pin RQFP 182 183 153 4 78 49 79 108 V10 U10 V17 W2 A9 D6 C11 A18 280-Pin PGA (3) DIN3 (GCLR) 13 72 43 55 42 30 38 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Table 26. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 2 of 2) Pin Name GND Note (1) 356-Pin BGA A9, A22, A25, A26, B25, B26, D2, E1, E26, F2, G1, G25, G26, H2, J1, J25, J26, K2, L26, M26, N1, N25, P26, R2, T1, U2, U26, V1, V25, W25, Y26, AA2, AB1, AB26, AC26, AE1, AF1, AF2, AF4, AF7, AF20 D26, F1, H1, K26, N26, P1, U1, W26, AE26, AF25, AF26 84-Pin PLCC (2) 208-Pin RQFP 280-Pin PGA (3) D4, D5, D16, E4, E5, E6, E15, E16, F5, F15, G5, G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P4, P5, P15, P16, R4, R5, R15, R16, T4, T5, T16 6, 18, 24, 25, 48, 14, 20, 24, 31, 35, 61, 67, 70 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 14, 21, 28, 57, 64, 71 VCCINT (5.0 V only) 10, 19, 30, 45, 112, D15, E8, E10, E12, E14, 128, 139, 148 R7, R9, R11, R13, R14, T14 5, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 6, 7, 8, 9, 11, 12, 13, 15, 16, 17, 18, 109, 140, 141, 142, 144, 145, 146, 147, 149, 150, 151 VCCIO 15, 37, 60, 79 (3.3 or 5.0 V) D14, E7, E9, E11, E13, R6, A1, A2, A21, B1, B10, B24, R8, R10, R12, T13, T15 D1, H26, K1, M25, R1, V26, AA1, AC25, AF5, AF8, AF19 B6, K19, L2, L4, L18, L19, M1, M2, M3, M4, M16, M17, M18, M19, N1, N2, N3, N4, N16, N17, N18, N19, P1, P2, P3, P17, P18, P19, R1, R2, R3, R17, R18, R19, T1, T2, T3, T17, T18, T19, U1, U2, U3, U17, U18, U19, V1, V2, V19, W1 B4, B5, B6, B7, B8, B9, B11, B12, B13, B14, B15, B16, B18, B19, B20, B21, B22, B23, C4, C23, D4, D23, E4, E22, F4, F23, G4, H4, H23, J23, K4, L4, L23, N4, P4, P23, R3, R26, T2, T3, T4, T5, T22, T23, T24, T25, T26, U3, U4, U5, U22, U23, U24, U25, V2, V3, V4, V5, V22, V23, V24, W1, W2, W3, W4, W5, W22, W23, W24, Y1, Y2, Y3, Y4, Y5, Y22, Y23, Y24, Y25, AA3, AA4, AA5, AA22, AA23, AA24, AA25, AA26, AB2, AB3, AB4, AB5, AB23, AB24, AB25, AC1, AC2, AC23, AD4, AD23, AE4, AE5, AE6, AE7, AE9, AE11, AE12, AE14, AE15, AE16, AE18, AE19, AE20, AE21, AE22, AE23 E25 168 No Connect (N.C.) 29 VPP (4) Total User I/O Pins (5) 56 60 48 132 C4 168 Altera Corporation 39 MAX 9000 Programmable Logic Device Family Data Sheet Notes: (1) (2) (3) (4) All pins not listed are user I/O pins. Perform a complete thermal analysis before committing a design to this device package. See Application Note 74 (Evaluating Power for Altera Devices). EPM9320A devices are not offered in this package. During in-system programming, each device’s VPP pin must be connected to the 5.0-V power supply. During normal device operation, the VPP pin is pulled up internally and can be connected to the 5.0-V supply or left unconnected. The user I/O pin count includes dedicated input pins and all I/O pins. (5) Table 27. EPM9400 Dedicated Pin-Outs Pin Name DIN1 (GCLK1) DIN2 (GCLK2) DIN3 (GCLR) DIN4 (GOE) TCK TMS TDI TDO GND 2 1 12 74 43 54 42 31 Note (1) 208-Pin RQFP 182 183 153 4 78 49 79 108 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 10, 19, 30, 45, 112, 128, 139, 148 5, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 6, 7, 8, 9, 11, 12, 13, 109, 144, 145, 146, 147, 149, 150, 151 210 211 187 234 91 68 92 114 5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 4, 24, 44, 64, 117, 137, 157, 177 15, 35, 55, 73, 86, 101, 116, 136, 156, 176, 192, 205, 220, 235 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 168, 169, 170, 171, 172, 173, 174, 175, 178, 179, 180, 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 67 159 84-Pin PLCC (2) 240-Pin RQFP 6, 13, 20, 26, 27, 47, 60, 66, 69, 73 VCCINT (5.0 V only) VCCIO (3.3 or 5.0 V) 16, 23, 30, 56, 63, 70 17, 37, 59, 80 No Connect (N.C.) – VPP (3) Total User I/O Pins (4) Notes: (1) (2) (3) 55 59 48 139 (4) All pins not listed are user I/O pins. Perform a complete thermal analysis before committing a design to this device package. See Application Note 74 (Evaluating Power for Altera Devices) for more information. During in-system programming, each device’s VPP pin must be connected to the 5.0-V power supply. During normal device operation, the VPP pin is pulled up internally and can be connected to the 5.0-V supply or left unconnected. The user I/O pin count includes dedicated input pins and all I/O pins. 40 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Table 28. EPM9480 Dedicated Pin-Outs Pin Name DIN1 (GCLK1) DIN2 (GCLK2) DIN3 (GCLR) DIN4 (GOE) TCK TMS TDI TDO GND 182 183 153 4 78 49 79 108 Note (1) 240-Pin RQFP 210 211 187 234 91 68 92 114 5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 208-Pin RQFP 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 VCCINT (5.0 V only) VCCIO (3.3 or 5.0 V) 10, 19, 30, 45, 112, 128, 4, 24, 44, 64, 117, 137, 139, 148 157, 177 5, 25, 36, 55, 72, 91, 111, 15, 35, 55, 73, 86, 101, 127, 138, 159, 176, 195 116, 136, 156, 176, 192, 205, 220, 235 6, 7, 8, 9, 109, 149, 150, 1, 2, 3, 178, 179, 180, 151 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 48 146 67 175 No Connect (N.C.) VPP (2) Total User I/O Pins (3) Notes: (1) (2) (3) All pins not listed are user I/O pins. During in-system programming, each device’s VPP pin must be connected to the 5.0-V power supply. During normal device operation, the VPP pin is pulled up internally and can be connected to the 5.0-V supply or left unconnected. The user I/O pin count includes dedicated input pins and all I/O pins. Altera Corporation 41 MAX 9000 Programmable Logic Device Family Data Sheet Table 29. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 1 of 2) Pin Name DIN1 (GCLK1) DIN2 (GCLK2) DIN4 (GOE) TCK TMS TDI TDO GND Note (1) 356-Pin BGA AD13 AF14 AD1 AC24 A18 E23 A13 D3 A9, A22, A25, A26, B25, B26, D2, E1, E26, F2, G1, G25, G26, H2, J1, J25, J26, K2, L26, M26, N1, N25, P26, R2, T1, U2, U26, V1, V25, W25, Y26, AA2, AB1, AB26, AC26, AE1, AF1, AF2, AF4, AF7, AF20 D26, F1, H1, K26, N26, P1, U1, W26, AE26, AF25, AF26 A1, A2, A21, B1, B10, B24, D1, H26, K1, M25, R1, V26, AA1, AC25, AF5, AF8, AF19 208-Pin RQFP 182 183 240-Pin RQFP 210 211 187 234 91 68 92 114 5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 280-Pin PGA (2) 304-Pin RQFP (2) V10 U10 V17 W2 A9 D6 C11 A18 D4, D5, D16, E4, E5, E6, E15, E16, F5, F15, G5, G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P4, P5, P15, P16, R4, R5, R15, R16, T4, T5, T16 266 267 237 296 114 85 115 144 13, 22, 33, 42, 53, 62, 73, 74, 102, 121, 138, 155, 166, 167, 186, 187, 206, 207, 226, 254, 273, 290 DIN3 (GCLR) 153 4 78 49 79 108 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 VCCINT (5.0 V only) 10, 19, 30, 45, 112, 128, 139, 148 4, 24, 44, 64, 117, D15, E8, E10, 12, 32, 52, 72, 137, 157, 177 E12, E14, R7, R9, 157, 177, 197, R11, R13, R14, 217 T14 3, 23, 43, 63, 91, 108, 127, 156, 176, 196, 216, 243, 260, 279 VCCIO 5, 25, 36, 55, 72, 15, 35, 55, 73, 86, D14, E7, E9, E11, (3.3 or 5.0 V) 91, 111, 127, 138, 101, 116, 136, E13, R6, R8, R10, 159, 176, 195 156, 176, 192, R12, T13, T15 205, 220, 235 42 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Table 29. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 2 of 2) Pin Name No Connect (N.C.) Note (1) 356-Pin BGA B4, B5, B6, B7, B8, B9, B11, B12, B13, B14, B15, B16, B18, B19, B20, B21, B22, B23, C4, C23, D4, D23, E4, E22, F4, F23, G4, H4, H23, J23, K4, L4, L23, N4, P4, P23, T4, T23, U4, V4, V23, W4, Y4, AA4, AA23, AB4, AB23, AC23, AD4, AD23, AE4, AE5, AE6, AE7, AE9, AE11, AE12, AE14, AE15, AE16, AE18, AE19, AE20, AE21, AE22, AE23 E25 216 208-Pin RQFP 109 – 240-Pin RQFP 280-Pin PGA (2) 304-Pin RQFP (2) B6, W1 1, 2, 76, 77, 78, 79, 80, 81, 82, 83, 84, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 297, 298, 299, 300, 301, 302, 303, 304 VPP (3) Total User I/O Pins (4) Notes: (1) (2) (3) 48 153 67 191 C4 216 75 216 (4) All pins not listed are user I/O pins. EPM9560A devices are not offered in this package. During in-system programming, each device’s VPP pin must be connected to the 5.0-V power supply. During normal device operation, the VPP pin is pulled up internally and can be connected to the 5.0-V supply or left unconnected. The user I/O pin count includes dedicated input pins and all I/O pins. Altera Corporation 43 MAX 9000 Programmable Logic Device Family Data Sheet Revision History Information contained in the MAX 9000 Programmable Logic Device Family Data Sheet version 6.5 supersedes information published in previous versions. Version 6.5 Version 6.6 of the MAX 9000 Programmable Logic Device Family Data Sheet contains the following change: ■ ■ Added Tables 7 through 9. Added “Programming Sequence” on page 20 and “Programming Times” on page 20 Version 6.4 Version 6.4 of the MAX 9000 Programmable Logic Device Family Data Sheet contains the following change: Updated text on page 23. Version 6.3 Version 6.3 of the MAX 9000 Programmable Logic Device Family Data Sheet contains the following change: added Note (7) to Table 16. ® 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 44 Printed on Recycled Paper. Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Altera Corporation 45 MAX 9000 Programmable Logic Device Family Data Sheet 46 Altera Corporation