FLEX8000

FLEX 8000 ® Programmable Logic Device Family Data Sheet January 2003, ver. 11.1 1 Features... ■ ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1) – 2,500 to 16,000 usable gates – 282 to 1,500 registers System-level features – In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller – Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices – MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels – Low power consumption (typical specification is 0.5 mA or less in standby mode) Flexible interconnect – FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implements internal tri-state nets Powerful I/O pins Programmable output slew-rate control reduces switching noise 3 FLEX 8000 Table 1. FLEX 8000 Device Features Feature Usable gates Flipflops Logic array blocks (LABs) Logic elements (LEs) Maximum user I/O pins EPF8282A EPF8282AV 2,500 282 26 208 78 EPF8452A 4,000 452 42 336 120 EPF8636A 6,000 636 63 504 136 EPF8820A 8,000 820 84 672 152 EPF81188A EPF81500A 12,000 1,188 126 1,008 184 16,000 1,500 162 1,296 208 Altera Corporation DS-F8000-11.1 1 FLEX 8000 Programmable Logic Device Family Data Sheet JTAG BST circuitry Yes ■ ■ ■ ■ No Yes Yes No Yes ...and More Features ■ Peripheral register for fast setup and clock-to-output delay Fabricated on an advanced SRAM process Available in a variety of packages with 84 to 304 pins (see Table 2) Software design support and automatic place-and-route provided by the Altera® MAX+PLUS® II development system for Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and Veribest Note (1) 192Pin PGA 208Pin PQFP 225Pin BGA 232Pin PGA 240Pin PQFP 280Pin PGA 304Pin RQFP Table 2. FLEX 8000 Package Options & I/O Pin Count Device 84Pin PLCC 68 68 68 112 100Pin TQFP 78 78 68 144Pin TQFP 160Pin PQFP 160Pin PGA EPF8282A EPF8282AV EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A Note: (1) 120 118 120 120 136 152 136 152 148 152 184 184 181 208 208 FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages. General Description Altera’s Flexible Logic Element MatriX (FLEX®) family combines the benefits of both erasable programmable logic devices (EPLDs) and fieldprogrammable gate arrays (FPGAs). The FLEX 8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources. 2 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers. The high-pin-count packages can integrate multiple 32-bit buses into a single device. Table 3 shows FLEX 8000 performance and LE requirements for typical applications. Table 3. FLEX 8000 Performance Application LEs Used A-2 16-bit loadable counter 16-bit up/down counter 24-bit accumulator 16-bit address decode 16-to-1 multiplexer 16 16 24 4 10 125 125 87 4.2 6.6 Speed Grade A-3 95 95 67 4.9 7.9 Units A-4 83 83 58 6.3 9.5 MHz MHz MHz ns ns 3 FLEX 8000 All FLEX 8000 device packages provide four dedicated inputs for synchronous control signals with large fan-outs. Each I/O pin has an associated register on the periphery of the device. As outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times. The logic and interconnections in the FLEX 8000 architecture are configured with CMOS SRAM elements. FLEX 8000 devices are configured at system power-up with data stored in an industry-standard parallel EPROM or an Altera serial configuration devices, or with data provided by a system controller. Altera offers the EPC1, EPC1213, EPC1064, and EPC1441 configuration devices, which configure FLEX 8000 devices via a serial data stream. Configuration data can also be stored in an industry-standard 32 K × 8 bit or larger configuration device, or downloaded from system RAM. After a FLEX 8000 device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 100 ms, realtime changes can be made during system operation. For information on how to configure FLEX 8000 devices, go to the following documents: ■ ■ ■ ■ ■ Configuration Devices for APEX & FLEX Devices Data Sheet BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet Application Note 33 (Configuring FLEX 8000 Devices) Application Note 38 (Configuring Multiple FLEX 8000 Devices) Altera Corporation 3 FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure FLEX 8000 devices serially, in parallel, synchronously, or asynchronously. The interface also enables the microprocessor to treat a FLEX 8000 device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to create configuration software. The FLEX 8000 family is supported by Altera’s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including the Altera Hardware Description Language (AHDL), VHDL, and Verilog HDL—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, library of parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industrystandard PC- and UNIX workstation-based EDA tools. The MAX+PLUS II software runs on Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. The MAX+PLUS II software interfaces easily with common gate array EDA tools for synthesis and simulation. For example, the MAX+PLUS II software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains EDA libraries that use device-specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the MAX+PLUS II development system includes DesignWare functions that are optimized for the FLEX 8000 architecture. f Functional Description For more information on the MAX+PLUS II software, go to the MAX+PLUS II Programmable Logic Development System & Software Data Sheet. The FLEX 8000 architecture incorporates a large matrix of compact building blocks called logic elements (LEs). Each LE contains a 4-input LUT that provides combinatorial logic capability and a programmable register that offers sequential logic capability. The fine-grained structure of the LE provides highly efficient logic implementation. Eight LEs are grouped together to form a logic array block (LAB). Each FLEX 8000 LAB is an independent structure with common inputs, interconnections, and control signals. The LAB architecture provides a coarse-grained structure for high device performance and easy routing. 4 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group of eight LEs is combined into an LAB; LABs are arranged into rows and columns. The I/O pins are supported by I/O elements (IOEs) located at the ends of rows and columns. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. Figure 1. FLEX 8000 Device Block Diagram I/O Element (IOE) IOE IOE IOE IOE IOE IOE IOE IOE Logic Array Block (LAB) IOE FastTrack Interconnect IOE 3 FLEX 8000 IOE IOE Logic Element (LE) IOE IOE IOE IOE Signal interconnections within FLEX 8000 devices and between device pins are provided by the FastTrack Interconnect, a series of fast, continuous channels that run the entire length and width of the device. IOEs are located at the end of each row (horizontal) and column (vertical) FastTrack Interconnect path. Altera Corporation 5 FLEX 8000 Programmable Logic Device Family Data Sheet Logic Array Block A logic array block (LAB) consists of eight LEs, their associated carry and cascade chains, LAB control signals, and the LAB local interconnect. The LAB provides the coarse-grained structure of the FLEX 8000 architecture. This structure enables FLEX 8000 devices to provide efficient routing, high device utilization, and high performance. Figure 2 shows a block diagram of the FLEX 8000 LAB. Figure 2. FLEX 8000 Logic Array Block Dedicated Inputs Row Interconnect 24 4 8 4 Carry-In and Cascade-In from LAB on Left 4 2 8 16 LAB Local Interconnect (32 channels) See Figure 8 for details. LAB Control Signals 4 4 4 4 4 4 4 4 LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 Column-to-Row Interconnect Column Interconnect 8 2 Carry-Out and Cascade-Out to LAB on Right 6 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Each LAB provides four control signals that can be used in all eight LEs. Two of these signals can be used as clocks, and the other two for clear/preset control. The LAB control signals can be driven directly from a dedicated input pin, an I/O pin, or any internal signal via the LAB local interconnect. The dedicated inputs are typically used for global clock, clear, or preset signals because they provide synchronous control with very low skew across the device. FLEX 8000 devices support up to four individual global clock, clear, or preset control signals. If logic is required on a control signal, it can be generated in one or more LEs in any LAB and driven into the local interconnect of the target LAB. Logic Element The logic element (LE) is the smallest unit of logic in the FLEX 8000 architecture, with a compact size that provides efficient logic utilization. Each LE contains a 4-input LUT, a programmable flipflop, a carry chain, and cascade chain. Figure 3 shows a block diagram of an LE. Figure 3. FLEX 8000 LE Carry-In Cascade-In 3 FLEX 8000 DFF DATA1 DATA2 DATA3 DATA4 Look-Up Table (LUT) Carry Chain Cascade Chain D PRN Q LE-Out CLRN LABCTRL1 LABCTRL2 Clear/ Preset Logic Clock Select LABCTRL3 LABCTRL4 Carry-Out Cascade-Out The LUT is a function generator that can quickly compute any function of four variables. The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock, clear, and preset control signals on the flipflop can be driven by dedicated input pins, general-purpose I/O pins, or any internal logic. For purely combinatorial functions, the flipflop is bypassed and the output of the LUT goes directly to the output of the LE. Altera Corporation 7 FLEX 8000 Programmable Logic Device Family Data Sheet The FLEX 8000 architecture provides two dedicated high-speed data paths—carry chains and cascade chains—that connect adjacent LEs without using local interconnect paths. The carry chain supports highspeed counters and adders; the cascade chain implements wide-input functions with minimum delay. Carry and cascade chains connect all LEs in an LAB and all LABs in the same row. Heavy use of carry and cascade chains can reduce routing flexibility. Therefore, the use of carry and cascade chains should be limited to speed-critical portions of a design. Carry Chain The carry chain provides a very fast (less than 1 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit moves forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX 8000 architecture to implement high-speed counters and adders of arbitrary width. The MAX+PLUS II Compiler can create carry chains automatically during design processing; designers can also insert carry chain logic manually during design entry. Figure 4 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. The register is typically bypassed for simple adders, but can be used for an accumulator function. Another portion of the LUT and the carry chain logic generate the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to another LE, where it can be used as a general-purpose signal. In addition to mathematical functions, carry chain logic supports very fast counters and comparators. 8 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 4. FLEX 8000 Carry Chain Operation Carry-In a1 b1 LU Register s1 Carry LE1 a2 b2 LUT Register s2 Carry Chain LE2 3 FLEX 8000 an bn LUT Register sn Carry Chain LEn LUT Register Carry-Out Carry Chain LEn + 1 Cascade Chain With the cascade chain, the FLEX 8000 architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR (via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each additional LE provides four more inputs to the effective width of a function, with a delay as low as 0.6 ns per LE. Altera Corporation 9 FLEX 8000 Programmable Logic Device Family Data Sheet The MAX+PLUS II Compiler can create cascade chains automatically during design processing; designers can also insert cascade chain logic manually during design entry. Cascade chains longer than eight LEs are automatically implemented by linking LABs together. The last LE of an LAB cascades to the first LE of the next LAB. Figure 5 shows how the cascade function can connect adjacent LEs to form functions with a wide fan-in. These examples show functions of 4n variables implemented with n LEs. For a device with an A-2 speed grade, the LE delay is 2.4 ns; the cascade chain delay is 0.6 ns. With the cascade chain, 4.2 ns is needed to decode a 16-bit address. Figure 5. FLEX 8000 Cascade Chain Operation AND Cascade Chain LE1 d[3..0] LUT d[3..0] LUT OR Cascade Chain LE1 LE2 d[7..4] LUT d[7..4] LUT LE2 LEn d[(4n-1)..4(n-1)] LUT d[(4n-1)..4(n-1)] LUT LEn LE Operating Modes The FLEX 8000 LE can operate in one of four modes, each of which uses LE resources differently. See Figure 6. In each mode, seven of the ten available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. The three remaining inputs to the LE provide clock, clear, and preset control for the register. The MAX+PLUS II software automatically chooses the appropriate mode for each application. Design performance can also be enhanced by designing for the operating mode that supports the desired application. 10 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 6. FLEX 8000 LE Operating Modes Normal Mode Carry-In data1 data2 4-Input LUT CLRN Cascade-Out data4 Cascade-In PRN D Q LE-Out data3 Arithmetic Mode Carry-In Cascade-In PRN Q LE-Out D data1 data2 3-Input LUT CLRN 3-Input LUT Carry-Out Cascade-Out 3 FLEX 8000 Up/Down Counter Mode Carry-In Cascade-In data1 (ena) data2 (nclr) data3 (data) 3-Input LUT 1 0 D PRN Q LE-Out 3-Input LUT data4 (nload) Carry-Out Cascade-Out CLRN Clearable Counter Mode Carry-In data1 (ena) data2 (nclr) data3 (data) 3-Input LUT 1 0 D PRN Q LE-Out 3-Input LUT data4 (nload) Carry-Out Cascade-Out CLRN Altera Corporation 11 FLEX 8000 Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in signal are the inputs to a 4-input LUT. Using a configurable SRAM bit, the MAX+PLUS II Compiler automatically selects the carry-in or the DATA3 signal as an input. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. The LE-Out signal—the data output of the LE—is either the combinatorial output of the LUT and cascade chain, or the data output (Q)of the programmable register. Arithmetic Mode The arithmetic mode offers two 3-input LUTs that are ideal for implementing adders, accumulators, and comparators. One LUT provides a 3-bit function; the other generates a carry bit. As shown in Figure 6, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, in an adder, this output is the sum of three bits: a, b, and the carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports a cascade chain. Up/Down Counter Mode The up/down counter mode offers counter enable, synchronous up/down control, and data loading options. These control signals are generated by the data inputs from the LAB local interconnect, the carry-in signal, and output feedback from the programmable register. Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data can also be loaded asynchronously with the clear and preset register control signals, without using the LUT resources. Clearable Counter Mode The clearable counter mode is similar to the up/down counter mode, but supports a synchronous clear instead of the up/down control; the clear function is substituted for the cascade-in signal in the up/down counter mode. Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer, and the output of this multiplexer is ANDed with a synchronous clear. 12 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Internal Tri-State Emulation Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus. In a physical tri-state bus, the tri-state buffers’ output enable signals select the signal that drives the bus. However, if multiple output enable signals are active, contending signals can be driven onto the bus. Conversely, if no output enable signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The MAX+PLUS II software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable register’s clear and preset functions is controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The clear and preset control structure of the LE is used to asynchronously load signals into a register. The register can be set up so that LABCTRL1 implements an asynchronous load. The data to be loaded is driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the register. During compilation, the MAX+PLUS II Compiler automatically selects the best control signal implementation. Because the clear and preset functions are active-low, the Compiler automatically assigns a logic high to an unused clear or preset. The clear and preset logic is implemented in one of the following six asynchronous modes, which are chosen during design entry. LPM functions that use registers will automatically use the correct asynchronous mode. See Figure 7. ■ ■ ■ ■ ■ ■ 3 FLEX 8000 Clear only Preset only Clear and preset Load with clear Load with preset Load without clear or preset Altera Corporation 13 FLEX 8000 Programmable Logic Device Family Data Sheet Figure 7. FLEX 8000 LE Asynchronous Clear & Preset Modes Asynchronous Clear VCC PRN D Q D Asynchronous Preset LABCTRL1 or LABCTRL2 PRN Q Asynchronous Clear & Preset LABCTRL1 PRN D Q CLRN LABCTRL1 or LABCTRL2 CLRN LABCTRL2 CLRN Asynchronous Load with Clear LABCTRL1 (Asynchronous Load) DATA3 (Data) NOT PRN D Q NOT CLRN LABCTRL2 (Clear) Asynchronous Load with Preset LABCTRL1 (Asynchronous Load) NOT LABCTRL2 (Preset) PRN D DATA3 (Data) CLRN NOT Q Asynchronous Load without Clear or Preset NOT LABCTRL1 (Asynchronous Load) DATA3 (Data) PRN D Q CLRN NOT 14 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Asynchronous Clear A register is cleared by one of the two LABCTRL signals. When the CLRn port receives a low signal, the register is set to zero. Asynchronous Preset An asynchronous preset is implemented as either an asynchronous load or an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRLl asynchronously loads a 1 into the register. Alternatively, the MAX+PLUS II software can provide preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore, if a register is preset by only one of the two LABCTRL signals, the DATA3 input is not needed and can be used for one of the LE operating modes. Asynchronous Clear & Preset When implementing asynchronous clear and preset, LABCTRL1 controls the preset and LABCTRL2 controls the clear. The DATA3 input is tied to VCC; therefore, asserting LABCTRL1 asynchronously loads a 1 into the register, effectively presetting the register. Asserting LABCTRL2 clears the register. Asynchronous Load with Clear When implementing an asynchronous load with the clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear. LABCTRL2 implements the clear by controlling the register clear. Asynchronous Load with Preset When implementing an asynchronous load in conjunction with a preset, the MAX+PLUS II software provides preset control by using the clear and inverting the input and output of the register. Asserting LABCTRL2 clears the register, while asserting LABCTRL1 loads the register. The MAX+PLUS II software inverts the signal that drives the DATA3 signal to account for the inversion of the register’s output. Asynchronous Load without Clear or Preset When implementing an asynchronous load without the clear or preset, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear. 3 FLEX 8000 Altera Corporation 15 FLEX 8000 Programmable Logic Device Family Data Sheet FastTrack Interconnect In the FLEX 8000 architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, a series of continuous horizontal (row) and vertical (column) routing channels that traverse the entire FLEX 8000 device. This device-wide routing structure provides predictable performance even in complex designs. In contrast, the segmented routing structure in FPGAs requires switch matrices to connect a variable number of routing paths, which increases the delays between logic resources and reduces performance. The LABs within FLEX 8000 devices are arranged into a matrix of columns and rows. Each row of LABs has a dedicated row interconnect that routes signals both into and out of the LABs in the row. The row interconnect can then drive I/O pins or feed other LABs in the device. Figure 8 shows how an LE drives the row and column interconnect. Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect 16 Column Channels Row Channels (1) Each LE drives one row channel. LE1 LE2 to Local to Local Feedback Feedback Note: (1) See Table 4 for the number of row channels. Each LE drives up to two column channels. 16 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Each LE in an LAB can drive up to two separate column interconnect channels. Therefore, all 16 available column channels can be driven by the LAB. The column channels run vertically across the entire device, and share access to LABs in the same column but in different rows. The MAX+PLUS II Compiler chooses which LEs must be connected to a column channel. A row interconnect channel can be fed by the output of the LE or by two column channels. These three signals feed a multiplexer that connects to a specific row channel. Each LE is connected to one 3-to-1 multiplexer. In an LAB, the multiplexers provide all 16 column channels with access to 8 row channels. Each column of LABs has a dedicated column interconnect that routes signals out of the LABs into the column. The column interconnect can then drive I/O pins or feed into the row interconnect to route the signals to other LABs in the device. A signal from the column interconnect, which can be either the output of an LE or an input from an I/O pin, must transfer to the row interconnect before it can enter an LAB. Table 4 summarizes the FastTrack Interconnect resources available in each FLEX 8000 device. 3 Table 4. FLEX 8000 FastTrack Interconnect Resources FLEX 8000 Device EPF8282A EPF8282AV EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A Rows 2 2 3 4 6 6 Channels per Row 168 168 168 168 168 216 Columns 13 21 21 21 21 27 Channels per Column 16 16 16 16 16 16 Figure 9 shows the interconnection of four adjacent LABs, with row, column, and local interconnects, as well as the associated cascade and carry chains. Altera Corporation 17 FLEX 8000 Programmable Logic Device Family Data Sheet Figure 9. FLEX 8000 Device Interconnect Resources Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device. See Figure 12 for details. IOE IOE IOE IOE Column Interconnect 1 IOE Row Interconnect IOE 1 See Figure 11 for details. 8 IOE IOE 8 LAB A1 LAB A2 1 IOE IOE 1 8 IOE IOE 8 LAB B1 LAB B2 LAB Local Interconnect Cascade & Carry Chain IOE IOE IOE IOE I/O Element An IOE contains a bidirectional I/O buffer and a register that can be used either as an input register for external data that requires a fast setup time, or as an output register for data that requires fast clock-to-output performance. IOEs can be used as input, output, or bidirectional pins. The MAX+PLUS II Compiler uses the programmable inversion option to automatically invert signals from the row and column interconnect where appropriate. Figure 10 shows the IOE block diagram. 18 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 10. FLEX 8000 IOE Numbers in parentheses are for EPF81500A devices only. I/O Controls To Row or Column Interconnect (6) 6 Programmable Inversion VCC From Row or Column Interconnect D Q CLRN Slew-Rate Control VCC 3 FLEX 8000 CLR0 CLR1/OE0 CLK0 CLK1/OE1 OE2 OE3 Row-to-IOE Connections Figure 11 illustrates the connection between row interconnect channels and IOEs. An input signal from an IOE can drive two separate row channels. When an IOE is used as an output, the signal is driven by an n-to-1 multiplexer that selects the row channels. The size of the multiplexer varies with the number of columns in a device. EPF81500A devices use a 27-to-1 multiplexer; EPF81188A, EPF8820A, EPF8636A, and EPF8452A devices use a 21-to-1 multiplexer; and EPF8282A and EPF8282AV devices use a 13-to-1 multiplexer. Eight IOEs are connected to each side of the row channels. Altera Corporation (OE [4..9]) 19 FLEX 8000 Programmable Logic Device Family Data Sheet Figure 11. FLEX 8000 Row-to-IOE Connections Numbers in parentheses are for EPF81500A devices. See Note (1). 2 2 2 2 IOE 1 Each IOE can drive up to two row channels. n n IOE 2 2 2 2 2 n IOE 3 n Row Interconnect 168 (216) 168 (216) 2 2 2 2 IOE 4 n IOE 5 Each IOE is driven by an n-to-1 multiplexer. n IOE 6 n IOE 7 n IOE 8 2 2 2 2 Note: (1) n = 13 for EPF8282A and EPF8282AV devices. n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices. n = 27 for EPF81500A devices. Column-to-IOE Connections Two IOEs are located at the top and bottom of the column channels (see Figure 12). When an IOE is used as an input, it can drive up to two separate column channels. The output signal to an IOE can choose from 8 of the 16 column channels through an 8-to-1 multiplexer. 20 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 12. FLEX 8000 Column-to-IOE Connections Each IOE is driven by an 8-to-1 multiplexer. IOE IOE Each IOE can drive up to two column signals. 8 8 16 Column Interconnect In addition to general-purpose I/O pins, FLEX 8000 devices have four dedicated input pins. These dedicated inputs provide low-skew, devicewide signal distribution, and are typically used for global clock, clear, and preset control signals. The signals from the dedicated inputs are available as control signals for all LABs and I/O elements in the device. The dedicated inputs can also be used as general-purpose data inputs because they can feed the local interconnect of each LAB in the device. Signals enter the FLEX 8000 device either from the I/O pins that provide general-purpose input capability or from the four dedicated inputs. The IOEs are located at the ends of the row and column interconnect channels. I/O pins can be used as input, output, or bidirectional pins. Each I/O pin has a register that can be used either as an input register for external data that requires fast setup times, or as an output register for data that requires fast clock-to-output performance. The MAX+PLUS II Compiler uses the programmable inversion option to invert signals automatically from the row and column interconnect when appropriate. The clock, clear, and output enable controls for the IOEs are provided by a network of I/O control signals. These signals can be supplied by either the dedicated input pins or by internal logic. The IOE control-signal paths are designed to minimize the skew across the device. All control-signal sources are buffered onto high-speed drivers that drive the signals around the periphery of the device. This “peripheral bus” can be configured to provide up to four output enable signals (10 in EPF81500A devices), and up to two clock or clear signals. Figure 13 on page 22 shows how two output enable signals are shared with one clock and one clear signal. Altera Corporation 21 3 FLEX 8000 FLEX 8000 Programmable Logic Device Family Data Sheet The signals for the peripheral bus can be generated by any of the four dedicated inputs or signals on the row interconnect channels, as shown in Figure 13. The number of row channels in a row that can drive the peripheral bus correlates to the number of columns in the FLEX 8000 device. EPF8282A and EPF8282AV devices use 13 channels; EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices use 21 channels; and EPF81500A devices use 27 channels. The first LE in each LAB is the source of the row channel signal. The six peripheral control signals (12 in EPF81500A devices) can be accessed by each IOE. Figure 13. FLEX 8000 Peripheral Bus Numbers in parentheses are for EPF81500A devices. Peripheral Control Signals Programmable Inversion Dedicated Inputs 1 2 4 Row Channels n (1) CLK0 CLK1/OE1 Note: (1) n = 13 for EPF8282A and EPF8282AV devices. n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices. n = 27 for EPF81500A devices. 22 Altera Corporation CLR1/OE0 OE3 (OE[4..9]) CLR0 OE2 FLEX 8000 Programmable Logic Device Family Data Sheet Table 5 lists the source of the peripheral control signal for each FLEX 8000 device by row. Table 5. Row Sources of FLEX 8000 Peripheral Control Signals Peripheral Control Signal CLK0 CLK1/OE1 CLR0 CLR1/OE0 OE2 OE3 OE4 OE5 OE6 OE7 OE8 OE9 EPF8282A EPF8282AV Row A Row B Row A Row B Row A Row B – – – – – – EPF8452A Row A Row B Row A Row B Row A Row B – – – – – – EPF8636A Row A Row C Row B Row C Row A Row B – – – – – – EPF8820A Row A Row C Row B Row D Row A Row B – – – – – – EPF81188A Row E Row B Row F Row C Row D Row A – – – – – – EPF81500A Row E Row B Row F Row C Row A Row A Row B Row C Row D Row D Row E 3 FLEX 8000 Row F Output Configuration This section discusses slew-rate control and MultiVolt I/O interface operation for FLEX 8000 devices. Slew-Rate Control The output buffer in each IOE has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slow slew rate reduces system noise by slowing signal transitions, adding a maximum delay of 3.5 ns. The slow slew-rate setting affects only the falling edge of a signal. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a global basis. f For more information on high-speed system design, go to Application Note 75 (High-Speed Board Designs). Altera Corporation 23 FLEX 8000 Programmable Logic Device Family Data Sheet MultiVolt I/O Interface The FLEX 8000 device architecture supports the MultiVolt I/O interface feature, which allows EPF81500A, EPF81188A, EPF8820A, and EPF8636A devices to interface with systems with differing supply voltages. These devices in all packages—except for EPF8636A devices in 84-pin PLCC packages—can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCINT pins must always be connected to a 5.0-V power supply. With a 5.0-V VCCINT level, input voltages are at TTL levels and are therefore compatible with 3.3-V and 5.0-V inputs. The VCCIO pins can be connected to either a 3.3-V or 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V power supply, the output levels are compatible with 5.0-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V incur a nominally greater timing delay of tOD2 instead of tOD1. See Table 8 on page 26. IEEE Std. 1149.1 (JTAG) Boundary-Scan Support The EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices provide JTAG BST circuitry. FLEX 8000 devices with JTAG circuitry support the JTAG instructions shown in Table 6. Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. EXTEST BYPASS Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. 24 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet The instruction register length for FLEX 8000 devices is three bits. Table 7 shows the boundary-scan register length for FLEX 8000 devices. Table 7. FLEX 8000 Boundary-Scan Register Length Device EPF8282A, EPF8282AV EPF8636A EPF8820A EPF81500A Boundary-Scan Register Length 273 417 465 645 FLEX 8000 devices that support JTAG include weak pull-ups on the JTAG pins. Figure 14 shows the timing requirements for the JTAG signals. Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Waveforms TMS 3 FLEX 8000 tJCP tJCH tJCL tJPSU tJPH TDI TCK tJPZX tJPCO tJPXZ TDO tJSSU tJSH Signal to Be Captured Signal to Be Driven tJSZX tJSCO tJSXZ Table 8 shows the timing parameters and values for EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices. Altera Corporation 25 FLEX 8000 Programmable Logic Device Family Data Sheet Table 8. JTAG Timing Parameters & Values Symbol Parameter EPF8282A EPF8282AV EPF8636A EPF8820A EPF81500A Min tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high-impedance to valid output JTAG port valid output to high-impedance Capture register setup time Capture register hold time Update register clock to output Update register high-impedance to valid output Update register valid output to high-impedance 20 45 35 35 35 100 50 50 20 45 25 25 25 Unit Max ns ns ns ns ns ns ns ns ns ns ns ns ns f Generic Testing For detailed information on JTAG operation in FLEX 8000 devices, refer to Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Each FLEX 8000 device is functionally tested and specified by Altera. Complete testing of each configurable SRAM bit and all logic functionality ensures 100% configuration yield. AC test measurements for FLEX 8000 devices are made under conditions equivalent to those shown in Figure 15. Designers can use multiple test patterns to configure devices during all stages of the production flow. 26 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 15. FLEX 8000 AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast-groundcurrent transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in parentheses are for 3.3-V devices or outputs. Numbers without parentheses are for 5.0-V devices or outputs. VCC 464 Ω (703 Ω) Device Output To Test System 250 Ω (8.06 KΩ) Device input rise and fall times < 3 ns C1 (includes JIG capacitance) Operating Conditions Tables 9 through 12 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 5.0-V FLEX 8000 devices. Note (1) Min –2.0 –2.0 –25 No bias Under bias Ceramic packages, under bias PQFP and RQFP, under bias –65 –65 3 FLEX 8000 Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings Symbol V CC VI I OUT T STG T AMB TJ Parameter Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature Conditions With respect to ground (2) Max 7.0 7.0 25 150 135 150 135 Unit V V mA °C °C °C °C Altera Corporation 27 FLEX 8000 Programmable Logic Device Family Data Sheet Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions Symbol Parameter Conditions Min 4.75 (4.50) 4.75 (4.50) 3.00 (3.00) –0.5 0 For commercial use For industrial use tR tF Input rise time Input fall time 0 –40 Max 5.25 (5.50) 5.25 (5.50) 3.60 (3.60) V CCINT + 0.5 V CCIO 70 85 40 40 Unit V V V V V °C °C ns ns V CCINT Supply voltage for internal logic (3), (4) and input buffers V CCIO Supply voltage for output buffers, 5.0-V operation Supply voltage for output buffers, 3.3-V operation VI VO TA Input voltage Output voltage Operating temperature (3), (4) (3), (4) Table 11. FLEX 8000 5.0-V Device DC Operating Conditions Symbol V IH V IL V OH Notes (5), (6) Min 2.0 –0.5 Parameter High-level input voltage Low-level input voltage 5.0-V high-level TTL output voltage 3.3-V high-level TTL output voltage Conditions Typ Max V CCINT + 0.5 0.8 Unit V V V V V I OH = –4 mA DC (7) V CCIO = 4.75 V I OH = –4 mA DC (7) V CCIO = 3.00 V 2.4 2.4 VCCIO – 0.2 0.45 0.45 0.2 –10 –40 0.5 10 40 10 3.3-V high-level CMOS output I OH = –0.1 mA DC (7) V CCIO = 3.00 V voltage V OL 5.0-V low-level TTL output voltage 3.3-V low-level TTL output voltage I OL = 12 mA DC (7) V CCIO = 4.75 V I OL = 12 mA DC (7) V CCIO = 3.00 V V V V µA µA mA 3.3-V low-level CMOS output I OL = 0.1 mA DC (7) V CCIO = 3.00 V voltage II I OZ I CC0 Input leakage current Tri-state output off-state current V I = V CC or ground V O = V CC or ground V CC supply current (standby) V I = ground, no load 28 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 12. FLEX 8000 5.0-V Device Capacitance Symbol C IN C OUT (1) (2) (3) (4) (5) (6) (7) (8) Note (8) Conditions Min Max 10 10 Parameter Input capacitance Output capacitance Unit pF pF V IN = 0 V, f = 1.0 MHz V OUT = 0 V, f = 1.0 MHz Notes to tables: See the Operating Requirements for Altera Devices Data Sheet. Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns. The maximum V CC rise time is 100 ms. Numbers in parentheses are for industrial-temperature-range devices. Typical values are for T A = 25° C and V CC = 5.0 V. These values are specified in Table 10 on page 28. The I OH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL or CMOS output current. Capacitance is sample-tested only. Tables 13 through 16 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 3.3-V FLEX 8000 devices. Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings Symbol V CC VI I OUT T STG T AMB TJ 3 FLEX 8000 Note (1) Min –2.0 –2.0 –25 Parameter Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias Conditions With respect to ground (2) Max 5.3 5.3 25 150 135 135 Unit V V mA °C °C °C –65 –65 Plastic packages, under bias Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions Symbol V CC VI VO TA tR tF Parameter Supply voltage Input voltage Output voltage Operating temperature Input rise time Input fall time (3) Conditions Min 3.0 –0.3 0 Max 3.6 V CC + 0.3 V CC 70 40 40 Unit V V V °C ns ns For commercial use 0 Altera Corporation 29 FLEX 8000 Programmable Logic Device Family Data Sheet Table 15. FLEX 8000 3.3-V Device DC Operating Conditions Symbol V IH V IL V OH V OL II I OZ I CC0 Note (4) Min 2.0 –0.3 Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current V CC supply current (standby) Conditions Typ Max V CC + 0.3 0.8 0.45 Unit V V V V µA µA mA I OH = –0.1 mA DC (5) I OL = 4 mA DC (5) V I = V CC or ground V I = ground, no load (6) V CC – 0.2 –10 –40 0.3 10 40 10 Tri-state output off-state current V O = V CC or ground Table 16. FLEX 8000 3.3-V Device Capacitance Symbol C IN C OUT (1) (2) (3) (4) (5) (6) (7) Note (7) Conditions Min Max 10 10 Parameter Input capacitance Output capacitance Unit pF pF V IN = 0 V, f = 1.0 MHz V OUT = 0 V, f = 1.0 MHz Notes to tables: See the O perating Requirements for Altera Devices Data Sheet. Minimum DC input voltage is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.3 V for input currents less than 100 mA and periods shorter than 20 ns. The maximum VCC rise time is 100 ms. VCC must rise monotonically. These values are specified in Table 14 on page 29. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current. Typical values are for TA = 25° C and VCC = 3.3 V. Capacitance is sample-tested only. Figure 16 shows the typical output drive characteristics of 5.0-V FLEX 8000 devices. The output driver is compliant with PCI Local Bus Specification, Revision 2.2. 30 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 16. Output Drive Characteristics of 5.0-V FLEX 8000 Devices (Except EPF8282A) 200 200 150 IOL 15 0 IOL Typical IO Output Current (mA) 100 VCCINT = 5.0 V VCCIO = 5.0 V Room Temperature Typical IO Output Current (mA) 100 VCCINT = 5.0 V VCCIO = 3.3 V Room Temperature 50 IOH IOH 50 1 2 3 4 5 1 2 3 4 Output Voltage (V) Output Voltage (V) Figure 17 shows the typical output drive characteristics of 5.0-V EPF8282A devices. The output driver is compliant with PCI Local Bus Specification, Revision 2.2. Figure 17. Output Drive Characteristics of EPF8282A Devices with 5.0-V V CCIO 150 3 FLEX 8000 IOL 120 Typical IO 90 Output Current (mA) 60 VCC = 5.0 V Room Temperature IOH 30 1 2 3 4 5 Output Voltage (V) Figure 18 shows the typical output drive characteristics of EPF8282AV devices. Altera Corporation 31 FLEX 8000 Programmable Logic Device Family Data Sheet Figure 18. Output Drive Characteristics of EPF8282AV Devices 100 75 IOL Typical IO Output 50 Current (mA) VCC = 3.3 V Room Temperature IOH 25 1 2 3 4 Output Voltage (V) Timing Model The continuous, high-performance FastTrack Interconnect routing structure ensures predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and hence have unpredictable performance. Timing simulation and delay prediction are available with the MAX+PLUS II Simulator and Timing Analyzer, or with industry-standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and postsynthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point-to-point timing delay information, setup and hold time prediction, and device-wide performance analysis. Tables 17 through 20 describe the FLEX 8000 timing parameters and their symbols. 32 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 17. FLEX 8000 Internal Timing Parameters Symbol t IOD t IOC t IOE t IOCO t IOCOMB t IOSU t IOH t IOCLR t IN t OD1 t OD2 t OD3 t XZ t ZX1 t ZX2 t ZX3 IOE register data delay IOE register control signal delay Output enable delay IOE register clock-to-output delay IOE combinatorial delay Note (1) Parameter IOE register setup time before clock; IOE register recovery time after asynchronous clear IOE register hold time after clock IOE register clear delay Input pad and buffer delay Output buffer and pad delay, slow slew rate = off, V CCIO = 5.0 V C1 = 35 pF (2) Output buffer and pad delay, slow slew rate = off, V CCIO = 3.3 V C1 = 35 pF (2) Output buffer and pad delay, slow slew rate = on, C1 = 35 pF (3) Output buffer disable delay, C1 = 5 pF Output buffer enable delay, slow slew rate = off, V CCIO = 5.0 V, C1 = 35 pF (2) Output buffer enable delay, slow slew rate = off, V CCIO = 3.3 V, C1 = 35 pF (2) Output buffer enable delay, slow slew rate = on, C1 = 35 pF (3) 3 FLEX 8000 Table 18. FLEX 8000 LE Timing Parameters Symbol t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR tC t CH t CL t CO t COMB t SU tH t PRE t CLR LUT delay for data-in LUT delay for carry-in LUT delay for LE register feedback Cascade gate delay Cascade chain routing delay Carry-in to carry-out delay Data-in to carry-out delay Note (1) Parameter LE register feedback to carry-out delay LE register control signal delay LE register clock high time LE register clock low time LE register clock-to-output delay Combinatorial delay LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or load LE register hold time after clock LE register preset delay LE register clear delay 33 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 19. FLEX 8000 Interconnect Timing Parameters Symbol t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Note (1) Parameter Cascade delay between LEs in different LABs Carry delay between LEs in different LABs LAB local interconnect delay Row interconnect routing delay (4) Column interconnect routing delay Dedicated input to LE control delay Dedicated input to LE data delay (4) Dedicated input to IOE control delay Table 20. FLEX 8000 External Reference Timing Characteristics Symbol t DRR tODH Notes to tables: (1) Note (5) Parameter Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local interconnects (6) Output data hold time after clock (7) (2) (3) (4) (5) (6) (7) Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and external parameters specified by Altera. Internal timing parameters should be used for estimating device performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. These values are specified in Table 10 on page 28 or Table 14 on page 29. For the tOD3 and tZX3 parameters, VCCIO = 3.3 V or 5.0 V. The t ROW and t DIN_D delays are worst-case values for typical applications. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. External reference timing characteristics are factory-tested, worst-case values specified by Altera. A representative subset of signal paths is tested to approximate typical device applications. For more information on test conditions, see Application Note 76 (Understanding FLEX 8000 Timing). This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies to global and non-global clocking, and for LE and I/O element registers. The FLEX 8000 timing model shows the delays for various paths and functions in the circuit. See Figure 19. This model contains three distinct parts: the LE; the IOE; and the interconnect, including the row and column FastTrack Interconnect, LAB local interconnect, and carry and cascade interconnect paths. Each parameter shown in Figure 19 is expressed as a worst-case value in Tables 22 through 49. Hand-calculations that use the FLEX 8000 timing model and these timing parameters can be used to estimate FLEX 8000 device performance. Timing simulation or timing analysis after compilation is required to determine the final worst-case performance. Table 21 summarizes the interconnect paths shown in Figure 19. f 34 For more information on timing parameters, go to Application Note 76 (Understanding FLEX 8000 Timing). Altera Corporation Figure 19. FLEX 8000 Timing Model FLEX 8000 Altera Corporation tLOCAL tROW Carry-In from Previous LE Cascade-In from Previous LE LE LUT Delay Cascade Gate Delay Register Delays Output Data Delay I/O Register Delays Output Delays IOE tLUT tRLUT tCLUT Carry Chain Delay tCGEN tGATE tCO tCOMB tSU tH tPRE tCLR LE-Out tIOD tCOL I/O Register Control tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 I/O Pin tCGENR tCICO tIOE Input Delay FLEX 8000 Programmable Logic Device Family Data Sheet Register Control tC tCASC Cascade Routing Delay Data-In tIN Dedicated Input Delays tDIN_D tLABCARRY tLABCASC tDIN_C tDIN_IO Carry-Out to Next LE in Same LAB Carry-Out to Next LE in Next LAB Cascade-Out Cascade-Out to Next LE in to Next LE in Same LAB Next LAB 35 3 FLEX 8000 Programmable Logic Device Family Data Sheet Table 21. FLEX 8000 Timing Model Interconnect Paths Source LE-Out LE-Out LE-Out LE-Out LE-Out IOE on row IOE on column Destination LE in same LAB LE in same row, different LAB LE in different row IOE on column IOE on row LE in same row Any LE Total Delay t LOCAL t ROW + t LOCAL t COL + t ROW + t LOCAL t COL t ROW t ROW + t LOCAL t COL + t ROW + t LOCAL Tables 22 through 49 show the FLEX 8000 internal and external timing parameters. Table 22. EPF8282A Internal I/O Element Timing Parameters Symbol A-2 Min t IOD t IOC t IOE tIOCO t IOCOMB t IOSU t IOH t IOCLR t IN t OD1 t OD2 t OD3 t XZ t ZX1 t ZX2 t ZX3 1.4 0.0 1.2 1.5 1.1 – 4.6 1.4 1.4 – 4.9 Speed Grade A-3 Max 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.6 1.4 – 4.9 1.6 1.6 – 5.1 Unit A-4 Min Max 0.8 1.8 1.8 1.0 0.2 Min Max 0.9 1.9 1.9 1.0 0.1 ns ns ns ns ns ns ns 1.2 1.7 1.7 – 5.2 1.8 1.8 – 5.3 ns ns ns ns ns ns ns ns ns 1.8 0.0 36 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 23. EPF8282A Interconnect Timing Parameters Symbol A-2 Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Speed Grade A-3 Max 0.3 0.3 0.5 4.2 2.5 5.0 7.2 5.0 Unit A-4 Min Max 0.3 0.3 0.6 4.2 2.5 5.0 7.2 5.0 Min Max 0.4 0.4 0.8 4.2 2.5 5.5 7.2 5.5 ns ns ns ns ns ns ns ns 3 FLEX 8000 Altera Corporation 37 FLEX 8000 Programmable Logic Device Family Data Sheet Table 24. EPF8282A LE Timing Parameters Symbol A-2 Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR tC t CH t CL t CO t COMB t SU tH t PRE t CLR 0.8 0.9 0.6 0.6 4.0 4.0 0.4 0.4 1.1 1.1 0.7 0.7 Speed Grade A-3 Max 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.5 0.5 1.2 1.5 0.8 0.8 Unit A-4 Min Max 2.5 0.0 1.1 0.0 0.7 0.5 0.5 1.1 2.0 Min Max 3.2 0.0 1.5 0.0 0.9 0.6 0.7 1.5 2.5 ns ns ns ns ns ns ns ns ns ns ns 0.6 0.6 ns ns ns ns ns ns 4.0 4.0 Table 25. EPF8282A External Timing Parameters Symbol A-2 Min t DRR t ODH 1.0 Speed Grade A-3 Max 15.8 1.0 Unit A-4 Min Max 19.8 Min 1.0 Max 24.8 ns ns 38 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 26. EPF8282AV I/O Element Timing Parameters Symbol A-3 Min tIOD tIOC tIOE tIOCO tIOCOMB tIOSU tIOH tIOCLR tIN tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 1.8 0.0 1.2 1.7 1.7 – 5.2 1.8 1.8 – 5.3 Speed Grade A-4 Max 0.9 1.9 1.9 1.0 0.1 2.8 0.2 2.3 3.4 4.1 – 7.1 4.3 4.3 – 8.3 Unit Min Max 2.2 2.0 2.0 2.0 0.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 FLEX 8000 Table 27. EPF8282AV Interconnect Timing Parameters Symbol A-3 Min tLABCASC tLABCARRY tLOCAL tROW tCOL tDIN_C tDIN_D tDIN_IO Speed Grade A-4 Max 0.4 0.4 0.8 4.2 2.5 5.5 7.2 5.5 Unit Min Max 1.3 0.8 1.5 6.3 3.8 8.0 10.8 9.0 ns ns ns ns ns ns ns ns Altera Corporation 39 FLEX 8000 Programmable Logic Device Family Data Sheet Table 28. EPF8282AV Logic Element Timing Parameters Symbol A-3 Min tLUT tCLUT tRLUT tGATE tCASC tCICO tCGEN tCGENR tC tCH tCL tCO tCOMB tSU tH tPRE tCLR 1.2 1.5 0.8 0.8 4.0 4.0 0.6 0.6 2.4 4.6 1.3 1.3 Speed Grade A-4 Max 3.2 0.0 1.5 0.0 0.9 0.6 0.7 1.5 2.5 6.0 6.0 0.9 0.9 Unit Min Max 7.3 1.4 5.1 0.0 2.8 1.5 2.2 3.7 4.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 29. EPF8282AV External Timing Parameters Symbol A-3 Min tDRR tODH 1.0 Speed Grade A-4 Max 24.8 1.0 Unit Min Max 50.1 ns ns 40 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 30. EPF8452A I/O Element Timing Parameters Symbol A-2 Min t IOD t IOC t IOE t IOCO t IOCOMB t IOSU t IOH t IOCLR t IN t OD1 t OD2 t OD3 t XZ t ZX1 t ZX2 t ZX3 1.4 0.0 1.2 1.5 1.1 – 4.6 1.4 1.4 – 4.9 Speed Grade A-3 Max 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.6 1.4 – 4.9 1.6 1.6 – 5.1 Unit A-4 Min Max 0.8 1.8 1.8 1.0 0.2 Min Max 0.9 1.9 1.9 1.0 0.1 ns ns ns ns ns ns ns 1.2 1.7 1.7 – 5.2 1.8 1.8 – 5.3 ns ns ns ns ns ns ns ns ns 1.8 0.0 3 FLEX 8000 Table 31. EPF8452A Interconnect Timing Parameters Symbol A-2 Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Speed Grade A-3 Max 0.3 0.3 0.5 5.0 3.0 5.0 7.0 5.0 Unit A-4 Min Max 0.4 0.4 0.5 5.0 3.0 5.0 7.0 5.0 Min Max 0.4 0.4 0.7 5.0 3.0 5.5 7.5 5.5 ns ns ns ns ns ns ns ns Altera Corporation 41 FLEX 8000 Programmable Logic Device Family Data Sheet Table 32. EPF8452A LE Timing Parameters Symbol A-2 Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR tC t CH t CL t CO t COMB t SU tH t PRE t CLR 0.8 0.9 0.6 0.6 4.0 4.0 0.4 0.4 1.0 1.1 0.7 0.7 Speed Grade A-3 Max 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.5 0.5 1.1 1.4 0.8 0.8 Unit A-4 Min Max 2.3 0.2 1.6 0.0 0.7 0.5 0.9 1.4 1.8 Min Max 3.0 0.1 1.6 0.0 0.9 0.6 0.8 1.5 2.4 ns ns ns ns ns ns ns ns ns ns ns 0.6 0.6 ns ns ns ns ns ns 4.0 4.0 Table 33. EPF8452A External Timing Parameters Symbol A-2 Min t DRR tODH 1.0 Speed Grade A-3 Max 16.0 1.0 Unit A-4 Min Max 20.0 Min 1.0 Max 25.0 ns ns 42 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 34. EPF8636A I/O Element Timing Parameters Symbol A-2 Min t IOD t IOC t IOE t IOCO t IOCOMB t IOSU t IOH t IOCLR t IN t OD1 t OD2 t OD3 t XZ t ZX1 t ZX2 t ZX3 1.4 0.0 1.2 1.5 1.1 1.6 4.6 1.4 1.4 1.9 4.9 Speed Grade A-3 Max 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.6 1.4 1.9 4.9 1.6 1.6 2.1 5.1 Unit A-4 Min Max 0.8 1.8 1.8 1.0 0.2 Min Max 0.9 1.9 1.9 1.0 0.1 ns ns ns ns ns ns ns 1.2 1.7 1.7 2.2 5.2 1.8 1.8 2.3 5.3 ns ns ns ns ns ns ns ns ns 1.8 0.0 3 FLEX 8000 Table 35. EPF8636A Interconnect Timing Parameters Symbol A-2 Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Speed Grade A-3 Max 0.3 0.3 0.5 5.0 3.0 5.0 7.0 5.0 Unit A-4 Min Max 0.4 0.4 0.5 5.0 3.0 5.0 7.0 5.0 Min Max 0.4 0.4 0.7 5.0 3.0 5.5 7.5 5.5 ns ns ns ns ns ns ns ns Altera Corporation 43 FLEX 8000 Programmable Logic Device Family Data Sheet Table 36. EPF8636A LE Timing Parameters Symbol A-2 Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR tC t CH t CL t CO t COMB t SU tH t PRE t CLR 0.8 0.9 0.6 0.6 4.0 4.0 0.4 0.4 1.0 1.1 0.7 0.7 Speed Grade A-3 Max 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.5 0.5 1.1 1.4 0.8 0.8 Unit A-4 Min Max 2.3 0.2 1.6 0.0 0.7 0.5 0.9 1.4 1.8 Min Max 3.0 0.1 1.6 0.0 0.9 0.6 0.8 1.5 2.4 ns ns ns ns ns ns ns ns ns ns ns 0.6 0.6 ns ns ns ns ns ns 4.0 4.0 Table 37. EPF8636A External Timing Parameters Symbol A-2 Min t DRR tODH 1.0 Speed Grade A-3 Max 16.0 1.0 Unit A-4 Max 20.0 1.0 Min Min Max 25.0 ns ns 44 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 38. EPF8820A I/O Element Timing Parameters Symbol A-2 Min t IOD t IOC t IOE t IOCO t IOCOMB t IOSU t IOH t IOCLR t IN t OD1 t OD2 t OD3 t XZ t ZX1 t ZX2 t ZX3 1.4 0.0 1.2 1.5 1.1 1.6 4.6 1.4 1.4 1.9 4.9 Speed Grade A-3 Max 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.6 1.4 1.9 4.9 1.6 1.6 2.1 5.1 Unit A-4 Min Max 0.8 1.8 1.8 1.0 0.2 Min Max 0.9 1.9 1.9 1.0 0.1 ns ns ns ns ns ns ns 1.2 1.7 1.7 2.2 5.2 1.8 1.8 2.3 5.3 ns ns ns ns ns ns ns ns ns 1.8 0.0 3 FLEX 8000 Table 39. EPF8820A Interconnect Timing Parameters Symbol A-2 Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Speed Grade A-3 Max 0.3 0.3 0.5 5.0 3.0 5.0 7.0 5.0 Unit A-4 Min Max 0.3 0.3 0.6 5.0 3.0 5.0 7.0 5.0 Min Max 0.4 0.4 0.8 5.0 3.0 5.5 7.5 5.5 ns ns ns ns ns ns ns ns Altera Corporation 45 FLEX 8000 Programmable Logic Device Family Data Sheet Table 40. EPF8820A LE Timing Parameters Symbol A-2 Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR tC t CH t CL t CO t COMB t SU tH t PRE t CLR 0.8 0.9 0.6 0.6 4.0 4.0 0.4 0.4 1.1 1.1 0.7 0.7 Speed Grade A-3 Max 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.5 0.5 1.2 1.5 0.8 0.8 Unit A-4 Min Max 2.5 0.0 1.1 0.0 0.7 0.5 0.5 1.1 2.0 Min Max 3.2 0.0 1.5 0.0 0.9 0.6 0.7 1.5 2.5 ns ns ns ns ns ns ns ns ns ns ns 0.6 0.6 ns ns ns ns ns ns 4.0 4.0 Table 41. EPF8820A External Timing Parameters Symbol A-2 Min t DRR tODH 1.0 Speed Grade A-3 Max 16.0 1.0 Unit A-4 Min Max 20.0 Min 1.0 Max 25.0 ns ns 46 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 42. EPF81188A I/O Element Timing Parameters Symbol A-2 Min t IOD t IOC t IOE t IOCO t IOCOMB t IOSU t IOH t IOCLR t IN t OD1 t OD2 t OD3 t XZ t ZX1 t ZX2 t ZX3 1.4 0.0 1.2 1.5 1.1 1.6 4.6 1.4 1.4 1.9 4.9 Speed Grade A-3 Max 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.6 1.4 1.9 4.9 1.6 1.6 2.1 5.1 Unit A-4 Min Max 0.8 1.8 1.8 1.0 0.2 Min Max 0.9 1.9 1.9 1.0 0.1 ns ns ns ns ns ns ns 1.2 1.7 1.7 2.2 5.2 1.8 1.8 2.3 5.3 ns ns ns ns ns ns ns ns ns 1.8 0.0 3 FLEX 8000 Table 43. EPF81188A Interconnect Timing Parameters Symbol A-2 Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Speed Grade A-3 Max 0.3 0.3 0.5 5.0 3.0 5.0 7.0 5.0 Unit A-4 Min Max 0.3 0.3 0.6 5.0 3.0 5.0 7.0 5.0 Min Max 0.4 0.4 0.8 5.0 3.0 5.5 7.5 5.5 ns ns ns ns ns ns ns ns Altera Corporation 47 FLEX 8000 Programmable Logic Device Family Data Sheet Table 44. EPF81188A LE Timing Parameters Symbol A-2 Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR tC t CH t CL t CO t COMB t SU tH t PRE t CLR 0.8 0.9 0.6 0.6 4.0 4.0 0.4 0.4 1.1 1.1 0.7 0.7 Speed Grade A-3 Max 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.5 0.5 1.2 1.5 0.8 0.8 Unit A-4 Min Max 2.5 0.0 1.1 0.0 0.7 0.5 0.5 1.1 2.0 Min Max 3.2 0.0 1.5 0.0 0.9 0.6 0.7 1.5 2.5 ns ns ns ns ns ns ns ns ns ns ns 0.6 0.6 ns ns ns ns ns ns 4.0 4.0 Table 45. EPF81188A External Timing Parameters Symbol A-2 Min t DRR t ODH 1.0 Speed Grade A-3 Max 16.0 1.0 Unit A-4 Min Max 20.0 Min 1.0 Max 25.0 ns ns 48 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 46. EPF81500A I/O Element Timing Parameters Symbol A-2 Min t IOD t IOC t IOE t IOCO t IOCOMB t IOSU t IOH t IOCLR t IN t OD1 t OD2 t OD3 t XZ t ZX1 t ZX2 t ZX3 1.4 0.0 1.2 1.5 1.1 1.6 4.6 1.4 1.4 1.9 4.9 Speed Grade A-3 Max 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.6 1.4 1.9 4.9 1.6 1.6 2.1 5.1 Unit A-4 Min Max 0.8 1.8 1.8 1.0 0.2 Min Max 0.9 1.9 1.9 1.0 0.1 ns ns ns ns ns ns ns 1.2 1.7 1.7 2.2 5.2 1.8 1.8 2.3 5.3 ns ns ns ns ns ns ns ns ns 1.8 0.0 3 FLEX 8000 Table 47. EPF81500A Interconnect Timing Parameters Symbol A-2 Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Speed Grade A-3 Max 0.3 0.3 0.5 6.2 3.0 5.0 8.2 5.0 Unit A-4 Min Max 0.3 0.3 0.6 6.2 3.0 5.0 8.2 5.0 Min Max 0.4 0.4 0.8 6.2 3.0 5.5 8.7 5.5 ns ns ns ns ns ns ns ns Altera Corporation 49 FLEX 8000 Programmable Logic Device Family Data Sheet Table 48. EPF81500A LE Timing Parameters Symbol A-2 Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR tC t CH t CL t CO t COMB t SU tH t PRE t CLR 0.8 0.9 0.6 0.6 4.0 4.0 0.4 0.4 1.1 1.1 0.7 0.7 Speed Grade A-3 Max 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.5 0.5 1.2 1.5 0.8 0.8 Unit A-4 Min Max 2.5 0.0 1.1 0.0 0.7 0.5 0.5 1.1 2.0 Min Max 3.2 0.0 1.5 0.0 0.9 0.6 0.7 1.5 2.5 ns ns ns ns ns ns ns ns ns ns ns 0.6 0.6 ns ns ns ns ns ns 4.0 4.0 Table 49. EPF81500A External Timing Parameters Symbol A-2 Min t DRR t ODH 1.0 Speed Grade A-3 Max 16.1 1.0 Unit A-4 Min Max 20.1 Min 1.0 Max 25.1 ns ns 50 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Power Consumption The supply power (P) for FLEX 8000 devices can be calculated with the following equation: P = PINT + PIO = [(I CCSTANDBY + I CCACTIVE) × VCC] + PIO Typical I CCSTANDBY values are shown as I CC0 in Table 11 on page 28 and Table 15 on page 30. The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The ICCACTIVE value depends on the switching frequency and the application logic. This value can be calculated based on the amount of current that each LE typically consumes. The following equation shows the general formula for calculating ICCACTIVE: µA ICC AC TIVE = K × f MAX × N × togLC × --------------------------MHz × LE The parameters in this equation are shown below: fMAX N togLC K = = = = Maximum operating frequency in MHz Total number of logic cells used in the device Average percentage of logic cells toggling at each clock Constant, shown in Table 50 3 FLEX 8000 Table 50. Values for Constant K Device 5.0-V FLEX 8000 devices 3.3-V FLEX 8000 devices K 75 60 This calculation provides an I CC estimate based on typical conditions with no output load. The actual I CC value should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Figure 20 shows the relationship between I CC and operating frequency for several LE utilization values. Altera Corporation 51 FLEX 8000 Programmable Logic Device Family Data Sheet Figure 20. FLEX 8000 I CCACTIVE vs. Operating Frequency 5.0-V FLEX 8000 Devices 1,000 1,500 LEs 800 600 ICC Supply Current (mA) 400 1,000 LEs 500 LEs 200 0 30 60 Frequency (MHz) 3.3-V FLEX 8000 Devices 100 90 80 70 60 150 LEs 200 LEs ICC Supply Current (mA) 50 40 30 100 LEs 50 LEs 20 10 0 30 60 Frequency (MHz) Configuration & Operation f 52 The FLEX 8000 architecture supports several configuration schemes to load a design into the device(s) on the circuit board. This section summarizes the device operating modes and available device configuration schemes. For more information, go to Application Note 33 (Configuring FLEX 8000 Devices) and Application Note 38 (Configuring Multiple FLEX 8000 Devices). Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Operating Modes The FLEX 8000 architecture uses SRAM elements that require configuration data to be loaded whenever the device powers up and begins operation. The process of physically loading the SRAM programming data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. The configuration and initialization processes together are called command mode; normal device operation is called user mode. SRAM elements allow FLEX 8000 devices to be reconfigured in-circuit with new programming data that is loaded into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different programming data, reinitializing the device, and resuming user-mode operation. The entire reconfiguration process requires less than 100 ms and can be used to dynamically reconfigure an entire system. In-field upgrades can be performed by distributing new configuration files. 3 FLEX 8000 Configuration Schemes The configuration data for a FLEX 8000 device can be loaded with one of six configuration schemes, chosen on the basis of the target application. Both active and passive schemes are available. In the active configuration schemes, the FLEX 8000 device functions as the controller, directing the loading operation, controlling external configuration devices, and completing the loading process. The clock source for all active configuration schemes is an oscillator on the FLEX 8000 device that operates between 2 MHz and 6 MHz. In the passive configuration schemes, an external controller guides the FLEX 8000 device. Table 51 shows the data source for each of the six configuration schemes. Table 51. Data Source for Configuration Configuration Scheme Active serial Active parallel up Active parallel down Passive serial Passive parallel synchronous Passive parallel asynchronous Acronym AS APU APD PS PPS PPA Data Source Altera configuration device Parallel configuration device Parallel configuration device Serial data path Intelligent host Intelligent host Altera Corporation 53 FLEX 8000 Programmable Logic Device Family Data Sheet Device Pin-Outs Tables 52 through 54 show the pin names and numbers for the dedicated pins in each FLEX 8000 device package. Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 1 of 3) Pin Name 84-Pin PLCC EPF8282A 75 74 53 32 33 10 11 30 48 49 29 28 77 50 51 36 56 57 58 60 61 62 63 64 65 66 67 69 70 71 76 84-Pin PLCC EPF8452A EPF8636A 75 74 53 32 33 10 11 30 48 49 29 28 77 50 51 55 56 57 58 60 61 62 63 64 65 66 67 69 70 71 72 100-Pin 100-Pin TQFP TQFP EPF8282A EPF8452A EPF8282AV 75 74 51 24 25 100 1 22 42 45 21 19 77 47 49 28 55 57 58 59 60 61 62 64 65 66 67 68 69 71 76 76 75 51 25 26 100 1 23 45 46 22 21 78 47 48 54 55 57 58 60 61 62 64 65 66 67 68 70 71 72 73 144-Pin TQFP EPF8820A 110 109 72 37 38 143 144 33 31 12 4 3 20 13 75 76 77 78 79 83 85 87 89 92 94 95 97 102 103 104 105 160-Pin PGA EPF8452A R1 P2 A1 C13 A15 P14 N13 F13 C6 B5 D15 E15 P3 C5 B4 E2 D1 E1 F3 F2 F1 G2 G1 H1 H2 J1 J2 K2 K1 K3 M1 160-Pin PQFP EPF8820A (1) 1 2 44 82 81 125 124 87 89 110 118 121 100 107 40 39 38 37 36 32 30 28 26 22 20 18 16 11 10 8 7 nSP (2) MSEL0 (2) MSEL1 (2) nSTATUS (2) nCONFIG (2) DCLK (2) CONF_DONE (2) nWS nRS RDCLK nCS CS RDYnBUSY CLKUSR ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 54 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 2 of 3) Pin Name 84-Pin PLCC EPF8282A 78 3 4 6 7 8 9 13 14 79 55 27 72 20 52 12, 31, 54, 73 17, 38, 59, 80 84-Pin PLCC EPF8452A EPF8636A 76 2 4 6 7 8 9 13 14 78 45 (5) 27 (5) 44 (5) 43 (5) 52 (8) 12, 31, 54, 73 17, 38, 59, 80 100-Pin 100-Pin TQFP TQFP EPF8282A EPF8452A EPF8282AV 78 90 91 92 95 97 99 4 5 79 54 18 72 11 50 77 89 91 95 96 97 98 4 5 79 – – – – – 144-Pin TQFP EPF8820A 106 131 132 133 134 135 137 138 140 23 96 18 88 86 71 9, 26, 82, 99 8, 28, 70, 90, 111 160-Pin PGA EPF8452A N3 P8 P10 R12 R13 P13 R14 N15 K13 P4 – – – – – C3, D14, N2, R15 160-Pin PQFP EPF8820A (1) 6 140 139 138 136 135 133 132 129 97 17 102 27 29 45 14, 33, 94, 113 ADD0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 SDOUT (3) TDI (4) TDO (4) TCK (4), (6) TMS (4) TRST (7) Dedicated Inputs (10) VCCINT 3 FLEX 8000 3, 23, 53, 73 3, 24, 53, 74 6, 20, 37, 56, 9, 32, 49, 70, 87 59, 82 B2, C4, D3, 3, 24, 46, D8, D12, 92, 114, G3, G12, 160 H4, H13, J3, J12, M4, M7, M9, M13, N12 – 23, 47, 57, 69, 79, 104, 127, 137, 149, 159 VCCIO – – – – 16, 40, 60, 69, 91, 112, 122, 141 Altera Corporation 55 FLEX 8000 Programmable Logic Device Family Data Sheet Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 3 of 3) Pin Name 84-Pin PLCC EPF8282A 84-Pin PLCC EPF8452A EPF8636A 100-Pin 100-Pin TQFP TQFP EPF8282A EPF8452A EPF8282AV 2, 13, 30, 44, 19, 44, 69, 52, 63, 80, 94 94 144-Pin TQFP EPF8820A 7, 17, 27, 39, 54, 80, 81, 100,101, 128, 142 160-Pin PGA EPF8452A C12, D4, D7, D9, D13, G4, G13, H3, H12, J4, J13, L1, M3, M8, M12, M15, N4 – 160-Pin PQFP EPF8820A (1) 12, 13, 34, 35, 51, 63, 75, 80, 83, 93, 103, 115, 126, 131, 143, 155 GND 5, 26, 47, 68 5, 26, 47, 68 No Connect (N.C.) – – – 2, 6, 13, 30, – 37, 42, 43, 50, 52, 56, 63, 80, 87, 92, 93, 99 64 108 – Total User I/O Pins (9) 64 64 74 116 116 56 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 53. FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2) Pin Name 160-Pin PQFP EPF8452A 120 117 84 1 3 38 83 81 120 118 89 50 48 91 93 155 44 43 33 31 29 27 24 23 22 21 20 19 18 17 13 11 9 7 157 137 132 129 160-Pin PQFP EPF8636A 192-Pin PGA 208-Pin 208-Pin 208-Pin EPF8636A PQFP PQFP PQFP EPF8820A EPF8636A (1) EPF8820A (1) EPF81188A (1) R15 T15 T3 B3 C3 C15 B15 C5 B5 C11 B13 A16 A8 A10 R5 U3 T5 U4 R6 T6 R7 T7 T8 U9 U10 U11 U12 R12 U14 U15 R13 U16 H17 G17 F17 207 4 49 108 103 158 153 114 66 64 116 118 201 59 57 43 41 39 37 31 30 29 28 24 23 22 21 14 12 10 8 203 178 172 169 207 4 49 108 103 158 153 114 116 137 145 148 127 134 43 42 41 40 39 35 33 31 29 25 23 21 19 14 13 11 10 9 178 176 174 5 21 33 124 107 154 138 118 121 137 142 144 128 134 46 45 44 39 37 36 31 30 29 26 25 24 18 17 16 10 9 8 177 175 172 57 nSP (2) MSEL0 (2) MSEL1 (2) nSTATUS (2) 37 nCONFIG (2) 40 DCLK (2) CONF_DONE (2) nWS nRS RDCLK nCS CS RDYnBUSY CLKUSR ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 DATA7 DATA6 DATA5 1 4 30 71 73 29 27 125 76 78 91 92 94 95 96 97 98 99 101 102 103 104 105 106 109 110 123 144 150 152 3 FLEX 8000 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 53. FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2) Pin Name 160-Pin PQFP EPF8452A 154 157 159 11 12 128 – – – – – 5, 36, 85, 116 160-Pin PQFP EPF8636A 127 124 122 115 113 152 55 95 57 59 40 192-Pin PGA 208-Pin 208-Pin 208-Pin EPF8636A PQFP PQFP PQFP EPF8820A EPF8636A (1) EPF8820A (1) EPF81188A (1) E17 G15 F15 E16 C16 C7 (11) R11 B9 U8 U7 R3 165 162 160 149 147 198 72 120 74 76 54 7, 45, 112, 150 5, 6, 33, 110, 137 172 171 167 165 162 124 20 129 30 32 54 17, 36, 121, 140 5, 6, 27, 48, 119, 141 170 168 166 163 161 119 – – – – – 13, 41, 116, 146 4, 20, 35, 48, 50, 102, 114, 131, 147 DATA4 DATA3 DATA2 DATA1 DATA0 SDOUT (3) TDI (4) TDO (4) TCK (4), (6) TMS (4) TRST (7) Dedicated Inputs (10) VCCINT (5.0 V) VCCIO (5.0 V or 3.3 V) GND 6, 35, 87, 116 A5, U5, U13, A13 C8, C9, C10, R8, R9, R10, R14 21, 41, 53, 67, 4, 5, 26, 85, 80, 81, 100, 121, 106 133, 147, 160 – 25, 41, 60, 70, D3, D4, D9, 32, 55, 78, 91, 26, 55, 69, 87, 3, 19, 34, 49, 80, 107, 121, D14, D15, G4, 102, 138, 159, 102, 131, 159, 69, 87, 106, 140, 149, 160 G14, L4, L14, 182, 193, 206 173, 191, 206 123, 140, 156, P4, P9, P14 174, 192 15, 16, 36, 37, 45, 51, 75, 84, 86, 96, 97, 117, 126, 131, 154 C4, D7, D8, D10, D11, H4, H14, K4, K14, P7, P8, P10, P11 19, 20, 46, 47, 60, 67, 96, 109, 111, 124, 125, 151, 164, 171, 200 1, 2, 3, 16, 17, 18, 25, 26, 27, 34, 35, 36, 50, 51, 52, 53, 104, 105, 106, 107, 121, 122, 123, 130, 131, 132, 139, 140, 141, 154, 155, 156, 157, 208 15, 16, 37, 38, 60, 78, 96, 109, 110, 120, 130, 142, 152, 164, 182, 200 1, 2, 3, 50, 51, 52, 53, 104, 105, 106, 107, 154, 155, 156, 157, 208 11, 12, 27, 28, 42, 43, 60, 78, 96, 105, 115, 122, 132, 139, 148, 155, 159, 165, 183, 201 1, 2, 51, 52, 53, 54, 103, 104, 157, 158, 207, 208 13, 14, 28, 46, 60, 75, 93, 107, 108, 126, 140, 155 No Connect (N.C.) 2, 3, 38, 39, 70, 2, 39, 82, 119 C6, C12, C13, 82, 83, 118, 119, C14, E3, E15, 148 F3, J3, J4, J14, J15, N3, N15, P3, P15, R4 (12) Total User I/O Pins (9) 116 114 132, 148 (13) 132 148 144 58 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3) Pin Name 225-Pin BGA EPF8820A A15 B14 R15 P2 R1 B2 A1 L4 K5 F1 D1 C1 J3 G2 M14 L12 M15 L13 L14 K13 K15 J13 J15 G14 G13 G11 F14 E13 D15 D14 E12 C15 A7 D7 A6 232-Pin PGA EPF81188A C14 G15 L15 L3 R4 C4 G3 P1 N1 G2 E2 E3 K2 H2 R15 T17 P15 M14 M15 M16 K15 K17 J14 J15 H17 H15 F16 F15 F14 D15 B17 C15 A7 D8 B7 240-Pin PQFP EPF81188A 237 21 40 141 117 184 160 133 137 158 166 169 146 155 58 56 54 47 45 43 36 34 32 29 27 25 18 16 14 7 5 3 205 203 200 240-Pin PQFP EPF81500A 237 19 38 142 120 183 161 134 138 159 167 170 147 156 56 54 52 45 43 41 34 32 30 27 25 23 16 14 12 5 3 1 199 197 196 280-Pin PGA EPF81500A W1 N1 H3 G19 B18 U18 M16 F18 G18 M17 N16 N18 J17 K19 E3 E2 F4 G1 H2 H1 J3 K3 K4 L1 L2 M1 N2 N3 N4 U1 U2 V1 W13 W14 W15 304-Pin RQFP EPF81500A 304 26 51 178 152 230 204 167 171 202 212 215 183 199 73 71 69 60 58 56 47 45 43 34 32 30 20 18 16 8 6 4 254 252 250 nSP (2) MSEL0 (2) MSEL1 (2) nSTATUS (2) nCONFIG (2) DCLK (2) CONF_DONE (2) nWS nRS RDCLK nCS CS RDYnBUSY CLKUSR ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 DATA7 DATA6 DATA5 3 FLEX 8000 Altera Corporation 59 FLEX 8000 Programmable Logic Device Family Data Sheet Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3) Pin Name 225-Pin BGA EPF8820A A5 B5 E6 D5 C4 K1 F15 (4) J2 (4) J14 (4) J12 (4) P14 232-Pin PGA EPF81188A C7 D7 B5 A3 A2 N2 – – – – – C1, C17, R1, R17 E4, H4, L4, P12, L14, H14, E14, R14, U1 N10, M13, M5, K13, K5, H13, H5, F5, E10, E8, N8, F13 240-Pin PQFP EPF81188A 198 196 194 191 189 135 – – – – – 10, 51, 130, 171 240-Pin PQFP EPF81500A 194 193 190 189 187 136 63 (14) 117 116 (14) 64 (14) 115 (14) 8, 49, 131, 172 280-Pin PGA EPF81500A W16 W17 V16 U16 V17 F19 B1 (14) C17 A19 (14) C2 (14) A18 (14) F1, F16, P3, P19 B17, D3, D15, E8, E10, E12, E14, R7, R9, R11, R13, R14, T14 D14, E7, E9, E11, E13, R6, R8, R10, R12, T13, T15 304-Pin RQFP EPF81500A 248 246 243 241 239 169 80 (14) 149 148 (14) 81 (14) 145 (14) 12, 64, 164, 217 24, 54, 77, 144, 79, 115, 162, 191, 218, 266, 301 22, 53, 78, 99, 119, 137, 163, 193, 220, 244, 262, 282, 300 DATA4 DATA3 DATA2 DATA1 DATA0 SDOUT (3) TDI TDO TCK (6) TMS TRST (7) Dedicated Inputs F4, L1, K12, (10) E15 VCCINT (5.0 V) F5, F10, E1, L2, K4, M12, P15, H13, H14, B15, C13 H3, H2, P6, R6, P10, N10, R14, N13, H15, H12, D12, A14, B10, A10, B6, C6, A2, C3, M4, R2 20, 42, 64, 66, 18, 40, 60, 62, 114, 128, 150, 91, 114, 129, 172, 236 151, 173, 209, 236 19, 41, 65, 81, 99, 116, 140, 162, 186, 202, 220, 235 17, 39, 61, 78, 94, 108, 130, 152, 174, 191, 205, 221, 235 VCCIO (5.0 V or 3.3 V) 60 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3) Pin Name 225-Pin BGA EPF8820A B1, D4, E14, F7, F8, F9, F12, G6, G7, G8, G9, G10, H1, H4, H5, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, K6, K7, K8, K9, K11, L15, N3, P1 232-Pin PGA EPF81188A A1, D6, E11, E7, E9, G4, G5, G13, G14, J5, J13, K4, K14, L5, L13, N4, N7, N9, N11, N14 240-Pin PQFP EPF81188A 8, 9, 30, 31, 52, 53, 72, 90, 108, 115, 129, 139, 151, 161, 173, 185, 187, 193, 211, 229 240-Pin PQFP EPF81500A 6, 7, 28, 29, 50, 51, 71, 85, 92, 101, 118, 119, 140, 141, 162, 163, 184, 185, 186, 198, 208, 214, 228 280-Pin PGA EPF81500A D4, D5, D16, E4, E5, E6, E15, E16, F5, F15, G5, G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P4, P5, P15, P16, R4, R5, R15, R16, T4, T5, T16, U17 – 304-Pin RQFP EPF81500A 9, 11, 36, 38, 65, 67, 90, 108, 116, 128, 150, 151, 175, 177, 206, 208, 231, 232, 237, 253, 265, 273, 291 GND No Connect (N.C.) – – 61, 62, 119, – 120, 181, 182, 239, 240 10, 21, 23, 25, 35, 37, 39, 40, 41, 42, 52, 55, 66, 68, 146, 147, 161, 173, 174, 176, 187, 188, 189, 190, 192, 194, 195, 205, 207, 219, 221, 233, 234, 235, 236, 302, 303 204 3 FLEX 8000 Total User I/O Pins (9) 148 180 180 177 204 Altera Corporation 61 FLEX 8000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) (3) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74 (Evaluating Power for Altera Devices) for more information. This pin is a dedicated pin and is not available as a user I/O pin. SDOUT will drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the MAX+PLUS II software will not use SDOUT as a user I/O pin; the user can override the MAX+PLUS II software and use SDOUT as a user I/O pin. If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin. JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins. If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration. TRST is a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used. Pin 52 is a V CC pin on EPF8452A devices only. The user I/O pin count includes dedicated input pins and all I/O pins. Unused dedicated inputs should be tied to ground on the board. SDOUT does not exist in the EPF8636GC192 device. These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices. EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins. For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is not used, TDI, TCK, TMS, and TRST should be tied to GND. (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) Revision History The information contained in the FLEX 8000 Programmable Logic Device Family Data Sheet version 11.1 supersedes information published in previous versions. The FLEX 8000 Programmable Logic Device Family Data Sheet version 11.1 contains the following change: minor textual updates. 62 Altera Corporation