S19227

P RODUC T BRIEF 50 92 S1 S19250 STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC Features • Operational from 9.9 Gbps to 11.3 Gbps • Built-In Self Test (BIST) with Error Counter • On-chip High-Frequency PLLs for Clock Recovery and Clock Gen. • 16-bit LVDS Parallel Data Path • TX and RX Lock Detect Indicators • Reference Loop Timing Modes • Line and Diagnostic Loopback Mode for Faulty Node Identification • -40°C to 85°C Industrial Temperature Range • Supports MDIO, I2C and SPI serial interface • Complies with applicable OIF SFI-4 Phase 1, Telcordia/ITU-T, 300-pin MSA, IEEE 802.3ae and XFP MSA Standards • 2000 V ESD rating on low speed pins, 1000 V on high speed I/Os • 17 x 17 mm2, 1.0 mm pitch package with Green / RoHS compliant lead free option. Pin Compatible with S19235/S19237. • 1.1 W typical Description The S19250 MUX/DeMux chip is a fully integrated serialization/de-serialization SONET STS-192/10 GB Ethernet/Fiber Channel transceiver with Electronic Dispersion Compensation (EDC). This device can be used to compensate channel impairments caused by Single Mode Fiber (SMF) and copper medium. The chip performs all necessary parallel-to-serial and serial-to-parallel functions in conformance with SONET/SDH, 10 Gigabit Ethernet (10 GbE) and 10 Gigabit Fibre Channel (10 G FC) transmission standards. The figure below shows a typical network application. The other application block diagrams are shown on page 2. On-chip clock synthesis PLL components are contained in the S19250 chip, allowing the use of a slower external transmit clock reference. The chip can be used with 155.52 MHz or 622.08 MHz (or equivalent FEC/10 GbE/10 G FC rates) reference clocks, in support of existing system clocking schemes. The low-jitter LVDS interface guarantees compliance with the biterror rate requirements of the Telcordia and ITUT standards. and the serial receive interface. The chip includes parallel-to-serial, and serial-to-parallel conversion and system timing. The S19250 is designed to be pin compatible with the S19235/S19237. Therefore, the default serial bus is MDIO. AMCC Suggested Interface Devices GANGES II (S19202CBI20) HUDSON (S19203) STS-192 POS/ATM SONET/SDH Mapper Variable Rate Digital Wrapper Framer/ Deframer, Performance Monitor, and FEC Device OC-192/48/12/3 DW/FEC/PM and ASYNC Mapper Device with Strong FEC STS-192 Pointer Processor STS-192c SONET/SDH Framer/Mapper with Integrated MAC RUBICON (S19227) MEKONG (S19204) KHATANGA (S19205) Transmitter Features • Ref. Freq. of 155.52 or 622.08 MHz (or eq. FEC rate); Common 10 GbE/10 G FC Ref. of 156.25 MHz or 159.375 MHz for 10 G FC; Divide by 16 or 64 of the TX rates • Internal, Self-Initializing FIFO to Decouple Transmit Clocks • Programmable TSD Output Differential Swing • Duo Binary Encoding Receiver Features • LOS/RSSI • ISI compensation. Tolerates additional 350 ps/ nm of chromatic dispersion with an OSNR penalty of 1.0dB over a traditional demux • Tolerates up to 36” of Standard FR-4 Material • Adaptive Post-Amplifier Offset Adjust • Phase Adjust of -0.11 to +0.085 UI • Ref. Freq. of 155.52 MHz or 622.08 MHz (or eq. FEC rate); Common ref. of 156.25 MHz for 10 GbE/10 GFC or 159.375 MHz for 10 GFC; Divide by 16 or 64 of the RX rates • Capability to Interface with Single-Ended or Differential TIAs (Center Tap Option) • Input Sensitivity of 10 mV p-p (one wire or two wire) at 10-12 BER Overview The S19250 transceiver incorporates SONET/ SDH/10 GbE/10 G Fibre Channel serialization and deserialization functions. This chip can be used to implement the front end of SONET/10 GbE/10 G Fibre Channel equipment, which consists primarily of the serial transmit interface Applications • SONET/SDH and 10GbE-Based Transmission Systems & Modules • Section Repeaters • Add Drop Multiplexers (ADM) • Broad-Band Cross-Connects • Fiber Optic Test Equipment 16 AMCC'S KHATANGA, GANGES, HUDSON, MEKONG, or RUBICON Laser Driver AMCC S19250 TIA 16 OTX ORX TIA AMCC S19250 16 ORX OTX Laser Driver 16 AMCC'S KHATANGA, GANGES, HUDSON, MEKONG, or RUBICON System Block Diagram with the S19250 SPECIFIC AT IONS S19250 The sequence of operations is as follows: Transmitter Operations • 16-bit parallel input • Parallel-to-serial conversion • Serial data output Receiver Operations • • • • • • • Serial input to limiting post-amp Inter Symbol Interference (ISI) compensation Threshold adjustment Clock and Data recovery Phase adjustment for improved BER Serial-to-parallel conversion 16-bit parallel data and clock output Enable Adaptive Post-Amplifier Offset Control Compensates up to 24" of FR-4 MDIO 16 ASIC 16 AMCC S19250 M I D P L A N E MDIO AMCC S19250 16 ASIC 16 Enable Adaptive ISI Mitigation Figure 1. Mid-Plane Application Block Diagram Enable Adaptive Post-Amplifier Offset Control Enable Adaptive ISI Mitigation Disable EDC MDIO ASIC OR FRAMER OR FEC 16 16 AMCC S19250 XFP MODULE Compensates up to 24" of FR-4 (Improves BER Performance and extends the reach of the standard XFP Module) Figure 2. XFP Application Block Diagram 6290 Sequence Dr. San Diego, CA 92121 P 858 450 9333 F 858 450 9885 www.amcc.com For technical support, please call 1-800-840-6055 or 858-535-6517, or email support@amcc.com. AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. PowerPC and the PowerPC logo are registered trademarks of IBM Corporation. All other trademarks are the property of their respective holders. Copyright © 2006 Applied Micro Circuits Corporation. All Rights Reserved. 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