S2070

® DEVICE SPECIFICATION FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION S2070 S2070 FEATURES • • • • 1062 Mbps (Fibre Channel) line rates 1250 Mbps (Gigabit Ethernet) line rates Half and full VCO output rates Functionally compliant to IEEE 802.3z Gigabit Ethernet Specification and the ANSI X3T11 Fibre Channel Specification Transmitter incorporating phase-locked loop (PLL) clock synthesis from low speed reference Receiver PLL provides clock and data recovery 10-bit parallel TTL compatible interface Low-jitter serial LVPECL compatible interface Local loopback Single +3.3 V supply, 620 mW power dissipation 64 PQFP package Continuous downstream clocking from receiver Drives 30 m of Twinax cable directly • • • • • • • • • The S2070 transmitter and receiver chip facilitates high speed serial transmission of data over fiber optic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet Specification and the ANSI X3T11 Fibre Channel specification, and runs at 1062 Mbps or 1250 Mbps data rates with an associated 10-bit data word. The chip provides parallel-to-serial and serial-to-parallel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a lowspeed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a +3.3 V power supply and dissipates approximately 620 mW under typical conditions. The S2070 can be used for a variety of applications including Fibre Channel, serial backplanes, and proprietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip. APPLICATIONS • • • • • Workstation Frame buffer Switched networks Data broadcast environments Proprietary extended backplanes Figure 1. System Block Diagram Gigabit Ethernet/ Fibre Channel Controller S2070 Optical Tx Optical Rx Optical Rx S2070 Optical Tx Gigabit Ethernet/ Fibre Channel Controller March 7, 2001 / Revision G 1 S2070 S2070 OVERVIEW FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER Loop Back Local loopback provides a capability for performing off-line testing. This is useful for ensuring the integrity of the serial channel before enabling the transmission medium. It also allows for system diagnostics. 1 A.X. Widmer and P.A. Franaszek, "A Byte Oriented DC Balanced (0,4) 8B/10B Transmission Code," IBM Research Report RC 9391, May 1982. The S2070 transmitter and receiver provide serialization and deserialization functions for block encoded data to implement a Gigabit Ethernet or Fibre Channel interface. The S2070 functional block diagram is depicted in Figure 2. The sequence of operations is as follows: Transmitter 1.10-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver 1. Clock and data recoverery from serial input 2. Serial-to-parallel conversion 3. Frame detection 4. 10-bit parallel output The 10-bit parallel data input to the S2070 should be from a DC-balanced encoding scheme, such as the 8B/10B transmission code, in which information to be transmitted is encoded 8 bits at a time into 10-bit transmission characters1. For reference, Table 1 shows the mapping of the parallel data to the 8B/10B codes. Table 1. Data Mapping to 8B/10B Alphabetic Representation Data Byte TX[0:9] or RX[0:9] 8B/10B Alphabetic Representation 0 a 1 b 2 c 3 d 4 e 5 i 6 f 7 g 8 h 9 j Figure 2. Functional Block Diagram S2070 TX[0:9] 10 FIFO (4 x 10) 10 Shift Register TXP TXN TBC PLL Clock Multiplier w/ lock detect F0 = F1 x 10 RATEN 2:1 D PLL Clock Recovery w/ lock detect Shift Register RXP RXN EWRAP –LCK_REF EN_CDET Control Logic 10 D Q RX[0:9] Comma Detect Logic COM_DET RBC0 RBC1 2 March 7, 2001 / Revision G FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER TRANSMITTER DESCRIPTION The S2070 transmitter accepts 10-bit parallel input data and serializes it for transmission over fiber optic or coaxial cable media. The chip is fully compatible with the IEEE 802.3z Gigabit Ethernet and ANSI X3T11 Fibre Channel standards. The S2070 uses a PLL to generate the serial rate transmit clock. The transmitter runs at 10 times the TBC input clock, and operates in either full rate or half rate mode. S2070 Transmit Byte Clock (TBC) The Transmit Byte Clock (TBC) input must be supplied from a clock source with 100 ppm tolerance to assure that the transmitted data meets the Fibre Channel frequency limits. The internal serial clock is frequency locked to TBC. TBC is input at full or half rate determined by the state of the RATEN input. Operating rates are shown in Table 2. Parallel-to-Serial Conversion The parallel-to-serial converter takes in 10-bit wide data from the input latch and converts it to a serial data stream. Parallel data is latched into the transmitter on the positive going edge of TBC. The data is then clocked into the serial output shift register. The shift register is clocked by the internally generated bit clock which is 10x the TBC input frequency. TX[0] is transmitted first. Transmit Latency The average transmit latency is 4 parallel clocks. Table 2. Operating Rates RATEN 0 0 1 1 Parallel Input Rate (Mbps) 125 106.25 62.5 53.125 TBC Frequency (MHz) 125 106.25 62.5 53.125 Serial Output Rate (Gbps) 1.25 1.0625 0.625 0.53125 March 7, 2001 / Revision G 3 S2070 RECEIVER DESCRIPTION FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER propriately and quickly to a loss of signal. The runlength checker flags a condition of consecutive ones or zeros across 12 parallel words. Thus, 119 or less consecutive ones or zeros does not cause signal loss, 129 or more causes signal loss, and 120 – 128 may or may not, depending on how the data aligns across byte boundaries. If both the off-frequency detect test and the run-length test is satisfied, the CRU will attempt to lock to the incoming data. In any transfer of PLL control between the serial data and the reference clock, the RBC0 and RBC1 remain phase continuous and glitch free, assuring the integrity of downstream clocking. Whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. The S2070 searches the serial bit stream for the occurrence of a positive polarity COMMA sync pattern (0011111xxx positive running disparity) to perform word synchronization. Once synchronization on both bit and word boundaries is achieved, the receiver provides the decoded data on its parallel outputs. Clock Recovery Function Clock recovery is performed on the input data stream. A simple state machine in the clock recovery macro decides whether to acquire lock from the serial data input or from the reference clock. The decision is based upon the frequency and run length of the input serial data. The lock to reference frequency criteria ensure that the S2070 will respond to variations in the serial data input frequency (as compared to the reference frequency). The new lock state is dependent upon the current lock state, as shown in Table 3. The runlength criteria ensure that the S2070 will respond ap- Reference Clock Input The reference clock must be provided from a low jitter clock source. The frequency of the received data stream must be within 200 ppm of the reference clock to ensure reliable locking of the receiver PLL. A single reference clock is provided to both the transmit and receive PLLs. Data Output The S2070 provides either framed or unframed parallel output data, determined by the state of EN_CDET. With EN_CDET held ACTIVE, the S2070 will detect and align to the 8B/10B COMMA codeword anywhere in the data stream. When EN_CDET is INACTIVE, no attempt is made to synchronize on any particular incoming character. Upon change of state of the EN_CDET input, the COM_DET output response will be delayed by a maximum of 3 byte times. The COM_DET output signal is ACTIVE whenever EN_CDET is active and the COMMA control character is present on the RX[0:9] parallel data outputs. The COM_DET output signal will be INACTIVE at all other times. Table 3. Lock to Reference Frequency Criteria Current Lock State PLL Frequency (vs. TBC) < 488 ppm Locked 488 to 732 ppm > 732 ppm < 244 ppm Unlocked 244 to 366 ppm > 366 ppm New Lock State Locked Undetermined Unlocked Locked Undetermined Unlocked 4 March 7, 2001 / Revision G FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER Parallel Output Clock Rate and Data Stretching The S2070 supports both full rate and half rate outputs, selected via the RATEN input. Table 4 shows the operating rate scenarios. When RATEN is INACTIVE, a data clock is provided on RBC1 at the data rate. Data should be clocked on the rising edge of RBC1. When RATEN is ACTIVE the device is in full rate mode, and complementary TTL clocks are provided on the RBC0 and RBC1 outputs at 1/2 the data rate as required by the Fibre Channel standard. Data is clocked on the rising edges of both RBC0 and RBC1. See Figures 9 and 10. S2070 OTHER OPERATING MODES Loopback Mode The S2070 supports internal loopback mode in which the serial data from the transmitter replaces external serial data. The loopback function is enabled when the loopback enable signal, EWRAP, is set ACTIVE. The loopback mode provides the ability to perform system diagnostics and to perform off-line testing of the interface to guarantee the integrity of the serial channel before enabling the transmission medium. Figure 3 shows the basic loopback operation. Table 4. Operating Rates RATEN 0 0 1 1 Serial Input Rate (Gbps) 1.25 1.0625 0.625 0.53125 RBC0 (MHz) 62.5 53.125 N/A N/A RCB1 (MHz) 62.5 53.125 62.5 53.125 Parallel Output Rate (Mbps) 125 106.25 62.5 53.125 Figure 3. Loopback Operation output disabled CSU Fibre Channel and Gigabit Ethernet standards require that the COMMA sync character appears on the rising edge of the RBC1 signal. In full rate mode the phase of the data is adjusted such that this requirement is met. No alignment is necessary when the S2070 is operating in half rate mode (RATEN INACTIVE) since the output clock frequency is equal to the parallel word rate. In Fibre Channel and Gigabit Ethernet applications it is illegal for multiple consecutive COMMA characters to be generated. However, multiple consecutive COMMA characters can occur in serial backplane applications. The S2070 is able to operate properly when multiple consecutive COMMA characters are received: after the first COMMA is detected and aligned, the RBC0/RBC1 clock operates without glitches or loss of cycles. Additionally, COM_DET stays high while multiple COMMAs are being output. CRU Receive Latency The average receive latency is 8 byte times. March 7, 2001 / Revision G 5 S2070 FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER Table 5. Pin Description and Assignment Pin Name TX[9] TX[8] TX[7] TX[6] TX[5] TX[4] TX[3] TX[2] TX[1] TX[0] TBC Level LVTTL I/O I Pin # 13 12 11 9 8 7 6 4 3 2 22 Description Transmit Data. Parallel data on this bus is clocked in on the rising edge of TBC. TX[0] is transmitted first. LVTTL I Transmit Byte Clock. Reference clock input to the PLL clock multiplier. The frequency of TBC is the bit rate divided by 10. When TESTEN is active, TBC replaces the VCO clock to facilitate factory test. TBC should be supplied by a crystal controlled reference since jitter on this line directly translates to jitter on the output data. Rate Select. Active Low. This signal configures the PLL's for the appropriate TBC frequency. When inactive, the device operates in 1/2 rate mode. When active, the device operates in full rate mode. See Tables 2 and 4. Enable Comma Detect. Active High. When active, enables detection of the COMMA sync pattern to set the word frame boundary for the data to follow. When inactive, data is treated as unframed. Enable Wrap. Active High. When active, the transmitter serial data outputs are internally routed to the receiver serial data inputs. TXP/N are static (logic 1) in this state. When inactive, the RXP/N serial inputs are selected (normal operation). (Externally capacitively coupled.) LVPECL Receive Serial Data Inputs. RXP is the positive differential input, RXN is negative. Internally biased to VCC -1.3 V. Lock to Reference Input. Active Low. When inactive or open, the receive PLL will lock to the incoming data (normal operation). When active, the receive PLL is forced to lock to the TBC input. RATEN LVTTL I 14 EN_CDET LVTTL I 24 EWRAP LVTTL I 19 RXP RXN –LCK_REF Diff. LVPECL LVTTL I 54 52 27 I Note: All TTL inputs have internal 15KΩ pull-up networks. 6 March 7, 2001 / Revision G FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER Table 5. Pin Description and Assignment (Continued) Pin Name RX[9] RX[8] RX[7] RX[6] RX[5] RX[4] RX[3] RX[2] RX[1] RX[0] RBC1 RBC0 Level LVTTL I/O O Pin # 34 35 36 38 39 40 41 43 44 45 30 31 Description S2070 Receive Data Outputs. For full rate output, parallel data on this bus is valid on the rising edges of RBC0 and RBC1. RX[0] is the first bit received. LVTTL O Complementary Receive Byte Clocks. In full rate mode, parallel receive data is valid on the rising edges of RBC0 and RBC1 (see Figure 9, timing diagram). For half rate, output data is valid on the rising edge of RBC1. See Table 4. Comma Detect. Active High. When EN_CDET is active, COM_DET indicates that the sync character is present on the parallel bus bits RX[0:9]. Upon detection of the COMMA sync character (0011111xxx positive polarity) this output data is valid on the rising edge of RBC1 and remains active for one RBC1 clock period. When EN_CDET is inactive, COM_DET is held Low (logic 0). Upon change of state of the EN_CDET input, the COM_DET output response will be delayed by a maximum of 3 byte times. Transmit Serial Data. These lines are static (TXN HIGH, TXP HIGH) when EWRAP is active. These lines are static (TXN HIGH, TXP LOW) when TXRST is active. Upon startup, these outputs are held static (TXN HIGH, TXP LOW) until the TXPLL has locked to the reference clock. Each output can drive 150 Ω to ground. COM_DET LVTTL O 47 TXP TXN Diff. LVPECL O 62 61 March 7, 2001 / Revision G 7 S2070 Table 6. Power and Ground Signals FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER Pin Name ECLVCC ECLVEE ECLIOVCC ECLIOVEE TTLVCC TTLGND AVCC AVEE VCC VEE DNC Level +3.3 V GND +3.3 V GND +3.3 V GND +3.3 V GND +3.3 V GND — Pin # 20, 23 Description Core Power Supply 21, 25, 58 Core Ground 55, 60, 63 LVPECL I/O Power Supply 56, 64 37, 42 32, 46 18, 50 15, 5 1 5, 1 0 1, 3 3 48 LVPECL I/O Ground LVTTL Power Supply LVTTL Ground Analog Power Supply Analog Ground Power Ground This pin cannot be tied Low. It should be floated, or tied High. DNC — 16, 17, 26, 28, Not connected 29, 49, 53, 57, 59 8 March 7, 2001 / Revision G FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER Figure 4. S2070 Pinout ECLIOVEE ECLIOVCC TXP TXN ECLIOVCC DNC ECLVEE DNC ECLIOVEE ECLIOVCC RXP DNC RXN AVEE AVCC DNC S2070 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Thermal Management DNC AVCC EWRAP ECLVCC ECLVEE TBC ECLVCC EN_CDET ECLVEE DNC –LCK_REF DNC DNC RBC1 RBC0 TTLGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VEE TX[0] TX[1] TX[2] VCC TX[3] TX[4] TX[5] TX[6] VCC TX[7] TX[8] TX[9] RATEN AVEE DNC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S2070 TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DNC COM_DET TTLGND RX[0] RX[1] RX[2] TTLVCC RX[3] RX[4] RX[5] RX[6] TTLVCC RX[7] RX[8] RX[9] VEE Device S2070A (10mm package) S2070B (14mm package) Package Max Power 1.33 W 1.33 W Θja (Still Air) 45˚ C/W 45˚ C/W Θjc 15˚ C/W 15˚ C/W March 7, 2001 / Revision G 9 S2070 FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER Figure 5. 14mm x 14mm 64 PQFP Package TOP VIEW 10 March 7, 2001 / Revision G FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER Figure 6. 10mm x 10mm 64 PQFP with Heat Spreader Package S2070 TOP VIEW March 7, 2001 / Revision G 11 S2070 FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER Table 7. Power and Ground Application Information Function Pin Names Instructions Connect to low noise or filtered +3.3 V supply through a ferrite bead (600Ω at 100 MHz: Murrata BLM31B601S or equivalent). Provide dual local HF bypassing to AVEE (0.1 µf, 100 pf) for low inductance and resistance. A single low inductance 0.1 µf capacitor can be substituted for the pair (Vishay VJ0612 or equivalent,