AM29LV400BB120FCB

ADVANCE INFORMATION Am29LV400B 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS s Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s Manufactured on 0.35 µm process technology — Compatible with 0.5 µm Am29LV400 device s High performance — Full voltage range: access times as fast as 80 ns — Regulated voltage range: access times as fast as 70 ns s Ultra low power consumption (typical values at 5 MHz) — 200 nA Automatic Sleep mode current — 200 nA standby mode current — 7 mA read current — 15 mA program/erase current s Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences s Top or bottom boot block configurations available s Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 write cycle guarantee per sector s Package option — 48-ball FBGA — 48-pin TSOP — 44-pin SO s Compatibility with JEDEC standards — Pinout and software compatible with singlepower supply Flash — Superior inadvertent write protection s Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion s Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion s Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 21523 Rev: A Amendment/0 Issue Date: January 1998 ADVANCE INFORMATION GENERAL DESCRIPTION The Am29LV400B is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system using only a single 3.0 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMD’s 0.35 µ m process technology, and offers all the features and benefits of the Am29LV400, which was manufactured using 0.5 µ m process technology. In addition, the Am29LV400B features unlock bypass programming and in-system sector protection/unprotection. The standard device offers access times of 70, 80, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the E mbedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the a utomatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 1/29/98 Am29LV400B 2 ADVANCE INFORMATION PRODUCT SELECTOR GUIDE Family Part Number Speed Options Regulated Voltage Range: VCC =3.0–3.6 V Full Voltage Range: VCC = 2.7–3.6 V Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) 70 70 30 70R 80 80 80 30 90 90 90 35 120 120 120 50 Am29LV400B Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM RY/BY# VCC VSS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches DQ0–DQ15 (A-1) WE# BYTE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch CE# OE# STB VCC Detector Timer Address Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A0–A17 21523A-1 3 Am29LV400B ADVANCE INFORMATION CONNECTION DIAGRAMS A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard TSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Reverse TSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 21523A-2 1/29/98 Am29LV400B 4 ADVANCE INFORMATION CONNECTION DIAGRAMS NC RY/BY# A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC SO FBGA Bump Side (Bottom) View A1 A3 A2 A7 A3 RY/BY# A4 WE# A5 A9 A6 A13 B1 A4 B2 A17 B3 NC B4 RESET# B5 A8 B6 A12 C1 A2 C2 A6 C3 NC C4 NC C5 A10 C6 A14 D1 A1 D2 A5 D3 NC D4 NC D5 A11 D6 A15 E1 A0 E2 DQ0 E3 DQ2 E4 DQ5 E5 DQ7 E6 A16 F1 CE# F2 DQ8 F3 DQ10 F4 DQ12 F5 DQ14 F6 G1 OE# G2 DQ9 G3 DQ11 G4 VCC G5 DQ13 G6 H1 VSS H2 DQ1 H3 DQ3 H4 DQ4 H5 DQ6 H6 VSS BYTE# DQ15/A-1 21523A-3 5 Am29LV400B ADVANCE INFORMATION Special Handling Instructions for Fine PItch Ball Grid Array (FBGA) Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package an d/or data integr ity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. PIN CONFIGURATION A0–A17 = 18 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY# VCC = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) = Selects 8-bit or 16-bit mode = Chip enable = Output enable = Write enable = Hardware reset pin, active low = Ready/Busy# output = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Device ground = Pin not connected internally LOGIC SYMBOL 18 A0–A17 DQ0–DQ15 (A-1) CE# OE# WE# RESET# BYTE# RY/BY# 16 or 8 21523A-4 VSS NC 1/29/98 Am29LV400B 6 ADVANCE INFORMATION ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am29LV400B T 70R E C OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information) TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) WA = 48-ball Fine Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 8 mm package SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector DEVICE NUMBER/DESCRIPTION Am29LV400B 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase Valid Combinations Valid Combinations Am29LV400BT70R, Am29LV400BB70R Am29LV400BT80, Am29LV400BB80 Am29LV400BT90, Am29LV400BB90 Am29LV400BT120, Am29LV400BB120 Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. EC, EI, FC, FI, SC, SI, WAC Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. EC, EI, EE, FC, FI, FE, SC, SI, SE, WAC, WAI, WAE 7 Am29LV400B